1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only 25f60ed0dSThierry Reding /* 35f60ed0dSThierry Reding * Copyright (C) 2013 Avionic Design GmbH 45f60ed0dSThierry Reding * Copyright (C) 2013 NVIDIA Corporation 55f60ed0dSThierry Reding */ 65f60ed0dSThierry Reding 75f60ed0dSThierry Reding #include <linux/clk.h> 8*2421b20dSDmitry Osipenko #include <linux/delay.h> 95f60ed0dSThierry Reding #include <linux/host1x.h> 10c9ac5217SDmitry Osipenko #include <linux/iommu.h> 115f60ed0dSThierry Reding #include <linux/module.h> 1233f150eaSThierry Reding #include <linux/of_device.h> 135f60ed0dSThierry Reding #include <linux/platform_device.h> 14*2421b20dSDmitry Osipenko #include <linux/pm_domain.h> 15*2421b20dSDmitry Osipenko #include <linux/pm_opp.h> 16*2421b20dSDmitry Osipenko #include <linux/pm_runtime.h> 17ca48080aSStephen Warren #include <linux/reset.h> 18306a7f91SThierry Reding 19*2421b20dSDmitry Osipenko #include <soc/tegra/common.h> 207232398aSThierry Reding #include <soc/tegra/pmc.h> 215f60ed0dSThierry Reding 225f60ed0dSThierry Reding #include "drm.h" 235f60ed0dSThierry Reding #include "gem.h" 245f60ed0dSThierry Reding #include "gr3d.h" 255f60ed0dSThierry Reding 26*2421b20dSDmitry Osipenko enum { 27*2421b20dSDmitry Osipenko RST_MC, 28*2421b20dSDmitry Osipenko RST_GR3D, 29*2421b20dSDmitry Osipenko RST_MC2, 30*2421b20dSDmitry Osipenko RST_GR3D2, 31*2421b20dSDmitry Osipenko RST_GR3D_MAX, 32*2421b20dSDmitry Osipenko }; 33*2421b20dSDmitry Osipenko 3433f150eaSThierry Reding struct gr3d_soc { 3533f150eaSThierry Reding unsigned int version; 36*2421b20dSDmitry Osipenko unsigned int num_clocks; 37*2421b20dSDmitry Osipenko unsigned int num_resets; 3833f150eaSThierry Reding }; 3933f150eaSThierry Reding 405f60ed0dSThierry Reding struct gr3d { 415f60ed0dSThierry Reding struct tegra_drm_client client; 425f60ed0dSThierry Reding struct host1x_channel *channel; 435f60ed0dSThierry Reding 4433f150eaSThierry Reding const struct gr3d_soc *soc; 45*2421b20dSDmitry Osipenko struct clk_bulk_data *clocks; 46*2421b20dSDmitry Osipenko unsigned int nclocks; 47*2421b20dSDmitry Osipenko struct reset_control_bulk_data resets[RST_GR3D_MAX]; 48*2421b20dSDmitry Osipenko unsigned int nresets; 4933f150eaSThierry Reding 505f60ed0dSThierry Reding DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS); 515f60ed0dSThierry Reding }; 525f60ed0dSThierry Reding 535f60ed0dSThierry Reding static inline struct gr3d *to_gr3d(struct tegra_drm_client *client) 545f60ed0dSThierry Reding { 555f60ed0dSThierry Reding return container_of(client, struct gr3d, client); 565f60ed0dSThierry Reding } 575f60ed0dSThierry Reding 585f60ed0dSThierry Reding static int gr3d_init(struct host1x_client *client) 595f60ed0dSThierry Reding { 605f60ed0dSThierry Reding struct tegra_drm_client *drm = host1x_to_drm_client(client); 61608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 62977386a0SThierry Reding unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 635f60ed0dSThierry Reding struct gr3d *gr3d = to_gr3d(drm); 64c9ac5217SDmitry Osipenko int err; 655f60ed0dSThierry Reding 66caccddcfSThierry Reding gr3d->channel = host1x_channel_request(client); 675f60ed0dSThierry Reding if (!gr3d->channel) 685f60ed0dSThierry Reding return -ENOMEM; 695f60ed0dSThierry Reding 70617dd7ccSThierry Reding client->syncpts[0] = host1x_syncpt_request(client, flags); 715f60ed0dSThierry Reding if (!client->syncpts[0]) { 72230630bdSThierry Reding err = -ENOMEM; 73230630bdSThierry Reding dev_err(client->dev, "failed to request syncpoint: %d\n", err); 74230630bdSThierry Reding goto put; 755f60ed0dSThierry Reding } 765f60ed0dSThierry Reding 777edd7961SThierry Reding err = host1x_client_iommu_attach(client); 78aacdf198SThierry Reding if (err < 0) { 790c407de5SThierry Reding dev_err(client->dev, "failed to attach to domain: %d\n", err); 80230630bdSThierry Reding goto free; 81c9ac5217SDmitry Osipenko } 82c9ac5217SDmitry Osipenko 83*2421b20dSDmitry Osipenko pm_runtime_enable(client->dev); 84*2421b20dSDmitry Osipenko pm_runtime_use_autosuspend(client->dev); 85*2421b20dSDmitry Osipenko pm_runtime_set_autosuspend_delay(client->dev, 200); 86*2421b20dSDmitry Osipenko 87230630bdSThierry Reding err = tegra_drm_register_client(dev->dev_private, drm); 88230630bdSThierry Reding if (err < 0) { 89230630bdSThierry Reding dev_err(client->dev, "failed to register client: %d\n", err); 90*2421b20dSDmitry Osipenko goto disable_rpm; 91230630bdSThierry Reding } 92230630bdSThierry Reding 93230630bdSThierry Reding return 0; 94230630bdSThierry Reding 95*2421b20dSDmitry Osipenko disable_rpm: 96*2421b20dSDmitry Osipenko pm_runtime_dont_use_autosuspend(client->dev); 97*2421b20dSDmitry Osipenko pm_runtime_force_suspend(client->dev); 98*2421b20dSDmitry Osipenko 99aacdf198SThierry Reding host1x_client_iommu_detach(client); 100230630bdSThierry Reding free: 1012aed4f5aSMikko Perttunen host1x_syncpt_put(client->syncpts[0]); 102230630bdSThierry Reding put: 103230630bdSThierry Reding host1x_channel_put(gr3d->channel); 104230630bdSThierry Reding return err; 1055f60ed0dSThierry Reding } 1065f60ed0dSThierry Reding 1075f60ed0dSThierry Reding static int gr3d_exit(struct host1x_client *client) 1085f60ed0dSThierry Reding { 1095f60ed0dSThierry Reding struct tegra_drm_client *drm = host1x_to_drm_client(client); 110608f43adSThierry Reding struct drm_device *dev = dev_get_drvdata(client->host); 1115f60ed0dSThierry Reding struct gr3d *gr3d = to_gr3d(drm); 1125f60ed0dSThierry Reding int err; 1135f60ed0dSThierry Reding 1149910f5c4SThierry Reding err = tegra_drm_unregister_client(dev->dev_private, drm); 1155f60ed0dSThierry Reding if (err < 0) 1165f60ed0dSThierry Reding return err; 1175f60ed0dSThierry Reding 118*2421b20dSDmitry Osipenko pm_runtime_dont_use_autosuspend(client->dev); 119*2421b20dSDmitry Osipenko pm_runtime_force_suspend(client->dev); 120*2421b20dSDmitry Osipenko 121aacdf198SThierry Reding host1x_client_iommu_detach(client); 1222aed4f5aSMikko Perttunen host1x_syncpt_put(client->syncpts[0]); 1238474b025SMikko Perttunen host1x_channel_put(gr3d->channel); 1245f60ed0dSThierry Reding 125*2421b20dSDmitry Osipenko gr3d->channel = NULL; 126*2421b20dSDmitry Osipenko 1275f60ed0dSThierry Reding return 0; 1285f60ed0dSThierry Reding } 1295f60ed0dSThierry Reding 1305f60ed0dSThierry Reding static const struct host1x_client_ops gr3d_client_ops = { 1315f60ed0dSThierry Reding .init = gr3d_init, 1325f60ed0dSThierry Reding .exit = gr3d_exit, 1335f60ed0dSThierry Reding }; 1345f60ed0dSThierry Reding 1355f60ed0dSThierry Reding static int gr3d_open_channel(struct tegra_drm_client *client, 1365f60ed0dSThierry Reding struct tegra_drm_context *context) 1375f60ed0dSThierry Reding { 1385f60ed0dSThierry Reding struct gr3d *gr3d = to_gr3d(client); 139*2421b20dSDmitry Osipenko int err; 140*2421b20dSDmitry Osipenko 141*2421b20dSDmitry Osipenko err = pm_runtime_resume_and_get(client->base.dev); 142*2421b20dSDmitry Osipenko if (err) 143*2421b20dSDmitry Osipenko return err; 1445f60ed0dSThierry Reding 1455f60ed0dSThierry Reding context->channel = host1x_channel_get(gr3d->channel); 146*2421b20dSDmitry Osipenko if (!context->channel) { 147*2421b20dSDmitry Osipenko pm_runtime_put(client->base.dev); 1485f60ed0dSThierry Reding return -ENOMEM; 149*2421b20dSDmitry Osipenko } 1505f60ed0dSThierry Reding 1515f60ed0dSThierry Reding return 0; 1525f60ed0dSThierry Reding } 1535f60ed0dSThierry Reding 1545f60ed0dSThierry Reding static void gr3d_close_channel(struct tegra_drm_context *context) 1555f60ed0dSThierry Reding { 1565f60ed0dSThierry Reding host1x_channel_put(context->channel); 157*2421b20dSDmitry Osipenko pm_runtime_put(context->client->base.dev); 1585f60ed0dSThierry Reding } 1595f60ed0dSThierry Reding 1605f60ed0dSThierry Reding static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset) 1615f60ed0dSThierry Reding { 1625f60ed0dSThierry Reding struct gr3d *gr3d = dev_get_drvdata(dev); 1635f60ed0dSThierry Reding 1645f60ed0dSThierry Reding switch (class) { 1655f60ed0dSThierry Reding case HOST1X_CLASS_HOST1X: 1665f60ed0dSThierry Reding if (offset == 0x2b) 1675f60ed0dSThierry Reding return 1; 1685f60ed0dSThierry Reding 1695f60ed0dSThierry Reding break; 1705f60ed0dSThierry Reding 1715f60ed0dSThierry Reding case HOST1X_CLASS_GR3D: 1725f60ed0dSThierry Reding if (offset >= GR3D_NUM_REGS) 1735f60ed0dSThierry Reding break; 1745f60ed0dSThierry Reding 1755f60ed0dSThierry Reding if (test_bit(offset, gr3d->addr_regs)) 1765f60ed0dSThierry Reding return 1; 1775f60ed0dSThierry Reding 1785f60ed0dSThierry Reding break; 1795f60ed0dSThierry Reding } 1805f60ed0dSThierry Reding 1815f60ed0dSThierry Reding return 0; 1825f60ed0dSThierry Reding } 1835f60ed0dSThierry Reding 1845f60ed0dSThierry Reding static const struct tegra_drm_client_ops gr3d_ops = { 1855f60ed0dSThierry Reding .open_channel = gr3d_open_channel, 1865f60ed0dSThierry Reding .close_channel = gr3d_close_channel, 1875f60ed0dSThierry Reding .is_addr_reg = gr3d_is_addr_reg, 1885f60ed0dSThierry Reding .submit = tegra_drm_submit, 1895f60ed0dSThierry Reding }; 1905f60ed0dSThierry Reding 19133f150eaSThierry Reding static const struct gr3d_soc tegra20_gr3d_soc = { 19233f150eaSThierry Reding .version = 0x20, 193*2421b20dSDmitry Osipenko .num_clocks = 1, 194*2421b20dSDmitry Osipenko .num_resets = 2, 19533f150eaSThierry Reding }; 19633f150eaSThierry Reding 19733f150eaSThierry Reding static const struct gr3d_soc tegra30_gr3d_soc = { 19833f150eaSThierry Reding .version = 0x30, 199*2421b20dSDmitry Osipenko .num_clocks = 2, 200*2421b20dSDmitry Osipenko .num_resets = 4, 20133f150eaSThierry Reding }; 20233f150eaSThierry Reding 20333f150eaSThierry Reding static const struct gr3d_soc tegra114_gr3d_soc = { 20433f150eaSThierry Reding .version = 0x35, 205*2421b20dSDmitry Osipenko .num_clocks = 1, 206*2421b20dSDmitry Osipenko .num_resets = 2, 20733f150eaSThierry Reding }; 20833f150eaSThierry Reding 2095f60ed0dSThierry Reding static const struct of_device_id tegra_gr3d_match[] = { 21033f150eaSThierry Reding { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc }, 21133f150eaSThierry Reding { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc }, 21233f150eaSThierry Reding { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc }, 2135f60ed0dSThierry Reding { } 2145f60ed0dSThierry Reding }; 215ef70728cSStephen Warren MODULE_DEVICE_TABLE(of, tegra_gr3d_match); 2165f60ed0dSThierry Reding 2175f60ed0dSThierry Reding static const u32 gr3d_addr_regs[] = { 2185f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 0), 2195f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 1), 2205f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 2), 2215f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 3), 2225f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 4), 2235f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 5), 2245f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 6), 2255f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 7), 2265f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 8), 2275f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE( 9), 2285f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(10), 2295f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(11), 2305f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(12), 2315f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(13), 2325f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(14), 2335f60ed0dSThierry Reding GR3D_IDX_ATTRIBUTE(15), 2345f60ed0dSThierry Reding GR3D_IDX_INDEX_BASE, 2355f60ed0dSThierry Reding GR3D_QR_ZTAG_ADDR, 2365f60ed0dSThierry Reding GR3D_QR_CTAG_ADDR, 2375f60ed0dSThierry Reding GR3D_QR_CZ_ADDR, 2385f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 0), 2395f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 1), 2405f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 2), 2415f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 3), 2425f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 4), 2435f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 5), 2445f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 6), 2455f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 7), 2465f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 8), 2475f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR( 9), 2485f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(10), 2495f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(11), 2505f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(12), 2515f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(13), 2525f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(14), 2535f60ed0dSThierry Reding GR3D_TEX_TEX_ADDR(15), 2545f60ed0dSThierry Reding GR3D_DW_MEMORY_OUTPUT_ADDRESS, 2555f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 0), 2565f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 1), 2575f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 2), 2585f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 3), 2595f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 4), 2605f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 5), 2615f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 6), 2625f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 7), 2635f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 8), 2645f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR( 9), 2655f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(10), 2665f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(11), 2675f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(12), 2685f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(13), 2695f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(14), 2705f60ed0dSThierry Reding GR3D_GLOBAL_SURFADDR(15), 2715f60ed0dSThierry Reding GR3D_GLOBAL_SPILLSURFADDR, 2725f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 0), 2735f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 1), 2745f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 2), 2755f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 3), 2765f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 4), 2775f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 5), 2785f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 6), 2795f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 7), 2805f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 8), 2815f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR( 9), 2825f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(10), 2835f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(11), 2845f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(12), 2855f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(13), 2865f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(14), 2875f60ed0dSThierry Reding GR3D_GLOBAL_SURFOVERADDR(15), 2885f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 0), 2895f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 1), 2905f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 2), 2915f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 3), 2925f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 4), 2935f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 5), 2945f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 6), 2955f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 7), 2965f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 8), 2975f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR( 9), 2985f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(10), 2995f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(11), 3005f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(12), 3015f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(13), 3025f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(14), 3035f60ed0dSThierry Reding GR3D_GLOBAL_SAMP01SURFADDR(15), 3045f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 0), 3055f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 1), 3065f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 2), 3075f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 3), 3085f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 4), 3095f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 5), 3105f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 6), 3115f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 7), 3125f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 8), 3135f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR( 9), 3145f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(10), 3155f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(11), 3165f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(12), 3175f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(13), 3185f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(14), 3195f60ed0dSThierry Reding GR3D_GLOBAL_SAMP23SURFADDR(15), 3205f60ed0dSThierry Reding }; 3215f60ed0dSThierry Reding 322*2421b20dSDmitry Osipenko static int gr3d_power_up_legacy_domain(struct device *dev, const char *name, 323*2421b20dSDmitry Osipenko unsigned int id) 324*2421b20dSDmitry Osipenko { 325*2421b20dSDmitry Osipenko struct gr3d *gr3d = dev_get_drvdata(dev); 326*2421b20dSDmitry Osipenko struct reset_control *reset; 327*2421b20dSDmitry Osipenko struct clk *clk; 328*2421b20dSDmitry Osipenko unsigned int i; 329*2421b20dSDmitry Osipenko int err; 330*2421b20dSDmitry Osipenko 331*2421b20dSDmitry Osipenko /* 332*2421b20dSDmitry Osipenko * Tegra20 device-tree doesn't specify 3d clock name and there is only 333*2421b20dSDmitry Osipenko * one clock for Tegra20. Tegra30+ device-trees always specified names 334*2421b20dSDmitry Osipenko * for the clocks. 335*2421b20dSDmitry Osipenko */ 336*2421b20dSDmitry Osipenko if (gr3d->nclocks == 1) { 337*2421b20dSDmitry Osipenko if (id == TEGRA_POWERGATE_3D1) 338*2421b20dSDmitry Osipenko return 0; 339*2421b20dSDmitry Osipenko 340*2421b20dSDmitry Osipenko clk = gr3d->clocks[0].clk; 341*2421b20dSDmitry Osipenko } else { 342*2421b20dSDmitry Osipenko for (i = 0; i < gr3d->nclocks; i++) { 343*2421b20dSDmitry Osipenko if (WARN_ON(!gr3d->clocks[i].id)) 344*2421b20dSDmitry Osipenko continue; 345*2421b20dSDmitry Osipenko 346*2421b20dSDmitry Osipenko if (!strcmp(gr3d->clocks[i].id, name)) { 347*2421b20dSDmitry Osipenko clk = gr3d->clocks[i].clk; 348*2421b20dSDmitry Osipenko break; 349*2421b20dSDmitry Osipenko } 350*2421b20dSDmitry Osipenko } 351*2421b20dSDmitry Osipenko 352*2421b20dSDmitry Osipenko if (WARN_ON(i == gr3d->nclocks)) 353*2421b20dSDmitry Osipenko return -EINVAL; 354*2421b20dSDmitry Osipenko } 355*2421b20dSDmitry Osipenko 356*2421b20dSDmitry Osipenko /* 357*2421b20dSDmitry Osipenko * We use array of resets, which includes MC resets, and MC 358*2421b20dSDmitry Osipenko * reset shouldn't be asserted while hardware is gated because 359*2421b20dSDmitry Osipenko * MC flushing will fail for gated hardware. Hence for legacy 360*2421b20dSDmitry Osipenko * PD we request the individual reset separately. 361*2421b20dSDmitry Osipenko */ 362*2421b20dSDmitry Osipenko reset = reset_control_get_exclusive_released(dev, name); 363*2421b20dSDmitry Osipenko if (IS_ERR(reset)) 364*2421b20dSDmitry Osipenko return PTR_ERR(reset); 365*2421b20dSDmitry Osipenko 366*2421b20dSDmitry Osipenko err = reset_control_acquire(reset); 367*2421b20dSDmitry Osipenko if (err) { 368*2421b20dSDmitry Osipenko dev_err(dev, "failed to acquire %s reset: %d\n", name, err); 369*2421b20dSDmitry Osipenko } else { 370*2421b20dSDmitry Osipenko err = tegra_powergate_sequence_power_up(id, clk, reset); 371*2421b20dSDmitry Osipenko reset_control_release(reset); 372*2421b20dSDmitry Osipenko } 373*2421b20dSDmitry Osipenko 374*2421b20dSDmitry Osipenko reset_control_put(reset); 375*2421b20dSDmitry Osipenko if (err) 376*2421b20dSDmitry Osipenko return err; 377*2421b20dSDmitry Osipenko 378*2421b20dSDmitry Osipenko /* 379*2421b20dSDmitry Osipenko * tegra_powergate_sequence_power_up() leaves clocks enabled, 380*2421b20dSDmitry Osipenko * while GENPD not. Hence keep clock-enable balanced. 381*2421b20dSDmitry Osipenko */ 382*2421b20dSDmitry Osipenko clk_disable_unprepare(clk); 383*2421b20dSDmitry Osipenko 384*2421b20dSDmitry Osipenko return 0; 385*2421b20dSDmitry Osipenko } 386*2421b20dSDmitry Osipenko 387*2421b20dSDmitry Osipenko static void gr3d_del_link(void *link) 388*2421b20dSDmitry Osipenko { 389*2421b20dSDmitry Osipenko device_link_del(link); 390*2421b20dSDmitry Osipenko } 391*2421b20dSDmitry Osipenko 392*2421b20dSDmitry Osipenko static int gr3d_init_power(struct device *dev, struct gr3d *gr3d) 393*2421b20dSDmitry Osipenko { 394*2421b20dSDmitry Osipenko static const char * const opp_genpd_names[] = { "3d0", "3d1", NULL }; 395*2421b20dSDmitry Osipenko const u32 link_flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME; 396*2421b20dSDmitry Osipenko struct device **opp_virt_devs, *pd_dev; 397*2421b20dSDmitry Osipenko struct device_link *link; 398*2421b20dSDmitry Osipenko unsigned int i; 399*2421b20dSDmitry Osipenko int err; 400*2421b20dSDmitry Osipenko 401*2421b20dSDmitry Osipenko err = of_count_phandle_with_args(dev->of_node, "power-domains", 402*2421b20dSDmitry Osipenko "#power-domain-cells"); 403*2421b20dSDmitry Osipenko if (err < 0) { 404*2421b20dSDmitry Osipenko if (err != -ENOENT) 405*2421b20dSDmitry Osipenko return err; 406*2421b20dSDmitry Osipenko 407*2421b20dSDmitry Osipenko /* 408*2421b20dSDmitry Osipenko * Older device-trees don't use GENPD. In this case we should 409*2421b20dSDmitry Osipenko * toggle power domain manually. 410*2421b20dSDmitry Osipenko */ 411*2421b20dSDmitry Osipenko err = gr3d_power_up_legacy_domain(dev, "3d", 412*2421b20dSDmitry Osipenko TEGRA_POWERGATE_3D); 413*2421b20dSDmitry Osipenko if (err) 414*2421b20dSDmitry Osipenko return err; 415*2421b20dSDmitry Osipenko 416*2421b20dSDmitry Osipenko err = gr3d_power_up_legacy_domain(dev, "3d2", 417*2421b20dSDmitry Osipenko TEGRA_POWERGATE_3D1); 418*2421b20dSDmitry Osipenko if (err) 419*2421b20dSDmitry Osipenko return err; 420*2421b20dSDmitry Osipenko 421*2421b20dSDmitry Osipenko return 0; 422*2421b20dSDmitry Osipenko } 423*2421b20dSDmitry Osipenko 424*2421b20dSDmitry Osipenko /* 425*2421b20dSDmitry Osipenko * The PM domain core automatically attaches a single power domain, 426*2421b20dSDmitry Osipenko * otherwise it skips attaching completely. We have a single domain 427*2421b20dSDmitry Osipenko * on Tegra20 and two domains on Tegra30+. 428*2421b20dSDmitry Osipenko */ 429*2421b20dSDmitry Osipenko if (dev->pm_domain) 430*2421b20dSDmitry Osipenko return 0; 431*2421b20dSDmitry Osipenko 432*2421b20dSDmitry Osipenko err = devm_pm_opp_attach_genpd(dev, opp_genpd_names, &opp_virt_devs); 433*2421b20dSDmitry Osipenko if (err) 434*2421b20dSDmitry Osipenko return err; 435*2421b20dSDmitry Osipenko 436*2421b20dSDmitry Osipenko for (i = 0; opp_genpd_names[i]; i++) { 437*2421b20dSDmitry Osipenko pd_dev = opp_virt_devs[i]; 438*2421b20dSDmitry Osipenko if (!pd_dev) { 439*2421b20dSDmitry Osipenko dev_err(dev, "failed to get %s power domain\n", 440*2421b20dSDmitry Osipenko opp_genpd_names[i]); 441*2421b20dSDmitry Osipenko return -EINVAL; 442*2421b20dSDmitry Osipenko } 443*2421b20dSDmitry Osipenko 444*2421b20dSDmitry Osipenko link = device_link_add(dev, pd_dev, link_flags); 445*2421b20dSDmitry Osipenko if (!link) { 446*2421b20dSDmitry Osipenko dev_err(dev, "failed to link to %s\n", dev_name(pd_dev)); 447*2421b20dSDmitry Osipenko return -EINVAL; 448*2421b20dSDmitry Osipenko } 449*2421b20dSDmitry Osipenko 450*2421b20dSDmitry Osipenko err = devm_add_action_or_reset(dev, gr3d_del_link, link); 451*2421b20dSDmitry Osipenko if (err) 452*2421b20dSDmitry Osipenko return err; 453*2421b20dSDmitry Osipenko } 454*2421b20dSDmitry Osipenko 455*2421b20dSDmitry Osipenko return 0; 456*2421b20dSDmitry Osipenko } 457*2421b20dSDmitry Osipenko 458*2421b20dSDmitry Osipenko static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d) 459*2421b20dSDmitry Osipenko { 460*2421b20dSDmitry Osipenko int err; 461*2421b20dSDmitry Osipenko 462*2421b20dSDmitry Osipenko err = devm_clk_bulk_get_all(dev, &gr3d->clocks); 463*2421b20dSDmitry Osipenko if (err < 0) { 464*2421b20dSDmitry Osipenko dev_err(dev, "failed to get clock: %d\n", err); 465*2421b20dSDmitry Osipenko return err; 466*2421b20dSDmitry Osipenko } 467*2421b20dSDmitry Osipenko gr3d->nclocks = err; 468*2421b20dSDmitry Osipenko 469*2421b20dSDmitry Osipenko if (gr3d->nclocks != gr3d->soc->num_clocks) { 470*2421b20dSDmitry Osipenko dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks); 471*2421b20dSDmitry Osipenko return -ENOENT; 472*2421b20dSDmitry Osipenko } 473*2421b20dSDmitry Osipenko 474*2421b20dSDmitry Osipenko return 0; 475*2421b20dSDmitry Osipenko } 476*2421b20dSDmitry Osipenko 477*2421b20dSDmitry Osipenko static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d) 478*2421b20dSDmitry Osipenko { 479*2421b20dSDmitry Osipenko int err; 480*2421b20dSDmitry Osipenko 481*2421b20dSDmitry Osipenko gr3d->resets[RST_MC].id = "mc"; 482*2421b20dSDmitry Osipenko gr3d->resets[RST_MC2].id = "mc2"; 483*2421b20dSDmitry Osipenko gr3d->resets[RST_GR3D].id = "3d"; 484*2421b20dSDmitry Osipenko gr3d->resets[RST_GR3D2].id = "3d2"; 485*2421b20dSDmitry Osipenko gr3d->nresets = gr3d->soc->num_resets; 486*2421b20dSDmitry Osipenko 487*2421b20dSDmitry Osipenko err = devm_reset_control_bulk_get_optional_exclusive_released( 488*2421b20dSDmitry Osipenko dev, gr3d->nresets, gr3d->resets); 489*2421b20dSDmitry Osipenko if (err) { 490*2421b20dSDmitry Osipenko dev_err(dev, "failed to get reset: %d\n", err); 491*2421b20dSDmitry Osipenko return err; 492*2421b20dSDmitry Osipenko } 493*2421b20dSDmitry Osipenko 494*2421b20dSDmitry Osipenko if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) || 495*2421b20dSDmitry Osipenko WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4)) 496*2421b20dSDmitry Osipenko return -ENOENT; 497*2421b20dSDmitry Osipenko 498*2421b20dSDmitry Osipenko return 0; 499*2421b20dSDmitry Osipenko } 500*2421b20dSDmitry Osipenko 5015f60ed0dSThierry Reding static int gr3d_probe(struct platform_device *pdev) 5025f60ed0dSThierry Reding { 5035f60ed0dSThierry Reding struct host1x_syncpt **syncpts; 5045f60ed0dSThierry Reding struct gr3d *gr3d; 5055f60ed0dSThierry Reding unsigned int i; 5065f60ed0dSThierry Reding int err; 5075f60ed0dSThierry Reding 5085f60ed0dSThierry Reding gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL); 5095f60ed0dSThierry Reding if (!gr3d) 5105f60ed0dSThierry Reding return -ENOMEM; 5115f60ed0dSThierry Reding 512*2421b20dSDmitry Osipenko platform_set_drvdata(pdev, gr3d); 513*2421b20dSDmitry Osipenko 51433f150eaSThierry Reding gr3d->soc = of_device_get_match_data(&pdev->dev); 51533f150eaSThierry Reding 5165f60ed0dSThierry Reding syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL); 5175f60ed0dSThierry Reding if (!syncpts) 5185f60ed0dSThierry Reding return -ENOMEM; 5195f60ed0dSThierry Reding 520*2421b20dSDmitry Osipenko err = gr3d_get_clocks(&pdev->dev, gr3d); 521*2421b20dSDmitry Osipenko if (err) 5225f60ed0dSThierry Reding return err; 5235f60ed0dSThierry Reding 524*2421b20dSDmitry Osipenko err = gr3d_get_resets(&pdev->dev, gr3d); 525*2421b20dSDmitry Osipenko if (err) 5265f60ed0dSThierry Reding return err; 527*2421b20dSDmitry Osipenko 528*2421b20dSDmitry Osipenko err = gr3d_init_power(&pdev->dev, gr3d); 529*2421b20dSDmitry Osipenko if (err) 530*2421b20dSDmitry Osipenko return err; 5315f60ed0dSThierry Reding 5325f60ed0dSThierry Reding INIT_LIST_HEAD(&gr3d->client.base.list); 5335f60ed0dSThierry Reding gr3d->client.base.ops = &gr3d_client_ops; 5345f60ed0dSThierry Reding gr3d->client.base.dev = &pdev->dev; 5355f60ed0dSThierry Reding gr3d->client.base.class = HOST1X_CLASS_GR3D; 5365f60ed0dSThierry Reding gr3d->client.base.syncpts = syncpts; 5375f60ed0dSThierry Reding gr3d->client.base.num_syncpts = 1; 5385f60ed0dSThierry Reding 5395f60ed0dSThierry Reding INIT_LIST_HEAD(&gr3d->client.list); 54033f150eaSThierry Reding gr3d->client.version = gr3d->soc->version; 5415f60ed0dSThierry Reding gr3d->client.ops = &gr3d_ops; 5425f60ed0dSThierry Reding 543*2421b20dSDmitry Osipenko err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 544*2421b20dSDmitry Osipenko if (err) 545*2421b20dSDmitry Osipenko return err; 546*2421b20dSDmitry Osipenko 5475f60ed0dSThierry Reding err = host1x_client_register(&gr3d->client.base); 5485f60ed0dSThierry Reding if (err < 0) { 5495f60ed0dSThierry Reding dev_err(&pdev->dev, "failed to register host1x client: %d\n", 5505f60ed0dSThierry Reding err); 5515f60ed0dSThierry Reding return err; 5525f60ed0dSThierry Reding } 5535f60ed0dSThierry Reding 5545f60ed0dSThierry Reding /* initialize address register map */ 5555f60ed0dSThierry Reding for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++) 5565f60ed0dSThierry Reding set_bit(gr3d_addr_regs[i], gr3d->addr_regs); 5575f60ed0dSThierry Reding 5585f60ed0dSThierry Reding return 0; 5595f60ed0dSThierry Reding } 5605f60ed0dSThierry Reding 5615f60ed0dSThierry Reding static int gr3d_remove(struct platform_device *pdev) 5625f60ed0dSThierry Reding { 5635f60ed0dSThierry Reding struct gr3d *gr3d = platform_get_drvdata(pdev); 5645f60ed0dSThierry Reding int err; 5655f60ed0dSThierry Reding 5665f60ed0dSThierry Reding err = host1x_client_unregister(&gr3d->client.base); 5675f60ed0dSThierry Reding if (err < 0) { 5685f60ed0dSThierry Reding dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 5695f60ed0dSThierry Reding err); 5705f60ed0dSThierry Reding return err; 5715f60ed0dSThierry Reding } 5725f60ed0dSThierry Reding 573*2421b20dSDmitry Osipenko return 0; 5745f60ed0dSThierry Reding } 5755f60ed0dSThierry Reding 576*2421b20dSDmitry Osipenko static int __maybe_unused gr3d_runtime_suspend(struct device *dev) 577*2421b20dSDmitry Osipenko { 578*2421b20dSDmitry Osipenko struct gr3d *gr3d = dev_get_drvdata(dev); 579*2421b20dSDmitry Osipenko int err; 580*2421b20dSDmitry Osipenko 581*2421b20dSDmitry Osipenko host1x_channel_stop(gr3d->channel); 582*2421b20dSDmitry Osipenko 583*2421b20dSDmitry Osipenko err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets); 584*2421b20dSDmitry Osipenko if (err) { 585*2421b20dSDmitry Osipenko dev_err(dev, "failed to assert reset: %d\n", err); 586*2421b20dSDmitry Osipenko return err; 587*2421b20dSDmitry Osipenko } 588*2421b20dSDmitry Osipenko 589*2421b20dSDmitry Osipenko usleep_range(10, 20); 590*2421b20dSDmitry Osipenko 591*2421b20dSDmitry Osipenko /* 592*2421b20dSDmitry Osipenko * Older device-trees don't specify MC resets and power-gating can't 593*2421b20dSDmitry Osipenko * be done safely in that case. Hence we will keep the power ungated 594*2421b20dSDmitry Osipenko * for older DTBs. For newer DTBs, GENPD will perform the power-gating. 595*2421b20dSDmitry Osipenko */ 596*2421b20dSDmitry Osipenko 597*2421b20dSDmitry Osipenko clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 598*2421b20dSDmitry Osipenko reset_control_bulk_release(gr3d->nresets, gr3d->resets); 5995f60ed0dSThierry Reding 6005f60ed0dSThierry Reding return 0; 6015f60ed0dSThierry Reding } 6025f60ed0dSThierry Reding 603*2421b20dSDmitry Osipenko static int __maybe_unused gr3d_runtime_resume(struct device *dev) 604*2421b20dSDmitry Osipenko { 605*2421b20dSDmitry Osipenko struct gr3d *gr3d = dev_get_drvdata(dev); 606*2421b20dSDmitry Osipenko int err; 607*2421b20dSDmitry Osipenko 608*2421b20dSDmitry Osipenko err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets); 609*2421b20dSDmitry Osipenko if (err) { 610*2421b20dSDmitry Osipenko dev_err(dev, "failed to acquire reset: %d\n", err); 611*2421b20dSDmitry Osipenko return err; 612*2421b20dSDmitry Osipenko } 613*2421b20dSDmitry Osipenko 614*2421b20dSDmitry Osipenko err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks); 615*2421b20dSDmitry Osipenko if (err) { 616*2421b20dSDmitry Osipenko dev_err(dev, "failed to enable clock: %d\n", err); 617*2421b20dSDmitry Osipenko goto release_reset; 618*2421b20dSDmitry Osipenko } 619*2421b20dSDmitry Osipenko 620*2421b20dSDmitry Osipenko err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets); 621*2421b20dSDmitry Osipenko if (err) { 622*2421b20dSDmitry Osipenko dev_err(dev, "failed to deassert reset: %d\n", err); 623*2421b20dSDmitry Osipenko goto disable_clk; 624*2421b20dSDmitry Osipenko } 625*2421b20dSDmitry Osipenko 626*2421b20dSDmitry Osipenko return 0; 627*2421b20dSDmitry Osipenko 628*2421b20dSDmitry Osipenko disable_clk: 629*2421b20dSDmitry Osipenko clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks); 630*2421b20dSDmitry Osipenko release_reset: 631*2421b20dSDmitry Osipenko reset_control_bulk_release(gr3d->nresets, gr3d->resets); 632*2421b20dSDmitry Osipenko 633*2421b20dSDmitry Osipenko return err; 634*2421b20dSDmitry Osipenko } 635*2421b20dSDmitry Osipenko 636*2421b20dSDmitry Osipenko static const struct dev_pm_ops tegra_gr3d_pm = { 637*2421b20dSDmitry Osipenko SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL) 638*2421b20dSDmitry Osipenko SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 639*2421b20dSDmitry Osipenko pm_runtime_force_resume) 640*2421b20dSDmitry Osipenko }; 641*2421b20dSDmitry Osipenko 6425f60ed0dSThierry Reding struct platform_driver tegra_gr3d_driver = { 6435f60ed0dSThierry Reding .driver = { 6445f60ed0dSThierry Reding .name = "tegra-gr3d", 6455f60ed0dSThierry Reding .of_match_table = tegra_gr3d_match, 646*2421b20dSDmitry Osipenko .pm = &tegra_gr3d_pm, 6475f60ed0dSThierry Reding }, 6485f60ed0dSThierry Reding .probe = gr3d_probe, 6495f60ed0dSThierry Reding .remove = gr3d_remove, 6505f60ed0dSThierry Reding }; 651