1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2013, NVIDIA Corporation. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_device.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/reset.h> 13 14 #include <soc/tegra/common.h> 15 16 #include "drm.h" 17 #include "gem.h" 18 #include "gr2d.h" 19 20 enum { 21 RST_MC, 22 RST_GR2D, 23 RST_GR2D_MAX, 24 }; 25 26 struct gr2d_soc { 27 unsigned int version; 28 }; 29 30 struct gr2d { 31 struct tegra_drm_client client; 32 struct host1x_channel *channel; 33 struct clk *clk; 34 35 struct reset_control_bulk_data resets[RST_GR2D_MAX]; 36 unsigned int nresets; 37 38 const struct gr2d_soc *soc; 39 40 DECLARE_BITMAP(addr_regs, GR2D_NUM_REGS); 41 }; 42 43 static inline struct gr2d *to_gr2d(struct tegra_drm_client *client) 44 { 45 return container_of(client, struct gr2d, client); 46 } 47 48 static int gr2d_init(struct host1x_client *client) 49 { 50 struct tegra_drm_client *drm = host1x_to_drm_client(client); 51 struct drm_device *dev = dev_get_drvdata(client->host); 52 unsigned long flags = HOST1X_SYNCPT_HAS_BASE; 53 struct gr2d *gr2d = to_gr2d(drm); 54 int err; 55 56 gr2d->channel = host1x_channel_request(client); 57 if (!gr2d->channel) 58 return -ENOMEM; 59 60 client->syncpts[0] = host1x_syncpt_request(client, flags); 61 if (!client->syncpts[0]) { 62 err = -ENOMEM; 63 dev_err(client->dev, "failed to request syncpoint: %d\n", err); 64 goto put; 65 } 66 67 err = host1x_client_iommu_attach(client); 68 if (err < 0) { 69 dev_err(client->dev, "failed to attach to domain: %d\n", err); 70 goto free; 71 } 72 73 pm_runtime_enable(client->dev); 74 pm_runtime_use_autosuspend(client->dev); 75 pm_runtime_set_autosuspend_delay(client->dev, 200); 76 77 err = tegra_drm_register_client(dev->dev_private, drm); 78 if (err < 0) { 79 dev_err(client->dev, "failed to register client: %d\n", err); 80 goto disable_rpm; 81 } 82 83 return 0; 84 85 disable_rpm: 86 pm_runtime_dont_use_autosuspend(client->dev); 87 pm_runtime_force_suspend(client->dev); 88 89 host1x_client_iommu_detach(client); 90 free: 91 host1x_syncpt_put(client->syncpts[0]); 92 put: 93 host1x_channel_put(gr2d->channel); 94 return err; 95 } 96 97 static int gr2d_exit(struct host1x_client *client) 98 { 99 struct tegra_drm_client *drm = host1x_to_drm_client(client); 100 struct drm_device *dev = dev_get_drvdata(client->host); 101 struct tegra_drm *tegra = dev->dev_private; 102 struct gr2d *gr2d = to_gr2d(drm); 103 int err; 104 105 err = tegra_drm_unregister_client(tegra, drm); 106 if (err < 0) 107 return err; 108 109 pm_runtime_dont_use_autosuspend(client->dev); 110 pm_runtime_force_suspend(client->dev); 111 112 host1x_client_iommu_detach(client); 113 host1x_syncpt_put(client->syncpts[0]); 114 host1x_channel_put(gr2d->channel); 115 116 gr2d->channel = NULL; 117 118 return 0; 119 } 120 121 static const struct host1x_client_ops gr2d_client_ops = { 122 .init = gr2d_init, 123 .exit = gr2d_exit, 124 }; 125 126 static int gr2d_open_channel(struct tegra_drm_client *client, 127 struct tegra_drm_context *context) 128 { 129 struct gr2d *gr2d = to_gr2d(client); 130 131 context->channel = host1x_channel_get(gr2d->channel); 132 if (!context->channel) 133 return -ENOMEM; 134 135 return 0; 136 } 137 138 static void gr2d_close_channel(struct tegra_drm_context *context) 139 { 140 host1x_channel_put(context->channel); 141 } 142 143 static int gr2d_is_addr_reg(struct device *dev, u32 class, u32 offset) 144 { 145 struct gr2d *gr2d = dev_get_drvdata(dev); 146 147 switch (class) { 148 case HOST1X_CLASS_HOST1X: 149 if (offset == 0x2b) 150 return 1; 151 152 break; 153 154 case HOST1X_CLASS_GR2D: 155 case HOST1X_CLASS_GR2D_SB: 156 if (offset >= GR2D_NUM_REGS) 157 break; 158 159 if (test_bit(offset, gr2d->addr_regs)) 160 return 1; 161 162 break; 163 } 164 165 return 0; 166 } 167 168 static int gr2d_is_valid_class(u32 class) 169 { 170 return (class == HOST1X_CLASS_GR2D || 171 class == HOST1X_CLASS_GR2D_SB); 172 } 173 174 static const struct tegra_drm_client_ops gr2d_ops = { 175 .open_channel = gr2d_open_channel, 176 .close_channel = gr2d_close_channel, 177 .is_addr_reg = gr2d_is_addr_reg, 178 .is_valid_class = gr2d_is_valid_class, 179 .submit = tegra_drm_submit, 180 }; 181 182 static const struct gr2d_soc tegra20_gr2d_soc = { 183 .version = 0x20, 184 }; 185 186 static const struct gr2d_soc tegra30_gr2d_soc = { 187 .version = 0x30, 188 }; 189 190 static const struct gr2d_soc tegra114_gr2d_soc = { 191 .version = 0x35, 192 }; 193 194 static const struct of_device_id gr2d_match[] = { 195 { .compatible = "nvidia,tegra114-gr2d", .data = &tegra114_gr2d_soc }, 196 { .compatible = "nvidia,tegra30-gr2d", .data = &tegra30_gr2d_soc }, 197 { .compatible = "nvidia,tegra20-gr2d", .data = &tegra20_gr2d_soc }, 198 { }, 199 }; 200 MODULE_DEVICE_TABLE(of, gr2d_match); 201 202 static const u32 gr2d_addr_regs[] = { 203 GR2D_UA_BASE_ADDR, 204 GR2D_VA_BASE_ADDR, 205 GR2D_PAT_BASE_ADDR, 206 GR2D_DSTA_BASE_ADDR, 207 GR2D_DSTB_BASE_ADDR, 208 GR2D_DSTC_BASE_ADDR, 209 GR2D_SRCA_BASE_ADDR, 210 GR2D_SRCB_BASE_ADDR, 211 GR2D_PATBASE_ADDR, 212 GR2D_SRC_BASE_ADDR_SB, 213 GR2D_DSTA_BASE_ADDR_SB, 214 GR2D_DSTB_BASE_ADDR_SB, 215 GR2D_UA_BASE_ADDR_SB, 216 GR2D_VA_BASE_ADDR_SB, 217 }; 218 219 static int gr2d_get_resets(struct device *dev, struct gr2d *gr2d) 220 { 221 int err; 222 223 gr2d->resets[RST_MC].id = "mc"; 224 gr2d->resets[RST_GR2D].id = "2d"; 225 gr2d->nresets = RST_GR2D_MAX; 226 227 err = devm_reset_control_bulk_get_optional_exclusive_released( 228 dev, gr2d->nresets, gr2d->resets); 229 if (err) { 230 dev_err(dev, "failed to get reset: %d\n", err); 231 return err; 232 } 233 234 if (WARN_ON(!gr2d->resets[RST_GR2D].rstc)) 235 return -ENOENT; 236 237 return 0; 238 } 239 240 static int gr2d_probe(struct platform_device *pdev) 241 { 242 struct device *dev = &pdev->dev; 243 struct host1x_syncpt **syncpts; 244 struct gr2d *gr2d; 245 unsigned int i; 246 int err; 247 248 gr2d = devm_kzalloc(dev, sizeof(*gr2d), GFP_KERNEL); 249 if (!gr2d) 250 return -ENOMEM; 251 252 platform_set_drvdata(pdev, gr2d); 253 254 gr2d->soc = of_device_get_match_data(dev); 255 256 syncpts = devm_kzalloc(dev, sizeof(*syncpts), GFP_KERNEL); 257 if (!syncpts) 258 return -ENOMEM; 259 260 gr2d->clk = devm_clk_get(dev, NULL); 261 if (IS_ERR(gr2d->clk)) { 262 dev_err(dev, "cannot get clock\n"); 263 return PTR_ERR(gr2d->clk); 264 } 265 266 err = gr2d_get_resets(dev, gr2d); 267 if (err) 268 return err; 269 270 INIT_LIST_HEAD(&gr2d->client.base.list); 271 gr2d->client.base.ops = &gr2d_client_ops; 272 gr2d->client.base.dev = dev; 273 gr2d->client.base.class = HOST1X_CLASS_GR2D; 274 gr2d->client.base.syncpts = syncpts; 275 gr2d->client.base.num_syncpts = 1; 276 277 INIT_LIST_HEAD(&gr2d->client.list); 278 gr2d->client.version = gr2d->soc->version; 279 gr2d->client.ops = &gr2d_ops; 280 281 err = devm_tegra_core_dev_init_opp_table_common(dev); 282 if (err) 283 return err; 284 285 err = host1x_client_register(&gr2d->client.base); 286 if (err < 0) { 287 dev_err(dev, "failed to register host1x client: %d\n", err); 288 return err; 289 } 290 291 /* initialize address register map */ 292 for (i = 0; i < ARRAY_SIZE(gr2d_addr_regs); i++) 293 set_bit(gr2d_addr_regs[i], gr2d->addr_regs); 294 295 return 0; 296 } 297 298 static void gr2d_remove(struct platform_device *pdev) 299 { 300 struct gr2d *gr2d = platform_get_drvdata(pdev); 301 302 host1x_client_unregister(&gr2d->client.base); 303 } 304 305 static int __maybe_unused gr2d_runtime_suspend(struct device *dev) 306 { 307 struct gr2d *gr2d = dev_get_drvdata(dev); 308 int err; 309 310 host1x_channel_stop(gr2d->channel); 311 reset_control_bulk_release(gr2d->nresets, gr2d->resets); 312 313 /* 314 * GR2D module shouldn't be reset while hardware is idling, otherwise 315 * host1x's cmdproc will stuck on trying to access any G2 register 316 * after reset. GR2D module could be either hot-reset or reset after 317 * power-gating of the HEG partition. Hence we will put in reset only 318 * the memory client part of the module, the HEG GENPD will take care 319 * of resetting GR2D module across power-gating. 320 * 321 * On Tegra20 there is no HEG partition, but it's okay to have 322 * undetermined h/w state since userspace is expected to reprogram 323 * the state on each job submission anyways. 324 */ 325 err = reset_control_acquire(gr2d->resets[RST_MC].rstc); 326 if (err) { 327 dev_err(dev, "failed to acquire MC reset: %d\n", err); 328 goto acquire_reset; 329 } 330 331 err = reset_control_assert(gr2d->resets[RST_MC].rstc); 332 reset_control_release(gr2d->resets[RST_MC].rstc); 333 if (err) { 334 dev_err(dev, "failed to assert MC reset: %d\n", err); 335 goto acquire_reset; 336 } 337 338 clk_disable_unprepare(gr2d->clk); 339 340 return 0; 341 342 acquire_reset: 343 reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); 344 reset_control_bulk_deassert(gr2d->nresets, gr2d->resets); 345 346 return err; 347 } 348 349 static int __maybe_unused gr2d_runtime_resume(struct device *dev) 350 { 351 struct gr2d *gr2d = dev_get_drvdata(dev); 352 int err; 353 354 err = reset_control_bulk_acquire(gr2d->nresets, gr2d->resets); 355 if (err) { 356 dev_err(dev, "failed to acquire reset: %d\n", err); 357 return err; 358 } 359 360 err = clk_prepare_enable(gr2d->clk); 361 if (err) { 362 dev_err(dev, "failed to enable clock: %d\n", err); 363 goto release_reset; 364 } 365 366 usleep_range(2000, 4000); 367 368 /* this is a reset array which deasserts both 2D MC and 2D itself */ 369 err = reset_control_bulk_deassert(gr2d->nresets, gr2d->resets); 370 if (err) { 371 dev_err(dev, "failed to deassert reset: %d\n", err); 372 goto disable_clk; 373 } 374 375 return 0; 376 377 disable_clk: 378 clk_disable_unprepare(gr2d->clk); 379 release_reset: 380 reset_control_bulk_release(gr2d->nresets, gr2d->resets); 381 382 return err; 383 } 384 385 static const struct dev_pm_ops tegra_gr2d_pm = { 386 SET_RUNTIME_PM_OPS(gr2d_runtime_suspend, gr2d_runtime_resume, NULL) 387 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 388 pm_runtime_force_resume) 389 }; 390 391 struct platform_driver tegra_gr2d_driver = { 392 .driver = { 393 .name = "tegra-gr2d", 394 .of_match_table = gr2d_match, 395 .pm = &tegra_gr2d_pm, 396 }, 397 .probe = gr2d_probe, 398 .remove_new = gr2d_remove, 399 }; 400