1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/debugfs.h> 11 #include <linux/host1x.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_platform.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <linux/regulator/consumer.h> 20 21 #include <drm/drm_atomic_helper.h> 22 #include <drm/drm_mipi_dsi.h> 23 #include <drm/drm_panel.h> 24 25 #include <video/mipi_display.h> 26 27 #include "dc.h" 28 #include "drm.h" 29 #include "dsi.h" 30 #include "mipi-phy.h" 31 #include "trace.h" 32 33 struct tegra_dsi_state { 34 struct drm_connector_state base; 35 36 struct mipi_dphy_timing timing; 37 unsigned long period; 38 39 unsigned int vrefresh; 40 unsigned int lanes; 41 unsigned long pclk; 42 unsigned long bclk; 43 44 enum tegra_dsi_format format; 45 unsigned int mul; 46 unsigned int div; 47 }; 48 49 static inline struct tegra_dsi_state * 50 to_dsi_state(struct drm_connector_state *state) 51 { 52 return container_of(state, struct tegra_dsi_state, base); 53 } 54 55 struct tegra_dsi { 56 struct host1x_client client; 57 struct tegra_output output; 58 struct device *dev; 59 60 void __iomem *regs; 61 62 struct reset_control *rst; 63 struct clk *clk_parent; 64 struct clk *clk_lp; 65 struct clk *clk; 66 67 struct drm_info_list *debugfs_files; 68 69 unsigned long flags; 70 enum mipi_dsi_pixel_format format; 71 unsigned int lanes; 72 73 struct tegra_mipi_device *mipi; 74 struct mipi_dsi_host host; 75 76 struct regulator *vdd; 77 78 unsigned int video_fifo_depth; 79 unsigned int host_fifo_depth; 80 81 /* for ganged-mode support */ 82 struct tegra_dsi *master; 83 struct tegra_dsi *slave; 84 }; 85 86 static inline struct tegra_dsi * 87 host1x_client_to_dsi(struct host1x_client *client) 88 { 89 return container_of(client, struct tegra_dsi, client); 90 } 91 92 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 93 { 94 return container_of(host, struct tegra_dsi, host); 95 } 96 97 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 98 { 99 return container_of(output, struct tegra_dsi, output); 100 } 101 102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 103 { 104 return to_dsi_state(dsi->output.connector.state); 105 } 106 107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 108 { 109 u32 value = readl(dsi->regs + (offset << 2)); 110 111 trace_dsi_readl(dsi->dev, offset, value); 112 113 return value; 114 } 115 116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 117 unsigned int offset) 118 { 119 trace_dsi_writel(dsi->dev, offset, value); 120 writel(value, dsi->regs + (offset << 2)); 121 } 122 123 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 124 125 static const struct debugfs_reg32 tegra_dsi_regs[] = { 126 DEBUGFS_REG32(DSI_INCR_SYNCPT), 127 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 129 DEBUGFS_REG32(DSI_CTXSW), 130 DEBUGFS_REG32(DSI_RD_DATA), 131 DEBUGFS_REG32(DSI_WR_DATA), 132 DEBUGFS_REG32(DSI_POWER_CONTROL), 133 DEBUGFS_REG32(DSI_INT_ENABLE), 134 DEBUGFS_REG32(DSI_INT_STATUS), 135 DEBUGFS_REG32(DSI_INT_MASK), 136 DEBUGFS_REG32(DSI_HOST_CONTROL), 137 DEBUGFS_REG32(DSI_CONTROL), 138 DEBUGFS_REG32(DSI_SOL_DELAY), 139 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 140 DEBUGFS_REG32(DSI_TRIGGER), 141 DEBUGFS_REG32(DSI_TX_CRC), 142 DEBUGFS_REG32(DSI_STATUS), 143 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 144 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 152 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 153 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 154 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 155 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 156 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 157 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 158 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 159 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 160 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 161 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 162 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 163 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 164 DEBUGFS_REG32(DSI_DCS_CMDS), 165 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 166 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 167 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 168 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 169 DEBUGFS_REG32(DSI_PHY_TIMING_0), 170 DEBUGFS_REG32(DSI_PHY_TIMING_1), 171 DEBUGFS_REG32(DSI_PHY_TIMING_2), 172 DEBUGFS_REG32(DSI_BTA_TIMING), 173 DEBUGFS_REG32(DSI_TIMEOUT_0), 174 DEBUGFS_REG32(DSI_TIMEOUT_1), 175 DEBUGFS_REG32(DSI_TO_TALLY), 176 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 177 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 178 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 179 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 180 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 181 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 182 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 183 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 184 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 185 DEBUGFS_REG32(DSI_GANGED_MODE_START), 186 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 187 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 188 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 189 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 197 }; 198 199 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 200 { 201 struct drm_info_node *node = s->private; 202 struct tegra_dsi *dsi = node->info_ent->data; 203 struct drm_crtc *crtc = dsi->output.encoder.crtc; 204 struct drm_device *drm = node->minor->dev; 205 unsigned int i; 206 int err = 0; 207 208 drm_modeset_lock_all(drm); 209 210 if (!crtc || !crtc->state->active) { 211 err = -EBUSY; 212 goto unlock; 213 } 214 215 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 216 unsigned int offset = tegra_dsi_regs[i].offset; 217 218 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 219 offset, tegra_dsi_readl(dsi, offset)); 220 } 221 222 unlock: 223 drm_modeset_unlock_all(drm); 224 return err; 225 } 226 227 static struct drm_info_list debugfs_files[] = { 228 { "regs", tegra_dsi_show_regs, 0, NULL }, 229 }; 230 231 static int tegra_dsi_late_register(struct drm_connector *connector) 232 { 233 struct tegra_output *output = connector_to_output(connector); 234 unsigned int i, count = ARRAY_SIZE(debugfs_files); 235 struct drm_minor *minor = connector->dev->primary; 236 struct dentry *root = connector->debugfs_entry; 237 struct tegra_dsi *dsi = to_dsi(output); 238 int err; 239 240 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 241 GFP_KERNEL); 242 if (!dsi->debugfs_files) 243 return -ENOMEM; 244 245 for (i = 0; i < count; i++) 246 dsi->debugfs_files[i].data = dsi; 247 248 err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 249 if (err < 0) 250 goto free; 251 252 return 0; 253 254 free: 255 kfree(dsi->debugfs_files); 256 dsi->debugfs_files = NULL; 257 258 return err; 259 } 260 261 static void tegra_dsi_early_unregister(struct drm_connector *connector) 262 { 263 struct tegra_output *output = connector_to_output(connector); 264 unsigned int count = ARRAY_SIZE(debugfs_files); 265 struct tegra_dsi *dsi = to_dsi(output); 266 267 drm_debugfs_remove_files(dsi->debugfs_files, count, 268 connector->dev->primary); 269 kfree(dsi->debugfs_files); 270 dsi->debugfs_files = NULL; 271 } 272 273 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 274 #define PKT_LEN0(len) (((len) & 0x07) << 0) 275 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 276 #define PKT_LEN1(len) (((len) & 0x07) << 10) 277 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 278 #define PKT_LEN2(len) (((len) & 0x07) << 20) 279 280 #define PKT_LP (1 << 30) 281 #define NUM_PKT_SEQ 12 282 283 /* 284 * non-burst mode with sync pulses 285 */ 286 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 287 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 288 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 289 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 290 PKT_LP, 291 [ 1] = 0, 292 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 293 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 294 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 295 PKT_LP, 296 [ 3] = 0, 297 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 298 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 299 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 300 PKT_LP, 301 [ 5] = 0, 302 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 303 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 304 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 305 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 306 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 307 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 308 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 309 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 310 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 311 PKT_LP, 312 [ 9] = 0, 313 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 314 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 315 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 316 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 317 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 318 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 319 }; 320 321 /* 322 * non-burst mode with sync events 323 */ 324 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 325 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 326 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 327 PKT_LP, 328 [ 1] = 0, 329 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 330 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 331 PKT_LP, 332 [ 3] = 0, 333 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 334 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 335 PKT_LP, 336 [ 5] = 0, 337 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 338 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 339 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 340 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 341 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 342 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 343 PKT_LP, 344 [ 9] = 0, 345 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 346 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 347 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 348 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 349 }; 350 351 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 352 [ 0] = 0, 353 [ 1] = 0, 354 [ 2] = 0, 355 [ 3] = 0, 356 [ 4] = 0, 357 [ 5] = 0, 358 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 359 [ 7] = 0, 360 [ 8] = 0, 361 [ 9] = 0, 362 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 363 [11] = 0, 364 }; 365 366 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 367 unsigned long period, 368 const struct mipi_dphy_timing *timing) 369 { 370 u32 value; 371 372 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 373 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 374 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 375 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 376 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 377 378 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 379 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 380 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 381 DSI_TIMING_FIELD(timing->lpx, period, 1); 382 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 383 384 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 385 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 386 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 387 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 388 389 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 390 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 391 DSI_TIMING_FIELD(timing->tago, period, 1); 392 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 393 394 if (dsi->slave) 395 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 396 } 397 398 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 399 unsigned int *mulp, unsigned int *divp) 400 { 401 switch (format) { 402 case MIPI_DSI_FMT_RGB666_PACKED: 403 case MIPI_DSI_FMT_RGB888: 404 *mulp = 3; 405 *divp = 1; 406 break; 407 408 case MIPI_DSI_FMT_RGB565: 409 *mulp = 2; 410 *divp = 1; 411 break; 412 413 case MIPI_DSI_FMT_RGB666: 414 *mulp = 9; 415 *divp = 4; 416 break; 417 418 default: 419 return -EINVAL; 420 } 421 422 return 0; 423 } 424 425 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 426 enum tegra_dsi_format *fmt) 427 { 428 switch (format) { 429 case MIPI_DSI_FMT_RGB888: 430 *fmt = TEGRA_DSI_FORMAT_24P; 431 break; 432 433 case MIPI_DSI_FMT_RGB666: 434 *fmt = TEGRA_DSI_FORMAT_18NP; 435 break; 436 437 case MIPI_DSI_FMT_RGB666_PACKED: 438 *fmt = TEGRA_DSI_FORMAT_18P; 439 break; 440 441 case MIPI_DSI_FMT_RGB565: 442 *fmt = TEGRA_DSI_FORMAT_16P; 443 break; 444 445 default: 446 return -EINVAL; 447 } 448 449 return 0; 450 } 451 452 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 453 unsigned int size) 454 { 455 u32 value; 456 457 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 458 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 459 460 value = DSI_GANGED_MODE_CONTROL_ENABLE; 461 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 462 } 463 464 static void tegra_dsi_enable(struct tegra_dsi *dsi) 465 { 466 u32 value; 467 468 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 469 value |= DSI_POWER_CONTROL_ENABLE; 470 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 471 472 if (dsi->slave) 473 tegra_dsi_enable(dsi->slave); 474 } 475 476 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 477 { 478 if (dsi->master) 479 return dsi->master->lanes + dsi->lanes; 480 481 if (dsi->slave) 482 return dsi->lanes + dsi->slave->lanes; 483 484 return dsi->lanes; 485 } 486 487 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 488 const struct drm_display_mode *mode) 489 { 490 unsigned int hact, hsw, hbp, hfp, i, mul, div; 491 struct tegra_dsi_state *state; 492 const u32 *pkt_seq; 493 u32 value; 494 495 /* XXX: pass in state into this function? */ 496 if (dsi->master) 497 state = tegra_dsi_get_state(dsi->master); 498 else 499 state = tegra_dsi_get_state(dsi); 500 501 mul = state->mul; 502 div = state->div; 503 504 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 505 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 506 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 507 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 508 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 509 pkt_seq = pkt_seq_video_non_burst_sync_events; 510 } else { 511 DRM_DEBUG_KMS("Command mode\n"); 512 pkt_seq = pkt_seq_command_mode; 513 } 514 515 value = DSI_CONTROL_CHANNEL(0) | 516 DSI_CONTROL_FORMAT(state->format) | 517 DSI_CONTROL_LANES(dsi->lanes - 1) | 518 DSI_CONTROL_SOURCE(pipe); 519 tegra_dsi_writel(dsi, value, DSI_CONTROL); 520 521 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 522 523 value = DSI_HOST_CONTROL_HS; 524 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 525 526 value = tegra_dsi_readl(dsi, DSI_CONTROL); 527 528 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 529 value |= DSI_CONTROL_HS_CLK_CTRL; 530 531 value &= ~DSI_CONTROL_TX_TRIG(3); 532 533 /* enable DCS commands for command mode */ 534 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 535 value &= ~DSI_CONTROL_DCS_ENABLE; 536 else 537 value |= DSI_CONTROL_DCS_ENABLE; 538 539 value |= DSI_CONTROL_VIDEO_ENABLE; 540 value &= ~DSI_CONTROL_HOST_ENABLE; 541 tegra_dsi_writel(dsi, value, DSI_CONTROL); 542 543 for (i = 0; i < NUM_PKT_SEQ; i++) 544 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 545 546 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 547 /* horizontal active pixels */ 548 hact = mode->hdisplay * mul / div; 549 550 /* horizontal sync width */ 551 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 552 553 /* horizontal back porch */ 554 hbp = (mode->htotal - mode->hsync_end) * mul / div; 555 556 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 557 hbp += hsw; 558 559 /* horizontal front porch */ 560 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 561 562 /* subtract packet overhead */ 563 hsw -= 10; 564 hbp -= 14; 565 hfp -= 8; 566 567 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 568 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 569 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 570 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 571 572 /* set SOL delay (for non-burst mode only) */ 573 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); 574 575 /* TODO: implement ganged mode */ 576 } else { 577 u16 bytes; 578 579 if (dsi->master || dsi->slave) { 580 /* 581 * For ganged mode, assume symmetric left-right mode. 582 */ 583 bytes = 1 + (mode->hdisplay / 2) * mul / div; 584 } else { 585 /* 1 byte (DCS command) + pixel data */ 586 bytes = 1 + mode->hdisplay * mul / div; 587 } 588 589 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 590 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 591 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 592 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 593 594 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 595 MIPI_DCS_WRITE_MEMORY_CONTINUE; 596 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 597 598 /* set SOL delay */ 599 if (dsi->master || dsi->slave) { 600 unsigned long delay, bclk, bclk_ganged; 601 unsigned int lanes = state->lanes; 602 603 /* SOL to valid, valid to FIFO and FIFO write delay */ 604 delay = 4 + 4 + 2; 605 delay = DIV_ROUND_UP(delay * mul, div * lanes); 606 /* FIFO read delay */ 607 delay = delay + 6; 608 609 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 610 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 611 value = bclk - bclk_ganged + delay + 20; 612 } else { 613 /* TODO: revisit for non-ganged mode */ 614 value = 8 * mul / div; 615 } 616 617 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 618 } 619 620 if (dsi->slave) { 621 tegra_dsi_configure(dsi->slave, pipe, mode); 622 623 /* 624 * TODO: Support modes other than symmetrical left-right 625 * split. 626 */ 627 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 628 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 629 mode->hdisplay / 2); 630 } 631 } 632 633 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 634 { 635 u32 value; 636 637 timeout = jiffies + msecs_to_jiffies(timeout); 638 639 while (time_before(jiffies, timeout)) { 640 value = tegra_dsi_readl(dsi, DSI_STATUS); 641 if (value & DSI_STATUS_IDLE) 642 return 0; 643 644 usleep_range(1000, 2000); 645 } 646 647 return -ETIMEDOUT; 648 } 649 650 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 651 { 652 u32 value; 653 654 value = tegra_dsi_readl(dsi, DSI_CONTROL); 655 value &= ~DSI_CONTROL_VIDEO_ENABLE; 656 tegra_dsi_writel(dsi, value, DSI_CONTROL); 657 658 if (dsi->slave) 659 tegra_dsi_video_disable(dsi->slave); 660 } 661 662 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 663 { 664 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 665 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 666 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 667 } 668 669 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 670 { 671 u32 value; 672 673 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 674 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 675 676 return 0; 677 } 678 679 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 680 { 681 u32 value; 682 683 /* 684 * XXX Is this still needed? The module reset is deasserted right 685 * before this function is called. 686 */ 687 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 688 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 689 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 690 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 691 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 692 693 /* start calibration */ 694 tegra_dsi_pad_enable(dsi); 695 696 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 697 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 698 DSI_PAD_OUT_CLK(0x0); 699 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 700 701 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 702 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 703 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 704 705 return tegra_mipi_calibrate(dsi->mipi); 706 } 707 708 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 709 unsigned int vrefresh) 710 { 711 unsigned int timeout; 712 u32 value; 713 714 /* one frame high-speed transmission timeout */ 715 timeout = (bclk / vrefresh) / 512; 716 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 717 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 718 719 /* 2 ms peripheral timeout for panel */ 720 timeout = 2 * bclk / 512 * 1000; 721 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 722 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 723 724 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 725 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 726 727 if (dsi->slave) 728 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 729 } 730 731 static void tegra_dsi_disable(struct tegra_dsi *dsi) 732 { 733 u32 value; 734 735 if (dsi->slave) { 736 tegra_dsi_ganged_disable(dsi->slave); 737 tegra_dsi_ganged_disable(dsi); 738 } 739 740 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 741 value &= ~DSI_POWER_CONTROL_ENABLE; 742 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 743 744 if (dsi->slave) 745 tegra_dsi_disable(dsi->slave); 746 747 usleep_range(5000, 10000); 748 } 749 750 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 751 { 752 u32 value; 753 754 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 755 value &= ~DSI_POWER_CONTROL_ENABLE; 756 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 757 758 usleep_range(300, 1000); 759 760 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 761 value |= DSI_POWER_CONTROL_ENABLE; 762 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 763 764 usleep_range(300, 1000); 765 766 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 767 if (value) 768 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 769 770 if (dsi->slave) 771 tegra_dsi_soft_reset(dsi->slave); 772 } 773 774 static void tegra_dsi_connector_reset(struct drm_connector *connector) 775 { 776 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 777 778 if (!state) 779 return; 780 781 if (connector->state) { 782 __drm_atomic_helper_connector_destroy_state(connector->state); 783 kfree(connector->state); 784 } 785 786 __drm_atomic_helper_connector_reset(connector, &state->base); 787 } 788 789 static struct drm_connector_state * 790 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 791 { 792 struct tegra_dsi_state *state = to_dsi_state(connector->state); 793 struct tegra_dsi_state *copy; 794 795 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 796 if (!copy) 797 return NULL; 798 799 __drm_atomic_helper_connector_duplicate_state(connector, 800 ©->base); 801 802 return ©->base; 803 } 804 805 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 806 .reset = tegra_dsi_connector_reset, 807 .detect = tegra_output_connector_detect, 808 .fill_modes = drm_helper_probe_single_connector_modes, 809 .destroy = tegra_output_connector_destroy, 810 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 811 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 812 .late_register = tegra_dsi_late_register, 813 .early_unregister = tegra_dsi_early_unregister, 814 }; 815 816 static enum drm_mode_status 817 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 818 struct drm_display_mode *mode) 819 { 820 return MODE_OK; 821 } 822 823 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 824 .get_modes = tegra_output_connector_get_modes, 825 .mode_valid = tegra_dsi_connector_mode_valid, 826 }; 827 828 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = { 829 .destroy = tegra_output_encoder_destroy, 830 }; 831 832 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 833 { 834 int err; 835 836 if (dsi->slave) 837 tegra_dsi_unprepare(dsi->slave); 838 839 err = tegra_mipi_disable(dsi->mipi); 840 if (err < 0) 841 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 842 err); 843 844 pm_runtime_put(dsi->dev); 845 } 846 847 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 848 { 849 struct tegra_output *output = encoder_to_output(encoder); 850 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 851 struct tegra_dsi *dsi = to_dsi(output); 852 u32 value; 853 int err; 854 855 if (output->panel) 856 drm_panel_disable(output->panel); 857 858 tegra_dsi_video_disable(dsi); 859 860 /* 861 * The following accesses registers of the display controller, so make 862 * sure it's only executed when the output is attached to one. 863 */ 864 if (dc) { 865 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 866 value &= ~DSI_ENABLE; 867 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 868 869 tegra_dc_commit(dc); 870 } 871 872 err = tegra_dsi_wait_idle(dsi, 100); 873 if (err < 0) 874 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 875 876 tegra_dsi_soft_reset(dsi); 877 878 if (output->panel) 879 drm_panel_unprepare(output->panel); 880 881 tegra_dsi_disable(dsi); 882 883 tegra_dsi_unprepare(dsi); 884 } 885 886 static void tegra_dsi_prepare(struct tegra_dsi *dsi) 887 { 888 int err; 889 890 pm_runtime_get_sync(dsi->dev); 891 892 err = tegra_mipi_enable(dsi->mipi); 893 if (err < 0) 894 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 895 err); 896 897 err = tegra_dsi_pad_calibrate(dsi); 898 if (err < 0) 899 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 900 901 if (dsi->slave) 902 tegra_dsi_prepare(dsi->slave); 903 } 904 905 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 906 { 907 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 908 struct tegra_output *output = encoder_to_output(encoder); 909 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 910 struct tegra_dsi *dsi = to_dsi(output); 911 struct tegra_dsi_state *state; 912 u32 value; 913 914 tegra_dsi_prepare(dsi); 915 916 state = tegra_dsi_get_state(dsi); 917 918 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 919 920 /* 921 * The D-PHY timing fields are expressed in byte-clock cycles, so 922 * multiply the period by 8. 923 */ 924 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 925 926 if (output->panel) 927 drm_panel_prepare(output->panel); 928 929 tegra_dsi_configure(dsi, dc->pipe, mode); 930 931 /* enable display controller */ 932 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 933 value |= DSI_ENABLE; 934 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 935 936 tegra_dc_commit(dc); 937 938 /* enable DSI controller */ 939 tegra_dsi_enable(dsi); 940 941 if (output->panel) 942 drm_panel_enable(output->panel); 943 } 944 945 static int 946 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 947 struct drm_crtc_state *crtc_state, 948 struct drm_connector_state *conn_state) 949 { 950 struct tegra_output *output = encoder_to_output(encoder); 951 struct tegra_dsi_state *state = to_dsi_state(conn_state); 952 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 953 struct tegra_dsi *dsi = to_dsi(output); 954 unsigned int scdiv; 955 unsigned long plld; 956 int err; 957 958 state->pclk = crtc_state->mode.clock * 1000; 959 960 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 961 if (err < 0) 962 return err; 963 964 state->lanes = tegra_dsi_get_lanes(dsi); 965 966 err = tegra_dsi_get_format(dsi->format, &state->format); 967 if (err < 0) 968 return err; 969 970 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 971 972 /* compute byte clock */ 973 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 974 975 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 976 state->lanes); 977 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 978 state->vrefresh); 979 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 980 981 /* 982 * Compute bit clock and round up to the next MHz. 983 */ 984 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 985 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 986 987 err = mipi_dphy_timing_get_default(&state->timing, state->period); 988 if (err < 0) 989 return err; 990 991 err = mipi_dphy_timing_validate(&state->timing, state->period); 992 if (err < 0) { 993 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 994 return err; 995 } 996 997 /* 998 * We divide the frequency by two here, but we make up for that by 999 * setting the shift clock divider (further below) to half of the 1000 * correct value. 1001 */ 1002 plld /= 2; 1003 1004 /* 1005 * Derive pixel clock from bit clock using the shift clock divider. 1006 * Note that this is only half of what we would expect, but we need 1007 * that to make up for the fact that we divided the bit clock by a 1008 * factor of two above. 1009 * 1010 * It's not clear exactly why this is necessary, but the display is 1011 * not working properly otherwise. Perhaps the PLLs cannot generate 1012 * frequencies sufficiently high. 1013 */ 1014 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1015 1016 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1017 plld, scdiv); 1018 if (err < 0) { 1019 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1020 return err; 1021 } 1022 1023 return err; 1024 } 1025 1026 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1027 .disable = tegra_dsi_encoder_disable, 1028 .enable = tegra_dsi_encoder_enable, 1029 .atomic_check = tegra_dsi_encoder_atomic_check, 1030 }; 1031 1032 static int tegra_dsi_init(struct host1x_client *client) 1033 { 1034 struct drm_device *drm = dev_get_drvdata(client->parent); 1035 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1036 int err; 1037 1038 /* Gangsters must not register their own outputs. */ 1039 if (!dsi->master) { 1040 dsi->output.dev = client->dev; 1041 1042 drm_connector_init(drm, &dsi->output.connector, 1043 &tegra_dsi_connector_funcs, 1044 DRM_MODE_CONNECTOR_DSI); 1045 drm_connector_helper_add(&dsi->output.connector, 1046 &tegra_dsi_connector_helper_funcs); 1047 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1048 1049 drm_encoder_init(drm, &dsi->output.encoder, 1050 &tegra_dsi_encoder_funcs, 1051 DRM_MODE_ENCODER_DSI, NULL); 1052 drm_encoder_helper_add(&dsi->output.encoder, 1053 &tegra_dsi_encoder_helper_funcs); 1054 1055 drm_mode_connector_attach_encoder(&dsi->output.connector, 1056 &dsi->output.encoder); 1057 drm_connector_register(&dsi->output.connector); 1058 1059 err = tegra_output_init(drm, &dsi->output); 1060 if (err < 0) 1061 dev_err(dsi->dev, "failed to initialize output: %d\n", 1062 err); 1063 1064 dsi->output.encoder.possible_crtcs = 0x3; 1065 } 1066 1067 return 0; 1068 } 1069 1070 static int tegra_dsi_exit(struct host1x_client *client) 1071 { 1072 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1073 1074 tegra_output_exit(&dsi->output); 1075 1076 return 0; 1077 } 1078 1079 static const struct host1x_client_ops dsi_client_ops = { 1080 .init = tegra_dsi_init, 1081 .exit = tegra_dsi_exit, 1082 }; 1083 1084 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1085 { 1086 struct clk *parent; 1087 int err; 1088 1089 parent = clk_get_parent(dsi->clk); 1090 if (!parent) 1091 return -EINVAL; 1092 1093 err = clk_set_parent(parent, dsi->clk_parent); 1094 if (err < 0) 1095 return err; 1096 1097 return 0; 1098 } 1099 1100 static const char * const error_report[16] = { 1101 "SoT Error", 1102 "SoT Sync Error", 1103 "EoT Sync Error", 1104 "Escape Mode Entry Command Error", 1105 "Low-Power Transmit Sync Error", 1106 "Peripheral Timeout Error", 1107 "False Control Error", 1108 "Contention Detected", 1109 "ECC Error, single-bit", 1110 "ECC Error, multi-bit", 1111 "Checksum Error", 1112 "DSI Data Type Not Recognized", 1113 "DSI VC ID Invalid", 1114 "Invalid Transmission Length", 1115 "Reserved", 1116 "DSI Protocol Violation", 1117 }; 1118 1119 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1120 const struct mipi_dsi_msg *msg, 1121 size_t count) 1122 { 1123 u8 *rx = msg->rx_buf; 1124 unsigned int i, j, k; 1125 size_t size = 0; 1126 u16 errors; 1127 u32 value; 1128 1129 /* read and parse packet header */ 1130 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1131 1132 switch (value & 0x3f) { 1133 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1134 errors = (value >> 8) & 0xffff; 1135 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1136 errors); 1137 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1138 if (errors & BIT(i)) 1139 dev_dbg(dsi->dev, " %2u: %s\n", i, 1140 error_report[i]); 1141 break; 1142 1143 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1144 rx[0] = (value >> 8) & 0xff; 1145 size = 1; 1146 break; 1147 1148 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1149 rx[0] = (value >> 8) & 0xff; 1150 rx[1] = (value >> 16) & 0xff; 1151 size = 2; 1152 break; 1153 1154 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1155 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1156 break; 1157 1158 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1159 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1160 break; 1161 1162 default: 1163 dev_err(dsi->dev, "unhandled response type: %02x\n", 1164 value & 0x3f); 1165 return -EPROTO; 1166 } 1167 1168 size = min(size, msg->rx_len); 1169 1170 if (msg->rx_buf && size > 0) { 1171 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1172 u8 *rx = msg->rx_buf + j; 1173 1174 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1175 1176 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1177 rx[j + k] = (value >> (k << 3)) & 0xff; 1178 } 1179 } 1180 1181 return size; 1182 } 1183 1184 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1185 { 1186 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1187 1188 timeout = jiffies + msecs_to_jiffies(timeout); 1189 1190 while (time_before(jiffies, timeout)) { 1191 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1192 if ((value & DSI_TRIGGER_HOST) == 0) 1193 return 0; 1194 1195 usleep_range(1000, 2000); 1196 } 1197 1198 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1199 return -ETIMEDOUT; 1200 } 1201 1202 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1203 unsigned long timeout) 1204 { 1205 timeout = jiffies + msecs_to_jiffies(250); 1206 1207 while (time_before(jiffies, timeout)) { 1208 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1209 u8 count = value & 0x1f; 1210 1211 if (count > 0) 1212 return count; 1213 1214 usleep_range(1000, 2000); 1215 } 1216 1217 DRM_DEBUG_KMS("peripheral returned no data\n"); 1218 return -ETIMEDOUT; 1219 } 1220 1221 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1222 const void *buffer, size_t size) 1223 { 1224 const u8 *buf = buffer; 1225 size_t i, j; 1226 u32 value; 1227 1228 for (j = 0; j < size; j += 4) { 1229 value = 0; 1230 1231 for (i = 0; i < 4 && j + i < size; i++) 1232 value |= buf[j + i] << (i << 3); 1233 1234 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1235 } 1236 } 1237 1238 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1239 const struct mipi_dsi_msg *msg) 1240 { 1241 struct tegra_dsi *dsi = host_to_tegra(host); 1242 struct mipi_dsi_packet packet; 1243 const u8 *header; 1244 size_t count; 1245 ssize_t err; 1246 u32 value; 1247 1248 err = mipi_dsi_create_packet(&packet, msg); 1249 if (err < 0) 1250 return err; 1251 1252 header = packet.header; 1253 1254 /* maximum FIFO depth is 1920 words */ 1255 if (packet.size > dsi->video_fifo_depth * 4) 1256 return -ENOSPC; 1257 1258 /* reset underflow/overflow flags */ 1259 value = tegra_dsi_readl(dsi, DSI_STATUS); 1260 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1261 value = DSI_HOST_CONTROL_FIFO_RESET; 1262 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1263 usleep_range(10, 20); 1264 } 1265 1266 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1267 value |= DSI_POWER_CONTROL_ENABLE; 1268 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1269 1270 usleep_range(5000, 10000); 1271 1272 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1273 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1274 1275 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1276 value |= DSI_HOST_CONTROL_HS; 1277 1278 /* 1279 * The host FIFO has a maximum of 64 words, so larger transmissions 1280 * need to use the video FIFO. 1281 */ 1282 if (packet.size > dsi->host_fifo_depth * 4) 1283 value |= DSI_HOST_CONTROL_FIFO_SEL; 1284 1285 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1286 1287 /* 1288 * For reads and messages with explicitly requested ACK, generate a 1289 * BTA sequence after the transmission of the packet. 1290 */ 1291 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1292 (msg->rx_buf && msg->rx_len > 0)) { 1293 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1294 value |= DSI_HOST_CONTROL_PKT_BTA; 1295 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1296 } 1297 1298 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1299 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1300 1301 /* write packet header, ECC is generated by hardware */ 1302 value = header[2] << 16 | header[1] << 8 | header[0]; 1303 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1304 1305 /* write payload (if any) */ 1306 if (packet.payload_length > 0) 1307 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1308 packet.payload_length); 1309 1310 err = tegra_dsi_transmit(dsi, 250); 1311 if (err < 0) 1312 return err; 1313 1314 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1315 (msg->rx_buf && msg->rx_len > 0)) { 1316 err = tegra_dsi_wait_for_response(dsi, 250); 1317 if (err < 0) 1318 return err; 1319 1320 count = err; 1321 1322 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1323 switch (value) { 1324 case 0x84: 1325 /* 1326 dev_dbg(dsi->dev, "ACK\n"); 1327 */ 1328 break; 1329 1330 case 0x87: 1331 /* 1332 dev_dbg(dsi->dev, "ESCAPE\n"); 1333 */ 1334 break; 1335 1336 default: 1337 dev_err(dsi->dev, "unknown status: %08x\n", value); 1338 break; 1339 } 1340 1341 if (count > 1) { 1342 err = tegra_dsi_read_response(dsi, msg, count); 1343 if (err < 0) 1344 dev_err(dsi->dev, 1345 "failed to parse response: %zd\n", 1346 err); 1347 else { 1348 /* 1349 * For read commands, return the number of 1350 * bytes returned by the peripheral. 1351 */ 1352 count = err; 1353 } 1354 } 1355 } else { 1356 /* 1357 * For write commands, we have transmitted the 4-byte header 1358 * plus the variable-length payload. 1359 */ 1360 count = 4 + packet.payload_length; 1361 } 1362 1363 return count; 1364 } 1365 1366 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1367 { 1368 struct clk *parent; 1369 int err; 1370 1371 /* make sure both DSI controllers share the same PLL */ 1372 parent = clk_get_parent(dsi->slave->clk); 1373 if (!parent) 1374 return -EINVAL; 1375 1376 err = clk_set_parent(parent, dsi->clk_parent); 1377 if (err < 0) 1378 return err; 1379 1380 return 0; 1381 } 1382 1383 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1384 struct mipi_dsi_device *device) 1385 { 1386 struct tegra_dsi *dsi = host_to_tegra(host); 1387 1388 dsi->flags = device->mode_flags; 1389 dsi->format = device->format; 1390 dsi->lanes = device->lanes; 1391 1392 if (dsi->slave) { 1393 int err; 1394 1395 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1396 dev_name(&device->dev)); 1397 1398 err = tegra_dsi_ganged_setup(dsi); 1399 if (err < 0) { 1400 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1401 err); 1402 return err; 1403 } 1404 } 1405 1406 /* 1407 * Slaves don't have a panel associated with them, so they provide 1408 * merely the second channel. 1409 */ 1410 if (!dsi->master) { 1411 struct tegra_output *output = &dsi->output; 1412 1413 output->panel = of_drm_find_panel(device->dev.of_node); 1414 if (output->panel && output->connector.dev) { 1415 drm_panel_attach(output->panel, &output->connector); 1416 drm_helper_hpd_irq_event(output->connector.dev); 1417 } 1418 } 1419 1420 return 0; 1421 } 1422 1423 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1424 struct mipi_dsi_device *device) 1425 { 1426 struct tegra_dsi *dsi = host_to_tegra(host); 1427 struct tegra_output *output = &dsi->output; 1428 1429 if (output->panel && &device->dev == output->panel->dev) { 1430 output->panel = NULL; 1431 1432 if (output->connector.dev) 1433 drm_helper_hpd_irq_event(output->connector.dev); 1434 } 1435 1436 return 0; 1437 } 1438 1439 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1440 .attach = tegra_dsi_host_attach, 1441 .detach = tegra_dsi_host_detach, 1442 .transfer = tegra_dsi_host_transfer, 1443 }; 1444 1445 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1446 { 1447 struct device_node *np; 1448 1449 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1450 if (np) { 1451 struct platform_device *gangster = of_find_device_by_node(np); 1452 1453 dsi->slave = platform_get_drvdata(gangster); 1454 of_node_put(np); 1455 1456 if (!dsi->slave) 1457 return -EPROBE_DEFER; 1458 1459 dsi->slave->master = dsi; 1460 } 1461 1462 return 0; 1463 } 1464 1465 static int tegra_dsi_probe(struct platform_device *pdev) 1466 { 1467 struct tegra_dsi *dsi; 1468 struct resource *regs; 1469 int err; 1470 1471 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1472 if (!dsi) 1473 return -ENOMEM; 1474 1475 dsi->output.dev = dsi->dev = &pdev->dev; 1476 dsi->video_fifo_depth = 1920; 1477 dsi->host_fifo_depth = 64; 1478 1479 err = tegra_dsi_ganged_probe(dsi); 1480 if (err < 0) 1481 return err; 1482 1483 err = tegra_output_probe(&dsi->output); 1484 if (err < 0) 1485 return err; 1486 1487 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1488 1489 /* 1490 * Assume these values by default. When a DSI peripheral driver 1491 * attaches to the DSI host, the parameters will be taken from 1492 * the attached device. 1493 */ 1494 dsi->flags = MIPI_DSI_MODE_VIDEO; 1495 dsi->format = MIPI_DSI_FMT_RGB888; 1496 dsi->lanes = 4; 1497 1498 if (!pdev->dev.pm_domain) { 1499 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1500 if (IS_ERR(dsi->rst)) 1501 return PTR_ERR(dsi->rst); 1502 } 1503 1504 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1505 if (IS_ERR(dsi->clk)) { 1506 dev_err(&pdev->dev, "cannot get DSI clock\n"); 1507 return PTR_ERR(dsi->clk); 1508 } 1509 1510 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1511 if (IS_ERR(dsi->clk_lp)) { 1512 dev_err(&pdev->dev, "cannot get low-power clock\n"); 1513 return PTR_ERR(dsi->clk_lp); 1514 } 1515 1516 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1517 if (IS_ERR(dsi->clk_parent)) { 1518 dev_err(&pdev->dev, "cannot get parent clock\n"); 1519 return PTR_ERR(dsi->clk_parent); 1520 } 1521 1522 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1523 if (IS_ERR(dsi->vdd)) { 1524 dev_err(&pdev->dev, "cannot get VDD supply\n"); 1525 return PTR_ERR(dsi->vdd); 1526 } 1527 1528 err = tegra_dsi_setup_clocks(dsi); 1529 if (err < 0) { 1530 dev_err(&pdev->dev, "cannot setup clocks\n"); 1531 return err; 1532 } 1533 1534 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1535 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); 1536 if (IS_ERR(dsi->regs)) 1537 return PTR_ERR(dsi->regs); 1538 1539 dsi->mipi = tegra_mipi_request(&pdev->dev); 1540 if (IS_ERR(dsi->mipi)) 1541 return PTR_ERR(dsi->mipi); 1542 1543 dsi->host.ops = &tegra_dsi_host_ops; 1544 dsi->host.dev = &pdev->dev; 1545 1546 err = mipi_dsi_host_register(&dsi->host); 1547 if (err < 0) { 1548 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1549 goto mipi_free; 1550 } 1551 1552 platform_set_drvdata(pdev, dsi); 1553 pm_runtime_enable(&pdev->dev); 1554 1555 INIT_LIST_HEAD(&dsi->client.list); 1556 dsi->client.ops = &dsi_client_ops; 1557 dsi->client.dev = &pdev->dev; 1558 1559 err = host1x_client_register(&dsi->client); 1560 if (err < 0) { 1561 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1562 err); 1563 goto unregister; 1564 } 1565 1566 return 0; 1567 1568 unregister: 1569 mipi_dsi_host_unregister(&dsi->host); 1570 mipi_free: 1571 tegra_mipi_free(dsi->mipi); 1572 return err; 1573 } 1574 1575 static int tegra_dsi_remove(struct platform_device *pdev) 1576 { 1577 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1578 int err; 1579 1580 pm_runtime_disable(&pdev->dev); 1581 1582 err = host1x_client_unregister(&dsi->client); 1583 if (err < 0) { 1584 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1585 err); 1586 return err; 1587 } 1588 1589 tegra_output_remove(&dsi->output); 1590 1591 mipi_dsi_host_unregister(&dsi->host); 1592 tegra_mipi_free(dsi->mipi); 1593 1594 return 0; 1595 } 1596 1597 #ifdef CONFIG_PM 1598 static int tegra_dsi_suspend(struct device *dev) 1599 { 1600 struct tegra_dsi *dsi = dev_get_drvdata(dev); 1601 int err; 1602 1603 if (dsi->rst) { 1604 err = reset_control_assert(dsi->rst); 1605 if (err < 0) { 1606 dev_err(dev, "failed to assert reset: %d\n", err); 1607 return err; 1608 } 1609 } 1610 1611 usleep_range(1000, 2000); 1612 1613 clk_disable_unprepare(dsi->clk_lp); 1614 clk_disable_unprepare(dsi->clk); 1615 1616 regulator_disable(dsi->vdd); 1617 1618 return 0; 1619 } 1620 1621 static int tegra_dsi_resume(struct device *dev) 1622 { 1623 struct tegra_dsi *dsi = dev_get_drvdata(dev); 1624 int err; 1625 1626 err = regulator_enable(dsi->vdd); 1627 if (err < 0) { 1628 dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err); 1629 return err; 1630 } 1631 1632 err = clk_prepare_enable(dsi->clk); 1633 if (err < 0) { 1634 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1635 goto disable_vdd; 1636 } 1637 1638 err = clk_prepare_enable(dsi->clk_lp); 1639 if (err < 0) { 1640 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1641 goto disable_clk; 1642 } 1643 1644 usleep_range(1000, 2000); 1645 1646 if (dsi->rst) { 1647 err = reset_control_deassert(dsi->rst); 1648 if (err < 0) { 1649 dev_err(dev, "cannot assert reset: %d\n", err); 1650 goto disable_clk_lp; 1651 } 1652 } 1653 1654 return 0; 1655 1656 disable_clk_lp: 1657 clk_disable_unprepare(dsi->clk_lp); 1658 disable_clk: 1659 clk_disable_unprepare(dsi->clk); 1660 disable_vdd: 1661 regulator_disable(dsi->vdd); 1662 return err; 1663 } 1664 #endif 1665 1666 static const struct dev_pm_ops tegra_dsi_pm_ops = { 1667 SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL) 1668 }; 1669 1670 static const struct of_device_id tegra_dsi_of_match[] = { 1671 { .compatible = "nvidia,tegra210-dsi", }, 1672 { .compatible = "nvidia,tegra132-dsi", }, 1673 { .compatible = "nvidia,tegra124-dsi", }, 1674 { .compatible = "nvidia,tegra114-dsi", }, 1675 { }, 1676 }; 1677 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1678 1679 struct platform_driver tegra_dsi_driver = { 1680 .driver = { 1681 .name = "tegra-dsi", 1682 .of_match_table = tegra_dsi_of_match, 1683 .pm = &tegra_dsi_pm_ops, 1684 }, 1685 .probe = tegra_dsi_probe, 1686 .remove = tegra_dsi_remove, 1687 }; 1688