xref: /openbmc/linux/drivers/gpu/drm/tegra/dsi.c (revision 9726bfcd)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (C) 2013 NVIDIA Corporation
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/debugfs.h>
8 #include <linux/host1x.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/of_platform.h>
12 #include <linux/platform_device.h>
13 #include <linux/pm_runtime.h>
14 #include <linux/reset.h>
15 
16 #include <linux/regulator/consumer.h>
17 
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_panel.h>
21 
22 #include <video/mipi_display.h>
23 
24 #include "dc.h"
25 #include "drm.h"
26 #include "dsi.h"
27 #include "mipi-phy.h"
28 #include "trace.h"
29 
30 struct tegra_dsi_state {
31 	struct drm_connector_state base;
32 
33 	struct mipi_dphy_timing timing;
34 	unsigned long period;
35 
36 	unsigned int vrefresh;
37 	unsigned int lanes;
38 	unsigned long pclk;
39 	unsigned long bclk;
40 
41 	enum tegra_dsi_format format;
42 	unsigned int mul;
43 	unsigned int div;
44 };
45 
46 static inline struct tegra_dsi_state *
47 to_dsi_state(struct drm_connector_state *state)
48 {
49 	return container_of(state, struct tegra_dsi_state, base);
50 }
51 
52 struct tegra_dsi {
53 	struct host1x_client client;
54 	struct tegra_output output;
55 	struct device *dev;
56 
57 	void __iomem *regs;
58 
59 	struct reset_control *rst;
60 	struct clk *clk_parent;
61 	struct clk *clk_lp;
62 	struct clk *clk;
63 
64 	struct drm_info_list *debugfs_files;
65 
66 	unsigned long flags;
67 	enum mipi_dsi_pixel_format format;
68 	unsigned int lanes;
69 
70 	struct tegra_mipi_device *mipi;
71 	struct mipi_dsi_host host;
72 
73 	struct regulator *vdd;
74 
75 	unsigned int video_fifo_depth;
76 	unsigned int host_fifo_depth;
77 
78 	/* for ganged-mode support */
79 	struct tegra_dsi *master;
80 	struct tegra_dsi *slave;
81 };
82 
83 static inline struct tegra_dsi *
84 host1x_client_to_dsi(struct host1x_client *client)
85 {
86 	return container_of(client, struct tegra_dsi, client);
87 }
88 
89 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
90 {
91 	return container_of(host, struct tegra_dsi, host);
92 }
93 
94 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
95 {
96 	return container_of(output, struct tegra_dsi, output);
97 }
98 
99 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
100 {
101 	return to_dsi_state(dsi->output.connector.state);
102 }
103 
104 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
105 {
106 	u32 value = readl(dsi->regs + (offset << 2));
107 
108 	trace_dsi_readl(dsi->dev, offset, value);
109 
110 	return value;
111 }
112 
113 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
114 				    unsigned int offset)
115 {
116 	trace_dsi_writel(dsi->dev, offset, value);
117 	writel(value, dsi->regs + (offset << 2));
118 }
119 
120 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
121 
122 static const struct debugfs_reg32 tegra_dsi_regs[] = {
123 	DEBUGFS_REG32(DSI_INCR_SYNCPT),
124 	DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
125 	DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
126 	DEBUGFS_REG32(DSI_CTXSW),
127 	DEBUGFS_REG32(DSI_RD_DATA),
128 	DEBUGFS_REG32(DSI_WR_DATA),
129 	DEBUGFS_REG32(DSI_POWER_CONTROL),
130 	DEBUGFS_REG32(DSI_INT_ENABLE),
131 	DEBUGFS_REG32(DSI_INT_STATUS),
132 	DEBUGFS_REG32(DSI_INT_MASK),
133 	DEBUGFS_REG32(DSI_HOST_CONTROL),
134 	DEBUGFS_REG32(DSI_CONTROL),
135 	DEBUGFS_REG32(DSI_SOL_DELAY),
136 	DEBUGFS_REG32(DSI_MAX_THRESHOLD),
137 	DEBUGFS_REG32(DSI_TRIGGER),
138 	DEBUGFS_REG32(DSI_TX_CRC),
139 	DEBUGFS_REG32(DSI_STATUS),
140 	DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
141 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
142 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
143 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
144 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
145 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
146 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
147 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
148 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
149 	DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
150 	DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
151 	DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
152 	DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
153 	DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
154 	DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
155 	DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
156 	DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
157 	DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
158 	DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
159 	DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
160 	DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
161 	DEBUGFS_REG32(DSI_DCS_CMDS),
162 	DEBUGFS_REG32(DSI_PKT_LEN_0_1),
163 	DEBUGFS_REG32(DSI_PKT_LEN_2_3),
164 	DEBUGFS_REG32(DSI_PKT_LEN_4_5),
165 	DEBUGFS_REG32(DSI_PKT_LEN_6_7),
166 	DEBUGFS_REG32(DSI_PHY_TIMING_0),
167 	DEBUGFS_REG32(DSI_PHY_TIMING_1),
168 	DEBUGFS_REG32(DSI_PHY_TIMING_2),
169 	DEBUGFS_REG32(DSI_BTA_TIMING),
170 	DEBUGFS_REG32(DSI_TIMEOUT_0),
171 	DEBUGFS_REG32(DSI_TIMEOUT_1),
172 	DEBUGFS_REG32(DSI_TO_TALLY),
173 	DEBUGFS_REG32(DSI_PAD_CONTROL_0),
174 	DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
175 	DEBUGFS_REG32(DSI_PAD_CD_STATUS),
176 	DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
177 	DEBUGFS_REG32(DSI_PAD_CONTROL_1),
178 	DEBUGFS_REG32(DSI_PAD_CONTROL_2),
179 	DEBUGFS_REG32(DSI_PAD_CONTROL_3),
180 	DEBUGFS_REG32(DSI_PAD_CONTROL_4),
181 	DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
182 	DEBUGFS_REG32(DSI_GANGED_MODE_START),
183 	DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
184 	DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
185 	DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
186 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
187 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
188 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
189 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
190 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
191 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
192 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
193 	DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
194 };
195 
196 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
197 {
198 	struct drm_info_node *node = s->private;
199 	struct tegra_dsi *dsi = node->info_ent->data;
200 	struct drm_crtc *crtc = dsi->output.encoder.crtc;
201 	struct drm_device *drm = node->minor->dev;
202 	unsigned int i;
203 	int err = 0;
204 
205 	drm_modeset_lock_all(drm);
206 
207 	if (!crtc || !crtc->state->active) {
208 		err = -EBUSY;
209 		goto unlock;
210 	}
211 
212 	for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
213 		unsigned int offset = tegra_dsi_regs[i].offset;
214 
215 		seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
216 			   offset, tegra_dsi_readl(dsi, offset));
217 	}
218 
219 unlock:
220 	drm_modeset_unlock_all(drm);
221 	return err;
222 }
223 
224 static struct drm_info_list debugfs_files[] = {
225 	{ "regs", tegra_dsi_show_regs, 0, NULL },
226 };
227 
228 static int tegra_dsi_late_register(struct drm_connector *connector)
229 {
230 	struct tegra_output *output = connector_to_output(connector);
231 	unsigned int i, count = ARRAY_SIZE(debugfs_files);
232 	struct drm_minor *minor = connector->dev->primary;
233 	struct dentry *root = connector->debugfs_entry;
234 	struct tegra_dsi *dsi = to_dsi(output);
235 	int err;
236 
237 	dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
238 				     GFP_KERNEL);
239 	if (!dsi->debugfs_files)
240 		return -ENOMEM;
241 
242 	for (i = 0; i < count; i++)
243 		dsi->debugfs_files[i].data = dsi;
244 
245 	err = drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
246 	if (err < 0)
247 		goto free;
248 
249 	return 0;
250 
251 free:
252 	kfree(dsi->debugfs_files);
253 	dsi->debugfs_files = NULL;
254 
255 	return err;
256 }
257 
258 static void tegra_dsi_early_unregister(struct drm_connector *connector)
259 {
260 	struct tegra_output *output = connector_to_output(connector);
261 	unsigned int count = ARRAY_SIZE(debugfs_files);
262 	struct tegra_dsi *dsi = to_dsi(output);
263 
264 	drm_debugfs_remove_files(dsi->debugfs_files, count,
265 				 connector->dev->primary);
266 	kfree(dsi->debugfs_files);
267 	dsi->debugfs_files = NULL;
268 }
269 
270 #define PKT_ID0(id)	((((id) & 0x3f) <<  3) | (1 <<  9))
271 #define PKT_LEN0(len)	(((len) & 0x07) <<  0)
272 #define PKT_ID1(id)	((((id) & 0x3f) << 13) | (1 << 19))
273 #define PKT_LEN1(len)	(((len) & 0x07) << 10)
274 #define PKT_ID2(id)	((((id) & 0x3f) << 23) | (1 << 29))
275 #define PKT_LEN2(len)	(((len) & 0x07) << 20)
276 
277 #define PKT_LP		(1 << 30)
278 #define NUM_PKT_SEQ	12
279 
280 /*
281  * non-burst mode with sync pulses
282  */
283 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
284 	[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
285 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
286 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
287 	       PKT_LP,
288 	[ 1] = 0,
289 	[ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
290 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
291 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
292 	       PKT_LP,
293 	[ 3] = 0,
294 	[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
295 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
296 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
297 	       PKT_LP,
298 	[ 5] = 0,
299 	[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
300 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
301 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
302 	[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
303 	       PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
304 	       PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
305 	[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
306 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
307 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
308 	       PKT_LP,
309 	[ 9] = 0,
310 	[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
311 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
312 	       PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
313 	[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
314 	       PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
315 	       PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
316 };
317 
318 /*
319  * non-burst mode with sync events
320  */
321 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
322 	[ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
323 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
324 	       PKT_LP,
325 	[ 1] = 0,
326 	[ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
327 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
328 	       PKT_LP,
329 	[ 3] = 0,
330 	[ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
331 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
332 	       PKT_LP,
333 	[ 5] = 0,
334 	[ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
335 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
336 	       PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
337 	[ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
338 	[ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
339 	       PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
340 	       PKT_LP,
341 	[ 9] = 0,
342 	[10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
343 	       PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
344 	       PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
345 	[11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
346 };
347 
348 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
349 	[ 0] = 0,
350 	[ 1] = 0,
351 	[ 2] = 0,
352 	[ 3] = 0,
353 	[ 4] = 0,
354 	[ 5] = 0,
355 	[ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
356 	[ 7] = 0,
357 	[ 8] = 0,
358 	[ 9] = 0,
359 	[10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
360 	[11] = 0,
361 };
362 
363 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
364 				     unsigned long period,
365 				     const struct mipi_dphy_timing *timing)
366 {
367 	u32 value;
368 
369 	value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
370 		DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
371 		DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
372 		DSI_TIMING_FIELD(timing->hsprepare, period, 1);
373 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
374 
375 	value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
376 		DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
377 		DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
378 		DSI_TIMING_FIELD(timing->lpx, period, 1);
379 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
380 
381 	value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
382 		DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
383 		DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
384 	tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
385 
386 	value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
387 		DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
388 		DSI_TIMING_FIELD(timing->tago, period, 1);
389 	tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
390 
391 	if (dsi->slave)
392 		tegra_dsi_set_phy_timing(dsi->slave, period, timing);
393 }
394 
395 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
396 				unsigned int *mulp, unsigned int *divp)
397 {
398 	switch (format) {
399 	case MIPI_DSI_FMT_RGB666_PACKED:
400 	case MIPI_DSI_FMT_RGB888:
401 		*mulp = 3;
402 		*divp = 1;
403 		break;
404 
405 	case MIPI_DSI_FMT_RGB565:
406 		*mulp = 2;
407 		*divp = 1;
408 		break;
409 
410 	case MIPI_DSI_FMT_RGB666:
411 		*mulp = 9;
412 		*divp = 4;
413 		break;
414 
415 	default:
416 		return -EINVAL;
417 	}
418 
419 	return 0;
420 }
421 
422 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
423 				enum tegra_dsi_format *fmt)
424 {
425 	switch (format) {
426 	case MIPI_DSI_FMT_RGB888:
427 		*fmt = TEGRA_DSI_FORMAT_24P;
428 		break;
429 
430 	case MIPI_DSI_FMT_RGB666:
431 		*fmt = TEGRA_DSI_FORMAT_18NP;
432 		break;
433 
434 	case MIPI_DSI_FMT_RGB666_PACKED:
435 		*fmt = TEGRA_DSI_FORMAT_18P;
436 		break;
437 
438 	case MIPI_DSI_FMT_RGB565:
439 		*fmt = TEGRA_DSI_FORMAT_16P;
440 		break;
441 
442 	default:
443 		return -EINVAL;
444 	}
445 
446 	return 0;
447 }
448 
449 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
450 				    unsigned int size)
451 {
452 	u32 value;
453 
454 	tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
455 	tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
456 
457 	value = DSI_GANGED_MODE_CONTROL_ENABLE;
458 	tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
459 }
460 
461 static void tegra_dsi_enable(struct tegra_dsi *dsi)
462 {
463 	u32 value;
464 
465 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
466 	value |= DSI_POWER_CONTROL_ENABLE;
467 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
468 
469 	if (dsi->slave)
470 		tegra_dsi_enable(dsi->slave);
471 }
472 
473 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
474 {
475 	if (dsi->master)
476 		return dsi->master->lanes + dsi->lanes;
477 
478 	if (dsi->slave)
479 		return dsi->lanes + dsi->slave->lanes;
480 
481 	return dsi->lanes;
482 }
483 
484 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
485 				const struct drm_display_mode *mode)
486 {
487 	unsigned int hact, hsw, hbp, hfp, i, mul, div;
488 	struct tegra_dsi_state *state;
489 	const u32 *pkt_seq;
490 	u32 value;
491 
492 	/* XXX: pass in state into this function? */
493 	if (dsi->master)
494 		state = tegra_dsi_get_state(dsi->master);
495 	else
496 		state = tegra_dsi_get_state(dsi);
497 
498 	mul = state->mul;
499 	div = state->div;
500 
501 	if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
502 		DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
503 		pkt_seq = pkt_seq_video_non_burst_sync_pulses;
504 	} else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
505 		DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
506 		pkt_seq = pkt_seq_video_non_burst_sync_events;
507 	} else {
508 		DRM_DEBUG_KMS("Command mode\n");
509 		pkt_seq = pkt_seq_command_mode;
510 	}
511 
512 	value = DSI_CONTROL_CHANNEL(0) |
513 		DSI_CONTROL_FORMAT(state->format) |
514 		DSI_CONTROL_LANES(dsi->lanes - 1) |
515 		DSI_CONTROL_SOURCE(pipe);
516 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
517 
518 	tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
519 
520 	value = DSI_HOST_CONTROL_HS;
521 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
522 
523 	value = tegra_dsi_readl(dsi, DSI_CONTROL);
524 
525 	if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
526 		value |= DSI_CONTROL_HS_CLK_CTRL;
527 
528 	value &= ~DSI_CONTROL_TX_TRIG(3);
529 
530 	/* enable DCS commands for command mode */
531 	if (dsi->flags & MIPI_DSI_MODE_VIDEO)
532 		value &= ~DSI_CONTROL_DCS_ENABLE;
533 	else
534 		value |= DSI_CONTROL_DCS_ENABLE;
535 
536 	value |= DSI_CONTROL_VIDEO_ENABLE;
537 	value &= ~DSI_CONTROL_HOST_ENABLE;
538 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
539 
540 	for (i = 0; i < NUM_PKT_SEQ; i++)
541 		tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
542 
543 	if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
544 		/* horizontal active pixels */
545 		hact = mode->hdisplay * mul / div;
546 
547 		/* horizontal sync width */
548 		hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
549 
550 		/* horizontal back porch */
551 		hbp = (mode->htotal - mode->hsync_end) * mul / div;
552 
553 		if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
554 			hbp += hsw;
555 
556 		/* horizontal front porch */
557 		hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
558 
559 		/* subtract packet overhead */
560 		hsw -= 10;
561 		hbp -= 14;
562 		hfp -= 8;
563 
564 		tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
565 		tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
566 		tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
567 		tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
568 
569 		/* set SOL delay (for non-burst mode only) */
570 		tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
571 
572 		/* TODO: implement ganged mode */
573 	} else {
574 		u16 bytes;
575 
576 		if (dsi->master || dsi->slave) {
577 			/*
578 			 * For ganged mode, assume symmetric left-right mode.
579 			 */
580 			bytes = 1 + (mode->hdisplay / 2) * mul / div;
581 		} else {
582 			/* 1 byte (DCS command) + pixel data */
583 			bytes = 1 + mode->hdisplay * mul / div;
584 		}
585 
586 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
587 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
588 		tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
589 		tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
590 
591 		value = MIPI_DCS_WRITE_MEMORY_START << 8 |
592 			MIPI_DCS_WRITE_MEMORY_CONTINUE;
593 		tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
594 
595 		/* set SOL delay */
596 		if (dsi->master || dsi->slave) {
597 			unsigned long delay, bclk, bclk_ganged;
598 			unsigned int lanes = state->lanes;
599 
600 			/* SOL to valid, valid to FIFO and FIFO write delay */
601 			delay = 4 + 4 + 2;
602 			delay = DIV_ROUND_UP(delay * mul, div * lanes);
603 			/* FIFO read delay */
604 			delay = delay + 6;
605 
606 			bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
607 			bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
608 			value = bclk - bclk_ganged + delay + 20;
609 		} else {
610 			/* TODO: revisit for non-ganged mode */
611 			value = 8 * mul / div;
612 		}
613 
614 		tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
615 	}
616 
617 	if (dsi->slave) {
618 		tegra_dsi_configure(dsi->slave, pipe, mode);
619 
620 		/*
621 		 * TODO: Support modes other than symmetrical left-right
622 		 * split.
623 		 */
624 		tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
625 		tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
626 					mode->hdisplay / 2);
627 	}
628 }
629 
630 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
631 {
632 	u32 value;
633 
634 	timeout = jiffies + msecs_to_jiffies(timeout);
635 
636 	while (time_before(jiffies, timeout)) {
637 		value = tegra_dsi_readl(dsi, DSI_STATUS);
638 		if (value & DSI_STATUS_IDLE)
639 			return 0;
640 
641 		usleep_range(1000, 2000);
642 	}
643 
644 	return -ETIMEDOUT;
645 }
646 
647 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
648 {
649 	u32 value;
650 
651 	value = tegra_dsi_readl(dsi, DSI_CONTROL);
652 	value &= ~DSI_CONTROL_VIDEO_ENABLE;
653 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
654 
655 	if (dsi->slave)
656 		tegra_dsi_video_disable(dsi->slave);
657 }
658 
659 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
660 {
661 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
662 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
663 	tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
664 }
665 
666 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
667 {
668 	u32 value;
669 
670 	value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
671 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
672 
673 	return 0;
674 }
675 
676 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
677 {
678 	u32 value;
679 
680 	/*
681 	 * XXX Is this still needed? The module reset is deasserted right
682 	 * before this function is called.
683 	 */
684 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
685 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
686 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
687 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
688 	tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
689 
690 	/* start calibration */
691 	tegra_dsi_pad_enable(dsi);
692 
693 	value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
694 		DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
695 		DSI_PAD_OUT_CLK(0x0);
696 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
697 
698 	value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
699 		DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
700 	tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
701 
702 	return tegra_mipi_calibrate(dsi->mipi);
703 }
704 
705 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
706 				  unsigned int vrefresh)
707 {
708 	unsigned int timeout;
709 	u32 value;
710 
711 	/* one frame high-speed transmission timeout */
712 	timeout = (bclk / vrefresh) / 512;
713 	value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
714 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
715 
716 	/* 2 ms peripheral timeout for panel */
717 	timeout = 2 * bclk / 512 * 1000;
718 	value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
719 	tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
720 
721 	value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
722 	tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
723 
724 	if (dsi->slave)
725 		tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
726 }
727 
728 static void tegra_dsi_disable(struct tegra_dsi *dsi)
729 {
730 	u32 value;
731 
732 	if (dsi->slave) {
733 		tegra_dsi_ganged_disable(dsi->slave);
734 		tegra_dsi_ganged_disable(dsi);
735 	}
736 
737 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
738 	value &= ~DSI_POWER_CONTROL_ENABLE;
739 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
740 
741 	if (dsi->slave)
742 		tegra_dsi_disable(dsi->slave);
743 
744 	usleep_range(5000, 10000);
745 }
746 
747 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
748 {
749 	u32 value;
750 
751 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
752 	value &= ~DSI_POWER_CONTROL_ENABLE;
753 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
754 
755 	usleep_range(300, 1000);
756 
757 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
758 	value |= DSI_POWER_CONTROL_ENABLE;
759 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
760 
761 	usleep_range(300, 1000);
762 
763 	value = tegra_dsi_readl(dsi, DSI_TRIGGER);
764 	if (value)
765 		tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
766 
767 	if (dsi->slave)
768 		tegra_dsi_soft_reset(dsi->slave);
769 }
770 
771 static void tegra_dsi_connector_reset(struct drm_connector *connector)
772 {
773 	struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
774 
775 	if (!state)
776 		return;
777 
778 	if (connector->state) {
779 		__drm_atomic_helper_connector_destroy_state(connector->state);
780 		kfree(connector->state);
781 	}
782 
783 	__drm_atomic_helper_connector_reset(connector, &state->base);
784 }
785 
786 static struct drm_connector_state *
787 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
788 {
789 	struct tegra_dsi_state *state = to_dsi_state(connector->state);
790 	struct tegra_dsi_state *copy;
791 
792 	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
793 	if (!copy)
794 		return NULL;
795 
796 	__drm_atomic_helper_connector_duplicate_state(connector,
797 						      &copy->base);
798 
799 	return &copy->base;
800 }
801 
802 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
803 	.reset = tegra_dsi_connector_reset,
804 	.detect = tegra_output_connector_detect,
805 	.fill_modes = drm_helper_probe_single_connector_modes,
806 	.destroy = tegra_output_connector_destroy,
807 	.atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
808 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
809 	.late_register = tegra_dsi_late_register,
810 	.early_unregister = tegra_dsi_early_unregister,
811 };
812 
813 static enum drm_mode_status
814 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
815 			       struct drm_display_mode *mode)
816 {
817 	return MODE_OK;
818 }
819 
820 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
821 	.get_modes = tegra_output_connector_get_modes,
822 	.mode_valid = tegra_dsi_connector_mode_valid,
823 };
824 
825 static const struct drm_encoder_funcs tegra_dsi_encoder_funcs = {
826 	.destroy = tegra_output_encoder_destroy,
827 };
828 
829 static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
830 {
831 	int err;
832 
833 	if (dsi->slave)
834 		tegra_dsi_unprepare(dsi->slave);
835 
836 	err = tegra_mipi_disable(dsi->mipi);
837 	if (err < 0)
838 		dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
839 			err);
840 
841 	pm_runtime_put(dsi->dev);
842 }
843 
844 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
845 {
846 	struct tegra_output *output = encoder_to_output(encoder);
847 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
848 	struct tegra_dsi *dsi = to_dsi(output);
849 	u32 value;
850 	int err;
851 
852 	if (output->panel)
853 		drm_panel_disable(output->panel);
854 
855 	tegra_dsi_video_disable(dsi);
856 
857 	/*
858 	 * The following accesses registers of the display controller, so make
859 	 * sure it's only executed when the output is attached to one.
860 	 */
861 	if (dc) {
862 		value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
863 		value &= ~DSI_ENABLE;
864 		tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
865 
866 		tegra_dc_commit(dc);
867 	}
868 
869 	err = tegra_dsi_wait_idle(dsi, 100);
870 	if (err < 0)
871 		dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
872 
873 	tegra_dsi_soft_reset(dsi);
874 
875 	if (output->panel)
876 		drm_panel_unprepare(output->panel);
877 
878 	tegra_dsi_disable(dsi);
879 
880 	tegra_dsi_unprepare(dsi);
881 }
882 
883 static void tegra_dsi_prepare(struct tegra_dsi *dsi)
884 {
885 	int err;
886 
887 	pm_runtime_get_sync(dsi->dev);
888 
889 	err = tegra_mipi_enable(dsi->mipi);
890 	if (err < 0)
891 		dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
892 			err);
893 
894 	err = tegra_dsi_pad_calibrate(dsi);
895 	if (err < 0)
896 		dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
897 
898 	if (dsi->slave)
899 		tegra_dsi_prepare(dsi->slave);
900 }
901 
902 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
903 {
904 	struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
905 	struct tegra_output *output = encoder_to_output(encoder);
906 	struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
907 	struct tegra_dsi *dsi = to_dsi(output);
908 	struct tegra_dsi_state *state;
909 	u32 value;
910 
911 	tegra_dsi_prepare(dsi);
912 
913 	state = tegra_dsi_get_state(dsi);
914 
915 	tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
916 
917 	/*
918 	 * The D-PHY timing fields are expressed in byte-clock cycles, so
919 	 * multiply the period by 8.
920 	 */
921 	tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
922 
923 	if (output->panel)
924 		drm_panel_prepare(output->panel);
925 
926 	tegra_dsi_configure(dsi, dc->pipe, mode);
927 
928 	/* enable display controller */
929 	value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
930 	value |= DSI_ENABLE;
931 	tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
932 
933 	tegra_dc_commit(dc);
934 
935 	/* enable DSI controller */
936 	tegra_dsi_enable(dsi);
937 
938 	if (output->panel)
939 		drm_panel_enable(output->panel);
940 }
941 
942 static int
943 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
944 			       struct drm_crtc_state *crtc_state,
945 			       struct drm_connector_state *conn_state)
946 {
947 	struct tegra_output *output = encoder_to_output(encoder);
948 	struct tegra_dsi_state *state = to_dsi_state(conn_state);
949 	struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
950 	struct tegra_dsi *dsi = to_dsi(output);
951 	unsigned int scdiv;
952 	unsigned long plld;
953 	int err;
954 
955 	state->pclk = crtc_state->mode.clock * 1000;
956 
957 	err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
958 	if (err < 0)
959 		return err;
960 
961 	state->lanes = tegra_dsi_get_lanes(dsi);
962 
963 	err = tegra_dsi_get_format(dsi->format, &state->format);
964 	if (err < 0)
965 		return err;
966 
967 	state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
968 
969 	/* compute byte clock */
970 	state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
971 
972 	DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
973 		      state->lanes);
974 	DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
975 		      state->vrefresh);
976 	DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
977 
978 	/*
979 	 * Compute bit clock and round up to the next MHz.
980 	 */
981 	plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
982 	state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
983 
984 	err = mipi_dphy_timing_get_default(&state->timing, state->period);
985 	if (err < 0)
986 		return err;
987 
988 	err = mipi_dphy_timing_validate(&state->timing, state->period);
989 	if (err < 0) {
990 		dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
991 		return err;
992 	}
993 
994 	/*
995 	 * We divide the frequency by two here, but we make up for that by
996 	 * setting the shift clock divider (further below) to half of the
997 	 * correct value.
998 	 */
999 	plld /= 2;
1000 
1001 	/*
1002 	 * Derive pixel clock from bit clock using the shift clock divider.
1003 	 * Note that this is only half of what we would expect, but we need
1004 	 * that to make up for the fact that we divided the bit clock by a
1005 	 * factor of two above.
1006 	 *
1007 	 * It's not clear exactly why this is necessary, but the display is
1008 	 * not working properly otherwise. Perhaps the PLLs cannot generate
1009 	 * frequencies sufficiently high.
1010 	 */
1011 	scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1012 
1013 	err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1014 					 plld, scdiv);
1015 	if (err < 0) {
1016 		dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1017 		return err;
1018 	}
1019 
1020 	return err;
1021 }
1022 
1023 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1024 	.disable = tegra_dsi_encoder_disable,
1025 	.enable = tegra_dsi_encoder_enable,
1026 	.atomic_check = tegra_dsi_encoder_atomic_check,
1027 };
1028 
1029 static int tegra_dsi_init(struct host1x_client *client)
1030 {
1031 	struct drm_device *drm = dev_get_drvdata(client->parent);
1032 	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1033 	int err;
1034 
1035 	/* Gangsters must not register their own outputs. */
1036 	if (!dsi->master) {
1037 		dsi->output.dev = client->dev;
1038 
1039 		drm_connector_init(drm, &dsi->output.connector,
1040 				   &tegra_dsi_connector_funcs,
1041 				   DRM_MODE_CONNECTOR_DSI);
1042 		drm_connector_helper_add(&dsi->output.connector,
1043 					 &tegra_dsi_connector_helper_funcs);
1044 		dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1045 
1046 		drm_encoder_init(drm, &dsi->output.encoder,
1047 				 &tegra_dsi_encoder_funcs,
1048 				 DRM_MODE_ENCODER_DSI, NULL);
1049 		drm_encoder_helper_add(&dsi->output.encoder,
1050 				       &tegra_dsi_encoder_helper_funcs);
1051 
1052 		drm_connector_attach_encoder(&dsi->output.connector,
1053 						  &dsi->output.encoder);
1054 		drm_connector_register(&dsi->output.connector);
1055 
1056 		err = tegra_output_init(drm, &dsi->output);
1057 		if (err < 0)
1058 			dev_err(dsi->dev, "failed to initialize output: %d\n",
1059 				err);
1060 
1061 		dsi->output.encoder.possible_crtcs = 0x3;
1062 	}
1063 
1064 	return 0;
1065 }
1066 
1067 static int tegra_dsi_exit(struct host1x_client *client)
1068 {
1069 	struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1070 
1071 	tegra_output_exit(&dsi->output);
1072 
1073 	return 0;
1074 }
1075 
1076 static const struct host1x_client_ops dsi_client_ops = {
1077 	.init = tegra_dsi_init,
1078 	.exit = tegra_dsi_exit,
1079 };
1080 
1081 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1082 {
1083 	struct clk *parent;
1084 	int err;
1085 
1086 	parent = clk_get_parent(dsi->clk);
1087 	if (!parent)
1088 		return -EINVAL;
1089 
1090 	err = clk_set_parent(parent, dsi->clk_parent);
1091 	if (err < 0)
1092 		return err;
1093 
1094 	return 0;
1095 }
1096 
1097 static const char * const error_report[16] = {
1098 	"SoT Error",
1099 	"SoT Sync Error",
1100 	"EoT Sync Error",
1101 	"Escape Mode Entry Command Error",
1102 	"Low-Power Transmit Sync Error",
1103 	"Peripheral Timeout Error",
1104 	"False Control Error",
1105 	"Contention Detected",
1106 	"ECC Error, single-bit",
1107 	"ECC Error, multi-bit",
1108 	"Checksum Error",
1109 	"DSI Data Type Not Recognized",
1110 	"DSI VC ID Invalid",
1111 	"Invalid Transmission Length",
1112 	"Reserved",
1113 	"DSI Protocol Violation",
1114 };
1115 
1116 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1117 				       const struct mipi_dsi_msg *msg,
1118 				       size_t count)
1119 {
1120 	u8 *rx = msg->rx_buf;
1121 	unsigned int i, j, k;
1122 	size_t size = 0;
1123 	u16 errors;
1124 	u32 value;
1125 
1126 	/* read and parse packet header */
1127 	value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1128 
1129 	switch (value & 0x3f) {
1130 	case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1131 		errors = (value >> 8) & 0xffff;
1132 		dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1133 			errors);
1134 		for (i = 0; i < ARRAY_SIZE(error_report); i++)
1135 			if (errors & BIT(i))
1136 				dev_dbg(dsi->dev, "  %2u: %s\n", i,
1137 					error_report[i]);
1138 		break;
1139 
1140 	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1141 		rx[0] = (value >> 8) & 0xff;
1142 		size = 1;
1143 		break;
1144 
1145 	case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1146 		rx[0] = (value >>  8) & 0xff;
1147 		rx[1] = (value >> 16) & 0xff;
1148 		size = 2;
1149 		break;
1150 
1151 	case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1152 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1153 		break;
1154 
1155 	case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1156 		size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1157 		break;
1158 
1159 	default:
1160 		dev_err(dsi->dev, "unhandled response type: %02x\n",
1161 			value & 0x3f);
1162 		return -EPROTO;
1163 	}
1164 
1165 	size = min(size, msg->rx_len);
1166 
1167 	if (msg->rx_buf && size > 0) {
1168 		for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1169 			u8 *rx = msg->rx_buf + j;
1170 
1171 			value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1172 
1173 			for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1174 				rx[j + k] = (value >> (k << 3)) & 0xff;
1175 		}
1176 	}
1177 
1178 	return size;
1179 }
1180 
1181 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1182 {
1183 	tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1184 
1185 	timeout = jiffies + msecs_to_jiffies(timeout);
1186 
1187 	while (time_before(jiffies, timeout)) {
1188 		u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1189 		if ((value & DSI_TRIGGER_HOST) == 0)
1190 			return 0;
1191 
1192 		usleep_range(1000, 2000);
1193 	}
1194 
1195 	DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1196 	return -ETIMEDOUT;
1197 }
1198 
1199 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1200 				       unsigned long timeout)
1201 {
1202 	timeout = jiffies + msecs_to_jiffies(250);
1203 
1204 	while (time_before(jiffies, timeout)) {
1205 		u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1206 		u8 count = value & 0x1f;
1207 
1208 		if (count > 0)
1209 			return count;
1210 
1211 		usleep_range(1000, 2000);
1212 	}
1213 
1214 	DRM_DEBUG_KMS("peripheral returned no data\n");
1215 	return -ETIMEDOUT;
1216 }
1217 
1218 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1219 			      const void *buffer, size_t size)
1220 {
1221 	const u8 *buf = buffer;
1222 	size_t i, j;
1223 	u32 value;
1224 
1225 	for (j = 0; j < size; j += 4) {
1226 		value = 0;
1227 
1228 		for (i = 0; i < 4 && j + i < size; i++)
1229 			value |= buf[j + i] << (i << 3);
1230 
1231 		tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1232 	}
1233 }
1234 
1235 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1236 				       const struct mipi_dsi_msg *msg)
1237 {
1238 	struct tegra_dsi *dsi = host_to_tegra(host);
1239 	struct mipi_dsi_packet packet;
1240 	const u8 *header;
1241 	size_t count;
1242 	ssize_t err;
1243 	u32 value;
1244 
1245 	err = mipi_dsi_create_packet(&packet, msg);
1246 	if (err < 0)
1247 		return err;
1248 
1249 	header = packet.header;
1250 
1251 	/* maximum FIFO depth is 1920 words */
1252 	if (packet.size > dsi->video_fifo_depth * 4)
1253 		return -ENOSPC;
1254 
1255 	/* reset underflow/overflow flags */
1256 	value = tegra_dsi_readl(dsi, DSI_STATUS);
1257 	if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1258 		value = DSI_HOST_CONTROL_FIFO_RESET;
1259 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1260 		usleep_range(10, 20);
1261 	}
1262 
1263 	value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1264 	value |= DSI_POWER_CONTROL_ENABLE;
1265 	tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1266 
1267 	usleep_range(5000, 10000);
1268 
1269 	value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1270 		DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1271 
1272 	if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1273 		value |= DSI_HOST_CONTROL_HS;
1274 
1275 	/*
1276 	 * The host FIFO has a maximum of 64 words, so larger transmissions
1277 	 * need to use the video FIFO.
1278 	 */
1279 	if (packet.size > dsi->host_fifo_depth * 4)
1280 		value |= DSI_HOST_CONTROL_FIFO_SEL;
1281 
1282 	tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1283 
1284 	/*
1285 	 * For reads and messages with explicitly requested ACK, generate a
1286 	 * BTA sequence after the transmission of the packet.
1287 	 */
1288 	if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1289 	    (msg->rx_buf && msg->rx_len > 0)) {
1290 		value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1291 		value |= DSI_HOST_CONTROL_PKT_BTA;
1292 		tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1293 	}
1294 
1295 	value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1296 	tegra_dsi_writel(dsi, value, DSI_CONTROL);
1297 
1298 	/* write packet header, ECC is generated by hardware */
1299 	value = header[2] << 16 | header[1] << 8 | header[0];
1300 	tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1301 
1302 	/* write payload (if any) */
1303 	if (packet.payload_length > 0)
1304 		tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1305 				  packet.payload_length);
1306 
1307 	err = tegra_dsi_transmit(dsi, 250);
1308 	if (err < 0)
1309 		return err;
1310 
1311 	if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1312 	    (msg->rx_buf && msg->rx_len > 0)) {
1313 		err = tegra_dsi_wait_for_response(dsi, 250);
1314 		if (err < 0)
1315 			return err;
1316 
1317 		count = err;
1318 
1319 		value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1320 		switch (value) {
1321 		case 0x84:
1322 			/*
1323 			dev_dbg(dsi->dev, "ACK\n");
1324 			*/
1325 			break;
1326 
1327 		case 0x87:
1328 			/*
1329 			dev_dbg(dsi->dev, "ESCAPE\n");
1330 			*/
1331 			break;
1332 
1333 		default:
1334 			dev_err(dsi->dev, "unknown status: %08x\n", value);
1335 			break;
1336 		}
1337 
1338 		if (count > 1) {
1339 			err = tegra_dsi_read_response(dsi, msg, count);
1340 			if (err < 0)
1341 				dev_err(dsi->dev,
1342 					"failed to parse response: %zd\n",
1343 					err);
1344 			else {
1345 				/*
1346 				 * For read commands, return the number of
1347 				 * bytes returned by the peripheral.
1348 				 */
1349 				count = err;
1350 			}
1351 		}
1352 	} else {
1353 		/*
1354 		 * For write commands, we have transmitted the 4-byte header
1355 		 * plus the variable-length payload.
1356 		 */
1357 		count = 4 + packet.payload_length;
1358 	}
1359 
1360 	return count;
1361 }
1362 
1363 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1364 {
1365 	struct clk *parent;
1366 	int err;
1367 
1368 	/* make sure both DSI controllers share the same PLL */
1369 	parent = clk_get_parent(dsi->slave->clk);
1370 	if (!parent)
1371 		return -EINVAL;
1372 
1373 	err = clk_set_parent(parent, dsi->clk_parent);
1374 	if (err < 0)
1375 		return err;
1376 
1377 	return 0;
1378 }
1379 
1380 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1381 				 struct mipi_dsi_device *device)
1382 {
1383 	struct tegra_dsi *dsi = host_to_tegra(host);
1384 
1385 	dsi->flags = device->mode_flags;
1386 	dsi->format = device->format;
1387 	dsi->lanes = device->lanes;
1388 
1389 	if (dsi->slave) {
1390 		int err;
1391 
1392 		dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1393 			dev_name(&device->dev));
1394 
1395 		err = tegra_dsi_ganged_setup(dsi);
1396 		if (err < 0) {
1397 			dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1398 				err);
1399 			return err;
1400 		}
1401 	}
1402 
1403 	/*
1404 	 * Slaves don't have a panel associated with them, so they provide
1405 	 * merely the second channel.
1406 	 */
1407 	if (!dsi->master) {
1408 		struct tegra_output *output = &dsi->output;
1409 
1410 		output->panel = of_drm_find_panel(device->dev.of_node);
1411 		if (IS_ERR(output->panel))
1412 			output->panel = NULL;
1413 
1414 		if (output->panel && output->connector.dev) {
1415 			drm_panel_attach(output->panel, &output->connector);
1416 			drm_helper_hpd_irq_event(output->connector.dev);
1417 		}
1418 	}
1419 
1420 	return 0;
1421 }
1422 
1423 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1424 				 struct mipi_dsi_device *device)
1425 {
1426 	struct tegra_dsi *dsi = host_to_tegra(host);
1427 	struct tegra_output *output = &dsi->output;
1428 
1429 	if (output->panel && &device->dev == output->panel->dev) {
1430 		output->panel = NULL;
1431 
1432 		if (output->connector.dev)
1433 			drm_helper_hpd_irq_event(output->connector.dev);
1434 	}
1435 
1436 	return 0;
1437 }
1438 
1439 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1440 	.attach = tegra_dsi_host_attach,
1441 	.detach = tegra_dsi_host_detach,
1442 	.transfer = tegra_dsi_host_transfer,
1443 };
1444 
1445 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1446 {
1447 	struct device_node *np;
1448 
1449 	np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1450 	if (np) {
1451 		struct platform_device *gangster = of_find_device_by_node(np);
1452 
1453 		dsi->slave = platform_get_drvdata(gangster);
1454 		of_node_put(np);
1455 
1456 		if (!dsi->slave)
1457 			return -EPROBE_DEFER;
1458 
1459 		dsi->slave->master = dsi;
1460 	}
1461 
1462 	return 0;
1463 }
1464 
1465 static int tegra_dsi_probe(struct platform_device *pdev)
1466 {
1467 	struct tegra_dsi *dsi;
1468 	struct resource *regs;
1469 	int err;
1470 
1471 	dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1472 	if (!dsi)
1473 		return -ENOMEM;
1474 
1475 	dsi->output.dev = dsi->dev = &pdev->dev;
1476 	dsi->video_fifo_depth = 1920;
1477 	dsi->host_fifo_depth = 64;
1478 
1479 	err = tegra_dsi_ganged_probe(dsi);
1480 	if (err < 0)
1481 		return err;
1482 
1483 	err = tegra_output_probe(&dsi->output);
1484 	if (err < 0)
1485 		return err;
1486 
1487 	dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1488 
1489 	/*
1490 	 * Assume these values by default. When a DSI peripheral driver
1491 	 * attaches to the DSI host, the parameters will be taken from
1492 	 * the attached device.
1493 	 */
1494 	dsi->flags = MIPI_DSI_MODE_VIDEO;
1495 	dsi->format = MIPI_DSI_FMT_RGB888;
1496 	dsi->lanes = 4;
1497 
1498 	if (!pdev->dev.pm_domain) {
1499 		dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1500 		if (IS_ERR(dsi->rst))
1501 			return PTR_ERR(dsi->rst);
1502 	}
1503 
1504 	dsi->clk = devm_clk_get(&pdev->dev, NULL);
1505 	if (IS_ERR(dsi->clk)) {
1506 		dev_err(&pdev->dev, "cannot get DSI clock\n");
1507 		return PTR_ERR(dsi->clk);
1508 	}
1509 
1510 	dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1511 	if (IS_ERR(dsi->clk_lp)) {
1512 		dev_err(&pdev->dev, "cannot get low-power clock\n");
1513 		return PTR_ERR(dsi->clk_lp);
1514 	}
1515 
1516 	dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1517 	if (IS_ERR(dsi->clk_parent)) {
1518 		dev_err(&pdev->dev, "cannot get parent clock\n");
1519 		return PTR_ERR(dsi->clk_parent);
1520 	}
1521 
1522 	dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1523 	if (IS_ERR(dsi->vdd)) {
1524 		dev_err(&pdev->dev, "cannot get VDD supply\n");
1525 		return PTR_ERR(dsi->vdd);
1526 	}
1527 
1528 	err = tegra_dsi_setup_clocks(dsi);
1529 	if (err < 0) {
1530 		dev_err(&pdev->dev, "cannot setup clocks\n");
1531 		return err;
1532 	}
1533 
1534 	regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1535 	dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1536 	if (IS_ERR(dsi->regs))
1537 		return PTR_ERR(dsi->regs);
1538 
1539 	dsi->mipi = tegra_mipi_request(&pdev->dev);
1540 	if (IS_ERR(dsi->mipi))
1541 		return PTR_ERR(dsi->mipi);
1542 
1543 	dsi->host.ops = &tegra_dsi_host_ops;
1544 	dsi->host.dev = &pdev->dev;
1545 
1546 	err = mipi_dsi_host_register(&dsi->host);
1547 	if (err < 0) {
1548 		dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1549 		goto mipi_free;
1550 	}
1551 
1552 	platform_set_drvdata(pdev, dsi);
1553 	pm_runtime_enable(&pdev->dev);
1554 
1555 	INIT_LIST_HEAD(&dsi->client.list);
1556 	dsi->client.ops = &dsi_client_ops;
1557 	dsi->client.dev = &pdev->dev;
1558 
1559 	err = host1x_client_register(&dsi->client);
1560 	if (err < 0) {
1561 		dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1562 			err);
1563 		goto unregister;
1564 	}
1565 
1566 	return 0;
1567 
1568 unregister:
1569 	mipi_dsi_host_unregister(&dsi->host);
1570 mipi_free:
1571 	tegra_mipi_free(dsi->mipi);
1572 	return err;
1573 }
1574 
1575 static int tegra_dsi_remove(struct platform_device *pdev)
1576 {
1577 	struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1578 	int err;
1579 
1580 	pm_runtime_disable(&pdev->dev);
1581 
1582 	err = host1x_client_unregister(&dsi->client);
1583 	if (err < 0) {
1584 		dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1585 			err);
1586 		return err;
1587 	}
1588 
1589 	tegra_output_remove(&dsi->output);
1590 
1591 	mipi_dsi_host_unregister(&dsi->host);
1592 	tegra_mipi_free(dsi->mipi);
1593 
1594 	return 0;
1595 }
1596 
1597 #ifdef CONFIG_PM
1598 static int tegra_dsi_suspend(struct device *dev)
1599 {
1600 	struct tegra_dsi *dsi = dev_get_drvdata(dev);
1601 	int err;
1602 
1603 	if (dsi->rst) {
1604 		err = reset_control_assert(dsi->rst);
1605 		if (err < 0) {
1606 			dev_err(dev, "failed to assert reset: %d\n", err);
1607 			return err;
1608 		}
1609 	}
1610 
1611 	usleep_range(1000, 2000);
1612 
1613 	clk_disable_unprepare(dsi->clk_lp);
1614 	clk_disable_unprepare(dsi->clk);
1615 
1616 	regulator_disable(dsi->vdd);
1617 
1618 	return 0;
1619 }
1620 
1621 static int tegra_dsi_resume(struct device *dev)
1622 {
1623 	struct tegra_dsi *dsi = dev_get_drvdata(dev);
1624 	int err;
1625 
1626 	err = regulator_enable(dsi->vdd);
1627 	if (err < 0) {
1628 		dev_err(dsi->dev, "failed to enable VDD supply: %d\n", err);
1629 		return err;
1630 	}
1631 
1632 	err = clk_prepare_enable(dsi->clk);
1633 	if (err < 0) {
1634 		dev_err(dev, "cannot enable DSI clock: %d\n", err);
1635 		goto disable_vdd;
1636 	}
1637 
1638 	err = clk_prepare_enable(dsi->clk_lp);
1639 	if (err < 0) {
1640 		dev_err(dev, "cannot enable low-power clock: %d\n", err);
1641 		goto disable_clk;
1642 	}
1643 
1644 	usleep_range(1000, 2000);
1645 
1646 	if (dsi->rst) {
1647 		err = reset_control_deassert(dsi->rst);
1648 		if (err < 0) {
1649 			dev_err(dev, "cannot assert reset: %d\n", err);
1650 			goto disable_clk_lp;
1651 		}
1652 	}
1653 
1654 	return 0;
1655 
1656 disable_clk_lp:
1657 	clk_disable_unprepare(dsi->clk_lp);
1658 disable_clk:
1659 	clk_disable_unprepare(dsi->clk);
1660 disable_vdd:
1661 	regulator_disable(dsi->vdd);
1662 	return err;
1663 }
1664 #endif
1665 
1666 static const struct dev_pm_ops tegra_dsi_pm_ops = {
1667 	SET_RUNTIME_PM_OPS(tegra_dsi_suspend, tegra_dsi_resume, NULL)
1668 };
1669 
1670 static const struct of_device_id tegra_dsi_of_match[] = {
1671 	{ .compatible = "nvidia,tegra210-dsi", },
1672 	{ .compatible = "nvidia,tegra132-dsi", },
1673 	{ .compatible = "nvidia,tegra124-dsi", },
1674 	{ .compatible = "nvidia,tegra114-dsi", },
1675 	{ },
1676 };
1677 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1678 
1679 struct platform_driver tegra_dsi_driver = {
1680 	.driver = {
1681 		.name = "tegra-dsi",
1682 		.of_match_table = tegra_dsi_of_match,
1683 		.pm = &tegra_dsi_pm_ops,
1684 	},
1685 	.probe = tegra_dsi_probe,
1686 	.remove = tegra_dsi_remove,
1687 };
1688