1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/debugfs.h> 8 #include <linux/delay.h> 9 #include <linux/host1x.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/of_platform.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regulator/consumer.h> 16 #include <linux/reset.h> 17 18 #include <video/mipi_display.h> 19 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_debugfs.h> 22 #include <drm/drm_file.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_simple_kms_helper.h> 26 27 #include "dc.h" 28 #include "drm.h" 29 #include "dsi.h" 30 #include "mipi-phy.h" 31 #include "trace.h" 32 33 struct tegra_dsi_state { 34 struct drm_connector_state base; 35 36 struct mipi_dphy_timing timing; 37 unsigned long period; 38 39 unsigned int vrefresh; 40 unsigned int lanes; 41 unsigned long pclk; 42 unsigned long bclk; 43 44 enum tegra_dsi_format format; 45 unsigned int mul; 46 unsigned int div; 47 }; 48 49 static inline struct tegra_dsi_state * 50 to_dsi_state(struct drm_connector_state *state) 51 { 52 return container_of(state, struct tegra_dsi_state, base); 53 } 54 55 struct tegra_dsi { 56 struct host1x_client client; 57 struct tegra_output output; 58 struct device *dev; 59 60 void __iomem *regs; 61 62 struct reset_control *rst; 63 struct clk *clk_parent; 64 struct clk *clk_lp; 65 struct clk *clk; 66 67 struct drm_info_list *debugfs_files; 68 69 unsigned long flags; 70 enum mipi_dsi_pixel_format format; 71 unsigned int lanes; 72 73 struct tegra_mipi_device *mipi; 74 struct mipi_dsi_host host; 75 76 struct regulator *vdd; 77 78 unsigned int video_fifo_depth; 79 unsigned int host_fifo_depth; 80 81 /* for ganged-mode support */ 82 struct tegra_dsi *master; 83 struct tegra_dsi *slave; 84 }; 85 86 static inline struct tegra_dsi * 87 host1x_client_to_dsi(struct host1x_client *client) 88 { 89 return container_of(client, struct tegra_dsi, client); 90 } 91 92 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host) 93 { 94 return container_of(host, struct tegra_dsi, host); 95 } 96 97 static inline struct tegra_dsi *to_dsi(struct tegra_output *output) 98 { 99 return container_of(output, struct tegra_dsi, output); 100 } 101 102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) 103 { 104 return to_dsi_state(dsi->output.connector.state); 105 } 106 107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) 108 { 109 u32 value = readl(dsi->regs + (offset << 2)); 110 111 trace_dsi_readl(dsi->dev, offset, value); 112 113 return value; 114 } 115 116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, 117 unsigned int offset) 118 { 119 trace_dsi_writel(dsi->dev, offset, value); 120 writel(value, dsi->regs + (offset << 2)); 121 } 122 123 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 124 125 static const struct debugfs_reg32 tegra_dsi_regs[] = { 126 DEBUGFS_REG32(DSI_INCR_SYNCPT), 127 DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL), 128 DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR), 129 DEBUGFS_REG32(DSI_CTXSW), 130 DEBUGFS_REG32(DSI_RD_DATA), 131 DEBUGFS_REG32(DSI_WR_DATA), 132 DEBUGFS_REG32(DSI_POWER_CONTROL), 133 DEBUGFS_REG32(DSI_INT_ENABLE), 134 DEBUGFS_REG32(DSI_INT_STATUS), 135 DEBUGFS_REG32(DSI_INT_MASK), 136 DEBUGFS_REG32(DSI_HOST_CONTROL), 137 DEBUGFS_REG32(DSI_CONTROL), 138 DEBUGFS_REG32(DSI_SOL_DELAY), 139 DEBUGFS_REG32(DSI_MAX_THRESHOLD), 140 DEBUGFS_REG32(DSI_TRIGGER), 141 DEBUGFS_REG32(DSI_TX_CRC), 142 DEBUGFS_REG32(DSI_STATUS), 143 DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL), 144 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0), 145 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1), 146 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2), 147 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3), 148 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4), 149 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5), 150 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6), 151 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7), 152 DEBUGFS_REG32(DSI_PKT_SEQ_0_LO), 153 DEBUGFS_REG32(DSI_PKT_SEQ_0_HI), 154 DEBUGFS_REG32(DSI_PKT_SEQ_1_LO), 155 DEBUGFS_REG32(DSI_PKT_SEQ_1_HI), 156 DEBUGFS_REG32(DSI_PKT_SEQ_2_LO), 157 DEBUGFS_REG32(DSI_PKT_SEQ_2_HI), 158 DEBUGFS_REG32(DSI_PKT_SEQ_3_LO), 159 DEBUGFS_REG32(DSI_PKT_SEQ_3_HI), 160 DEBUGFS_REG32(DSI_PKT_SEQ_4_LO), 161 DEBUGFS_REG32(DSI_PKT_SEQ_4_HI), 162 DEBUGFS_REG32(DSI_PKT_SEQ_5_LO), 163 DEBUGFS_REG32(DSI_PKT_SEQ_5_HI), 164 DEBUGFS_REG32(DSI_DCS_CMDS), 165 DEBUGFS_REG32(DSI_PKT_LEN_0_1), 166 DEBUGFS_REG32(DSI_PKT_LEN_2_3), 167 DEBUGFS_REG32(DSI_PKT_LEN_4_5), 168 DEBUGFS_REG32(DSI_PKT_LEN_6_7), 169 DEBUGFS_REG32(DSI_PHY_TIMING_0), 170 DEBUGFS_REG32(DSI_PHY_TIMING_1), 171 DEBUGFS_REG32(DSI_PHY_TIMING_2), 172 DEBUGFS_REG32(DSI_BTA_TIMING), 173 DEBUGFS_REG32(DSI_TIMEOUT_0), 174 DEBUGFS_REG32(DSI_TIMEOUT_1), 175 DEBUGFS_REG32(DSI_TO_TALLY), 176 DEBUGFS_REG32(DSI_PAD_CONTROL_0), 177 DEBUGFS_REG32(DSI_PAD_CONTROL_CD), 178 DEBUGFS_REG32(DSI_PAD_CD_STATUS), 179 DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL), 180 DEBUGFS_REG32(DSI_PAD_CONTROL_1), 181 DEBUGFS_REG32(DSI_PAD_CONTROL_2), 182 DEBUGFS_REG32(DSI_PAD_CONTROL_3), 183 DEBUGFS_REG32(DSI_PAD_CONTROL_4), 184 DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL), 185 DEBUGFS_REG32(DSI_GANGED_MODE_START), 186 DEBUGFS_REG32(DSI_GANGED_MODE_SIZE), 187 DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT), 188 DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL), 189 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8), 190 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9), 191 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10), 192 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11), 193 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12), 194 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13), 195 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14), 196 DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15), 197 }; 198 199 static int tegra_dsi_show_regs(struct seq_file *s, void *data) 200 { 201 struct drm_info_node *node = s->private; 202 struct tegra_dsi *dsi = node->info_ent->data; 203 struct drm_crtc *crtc = dsi->output.encoder.crtc; 204 struct drm_device *drm = node->minor->dev; 205 unsigned int i; 206 int err = 0; 207 208 drm_modeset_lock_all(drm); 209 210 if (!crtc || !crtc->state->active) { 211 err = -EBUSY; 212 goto unlock; 213 } 214 215 for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) { 216 unsigned int offset = tegra_dsi_regs[i].offset; 217 218 seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name, 219 offset, tegra_dsi_readl(dsi, offset)); 220 } 221 222 unlock: 223 drm_modeset_unlock_all(drm); 224 return err; 225 } 226 227 static struct drm_info_list debugfs_files[] = { 228 { "regs", tegra_dsi_show_regs, 0, NULL }, 229 }; 230 231 static int tegra_dsi_late_register(struct drm_connector *connector) 232 { 233 struct tegra_output *output = connector_to_output(connector); 234 unsigned int i, count = ARRAY_SIZE(debugfs_files); 235 struct drm_minor *minor = connector->dev->primary; 236 struct dentry *root = connector->debugfs_entry; 237 struct tegra_dsi *dsi = to_dsi(output); 238 239 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 240 GFP_KERNEL); 241 if (!dsi->debugfs_files) 242 return -ENOMEM; 243 244 for (i = 0; i < count; i++) 245 dsi->debugfs_files[i].data = dsi; 246 247 drm_debugfs_create_files(dsi->debugfs_files, count, root, minor); 248 249 return 0; 250 } 251 252 static void tegra_dsi_early_unregister(struct drm_connector *connector) 253 { 254 struct tegra_output *output = connector_to_output(connector); 255 unsigned int count = ARRAY_SIZE(debugfs_files); 256 struct tegra_dsi *dsi = to_dsi(output); 257 258 drm_debugfs_remove_files(dsi->debugfs_files, count, 259 connector->dev->primary); 260 kfree(dsi->debugfs_files); 261 dsi->debugfs_files = NULL; 262 } 263 264 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9)) 265 #define PKT_LEN0(len) (((len) & 0x07) << 0) 266 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19)) 267 #define PKT_LEN1(len) (((len) & 0x07) << 10) 268 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29)) 269 #define PKT_LEN2(len) (((len) & 0x07) << 20) 270 271 #define PKT_LP (1 << 30) 272 #define NUM_PKT_SEQ 12 273 274 /* 275 * non-burst mode with sync pulses 276 */ 277 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = { 278 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 279 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 280 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 281 PKT_LP, 282 [ 1] = 0, 283 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) | 284 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 285 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 286 PKT_LP, 287 [ 3] = 0, 288 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 289 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 290 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 291 PKT_LP, 292 [ 5] = 0, 293 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 294 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 295 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 296 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 297 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 298 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 299 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 300 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 301 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) | 302 PKT_LP, 303 [ 9] = 0, 304 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 305 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) | 306 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0), 307 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) | 308 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) | 309 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4), 310 }; 311 312 /* 313 * non-burst mode with sync events 314 */ 315 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = { 316 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) | 317 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 318 PKT_LP, 319 [ 1] = 0, 320 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 321 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 322 PKT_LP, 323 [ 3] = 0, 324 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 325 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 326 PKT_LP, 327 [ 5] = 0, 328 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 329 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 330 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 331 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 332 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 333 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) | 334 PKT_LP, 335 [ 9] = 0, 336 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) | 337 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) | 338 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3), 339 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4), 340 }; 341 342 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = { 343 [ 0] = 0, 344 [ 1] = 0, 345 [ 2] = 0, 346 [ 3] = 0, 347 [ 4] = 0, 348 [ 5] = 0, 349 [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP, 350 [ 7] = 0, 351 [ 8] = 0, 352 [ 9] = 0, 353 [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP, 354 [11] = 0, 355 }; 356 357 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi, 358 unsigned long period, 359 const struct mipi_dphy_timing *timing) 360 { 361 u32 value; 362 363 value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 | 364 DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 | 365 DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 | 366 DSI_TIMING_FIELD(timing->hsprepare, period, 1); 367 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0); 368 369 value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 | 370 DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 | 371 DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 | 372 DSI_TIMING_FIELD(timing->lpx, period, 1); 373 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1); 374 375 value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 | 376 DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 | 377 DSI_TIMING_FIELD(0xff * period, period, 0) << 0; 378 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2); 379 380 value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 | 381 DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 | 382 DSI_TIMING_FIELD(timing->tago, period, 1); 383 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING); 384 385 if (dsi->slave) 386 tegra_dsi_set_phy_timing(dsi->slave, period, timing); 387 } 388 389 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format, 390 unsigned int *mulp, unsigned int *divp) 391 { 392 switch (format) { 393 case MIPI_DSI_FMT_RGB666_PACKED: 394 case MIPI_DSI_FMT_RGB888: 395 *mulp = 3; 396 *divp = 1; 397 break; 398 399 case MIPI_DSI_FMT_RGB565: 400 *mulp = 2; 401 *divp = 1; 402 break; 403 404 case MIPI_DSI_FMT_RGB666: 405 *mulp = 9; 406 *divp = 4; 407 break; 408 409 default: 410 return -EINVAL; 411 } 412 413 return 0; 414 } 415 416 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format, 417 enum tegra_dsi_format *fmt) 418 { 419 switch (format) { 420 case MIPI_DSI_FMT_RGB888: 421 *fmt = TEGRA_DSI_FORMAT_24P; 422 break; 423 424 case MIPI_DSI_FMT_RGB666: 425 *fmt = TEGRA_DSI_FORMAT_18NP; 426 break; 427 428 case MIPI_DSI_FMT_RGB666_PACKED: 429 *fmt = TEGRA_DSI_FORMAT_18P; 430 break; 431 432 case MIPI_DSI_FMT_RGB565: 433 *fmt = TEGRA_DSI_FORMAT_16P; 434 break; 435 436 default: 437 return -EINVAL; 438 } 439 440 return 0; 441 } 442 443 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start, 444 unsigned int size) 445 { 446 u32 value; 447 448 tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START); 449 tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE); 450 451 value = DSI_GANGED_MODE_CONTROL_ENABLE; 452 tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL); 453 } 454 455 static void tegra_dsi_enable(struct tegra_dsi *dsi) 456 { 457 u32 value; 458 459 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 460 value |= DSI_POWER_CONTROL_ENABLE; 461 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 462 463 if (dsi->slave) 464 tegra_dsi_enable(dsi->slave); 465 } 466 467 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi) 468 { 469 if (dsi->master) 470 return dsi->master->lanes + dsi->lanes; 471 472 if (dsi->slave) 473 return dsi->lanes + dsi->slave->lanes; 474 475 return dsi->lanes; 476 } 477 478 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe, 479 const struct drm_display_mode *mode) 480 { 481 unsigned int hact, hsw, hbp, hfp, i, mul, div; 482 struct tegra_dsi_state *state; 483 const u32 *pkt_seq; 484 u32 value; 485 486 /* XXX: pass in state into this function? */ 487 if (dsi->master) 488 state = tegra_dsi_get_state(dsi->master); 489 else 490 state = tegra_dsi_get_state(dsi); 491 492 mul = state->mul; 493 div = state->div; 494 495 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) { 496 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n"); 497 pkt_seq = pkt_seq_video_non_burst_sync_pulses; 498 } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 499 DRM_DEBUG_KMS("Non-burst video mode with sync events\n"); 500 pkt_seq = pkt_seq_video_non_burst_sync_events; 501 } else { 502 DRM_DEBUG_KMS("Command mode\n"); 503 pkt_seq = pkt_seq_command_mode; 504 } 505 506 value = DSI_CONTROL_CHANNEL(0) | 507 DSI_CONTROL_FORMAT(state->format) | 508 DSI_CONTROL_LANES(dsi->lanes - 1) | 509 DSI_CONTROL_SOURCE(pipe); 510 tegra_dsi_writel(dsi, value, DSI_CONTROL); 511 512 tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD); 513 514 value = DSI_HOST_CONTROL_HS; 515 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 516 517 value = tegra_dsi_readl(dsi, DSI_CONTROL); 518 519 if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) 520 value |= DSI_CONTROL_HS_CLK_CTRL; 521 522 value &= ~DSI_CONTROL_TX_TRIG(3); 523 524 /* enable DCS commands for command mode */ 525 if (dsi->flags & MIPI_DSI_MODE_VIDEO) 526 value &= ~DSI_CONTROL_DCS_ENABLE; 527 else 528 value |= DSI_CONTROL_DCS_ENABLE; 529 530 value |= DSI_CONTROL_VIDEO_ENABLE; 531 value &= ~DSI_CONTROL_HOST_ENABLE; 532 tegra_dsi_writel(dsi, value, DSI_CONTROL); 533 534 for (i = 0; i < NUM_PKT_SEQ; i++) 535 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i); 536 537 if (dsi->flags & MIPI_DSI_MODE_VIDEO) { 538 /* horizontal active pixels */ 539 hact = mode->hdisplay * mul / div; 540 541 /* horizontal sync width */ 542 hsw = (mode->hsync_end - mode->hsync_start) * mul / div; 543 544 /* horizontal back porch */ 545 hbp = (mode->htotal - mode->hsync_end) * mul / div; 546 547 if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0) 548 hbp += hsw; 549 550 /* horizontal front porch */ 551 hfp = (mode->hsync_start - mode->hdisplay) * mul / div; 552 553 /* subtract packet overhead */ 554 hsw -= 10; 555 hbp -= 14; 556 hfp -= 8; 557 558 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1); 559 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3); 560 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5); 561 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7); 562 563 /* set SOL delay (for non-burst mode only) */ 564 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY); 565 566 /* TODO: implement ganged mode */ 567 } else { 568 u16 bytes; 569 570 if (dsi->master || dsi->slave) { 571 /* 572 * For ganged mode, assume symmetric left-right mode. 573 */ 574 bytes = 1 + (mode->hdisplay / 2) * mul / div; 575 } else { 576 /* 1 byte (DCS command) + pixel data */ 577 bytes = 1 + mode->hdisplay * mul / div; 578 } 579 580 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1); 581 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3); 582 tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5); 583 tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7); 584 585 value = MIPI_DCS_WRITE_MEMORY_START << 8 | 586 MIPI_DCS_WRITE_MEMORY_CONTINUE; 587 tegra_dsi_writel(dsi, value, DSI_DCS_CMDS); 588 589 /* set SOL delay */ 590 if (dsi->master || dsi->slave) { 591 unsigned long delay, bclk, bclk_ganged; 592 unsigned int lanes = state->lanes; 593 594 /* SOL to valid, valid to FIFO and FIFO write delay */ 595 delay = 4 + 4 + 2; 596 delay = DIV_ROUND_UP(delay * mul, div * lanes); 597 /* FIFO read delay */ 598 delay = delay + 6; 599 600 bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes); 601 bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes); 602 value = bclk - bclk_ganged + delay + 20; 603 } else { 604 /* TODO: revisit for non-ganged mode */ 605 value = 8 * mul / div; 606 } 607 608 tegra_dsi_writel(dsi, value, DSI_SOL_DELAY); 609 } 610 611 if (dsi->slave) { 612 tegra_dsi_configure(dsi->slave, pipe, mode); 613 614 /* 615 * TODO: Support modes other than symmetrical left-right 616 * split. 617 */ 618 tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2); 619 tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2, 620 mode->hdisplay / 2); 621 } 622 } 623 624 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout) 625 { 626 u32 value; 627 628 timeout = jiffies + msecs_to_jiffies(timeout); 629 630 while (time_before(jiffies, timeout)) { 631 value = tegra_dsi_readl(dsi, DSI_STATUS); 632 if (value & DSI_STATUS_IDLE) 633 return 0; 634 635 usleep_range(1000, 2000); 636 } 637 638 return -ETIMEDOUT; 639 } 640 641 static void tegra_dsi_video_disable(struct tegra_dsi *dsi) 642 { 643 u32 value; 644 645 value = tegra_dsi_readl(dsi, DSI_CONTROL); 646 value &= ~DSI_CONTROL_VIDEO_ENABLE; 647 tegra_dsi_writel(dsi, value, DSI_CONTROL); 648 649 if (dsi->slave) 650 tegra_dsi_video_disable(dsi->slave); 651 } 652 653 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi) 654 { 655 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START); 656 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE); 657 tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL); 658 } 659 660 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi) 661 { 662 u32 value; 663 664 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); 665 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0); 666 667 return 0; 668 } 669 670 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi) 671 { 672 u32 value; 673 674 /* 675 * XXX Is this still needed? The module reset is deasserted right 676 * before this function is called. 677 */ 678 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0); 679 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1); 680 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2); 681 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3); 682 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4); 683 684 /* start calibration */ 685 tegra_dsi_pad_enable(dsi); 686 687 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | 688 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) | 689 DSI_PAD_OUT_CLK(0x0); 690 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2); 691 692 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | 693 DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3); 694 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3); 695 696 return tegra_mipi_calibrate(dsi->mipi); 697 } 698 699 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk, 700 unsigned int vrefresh) 701 { 702 unsigned int timeout; 703 u32 value; 704 705 /* one frame high-speed transmission timeout */ 706 timeout = (bclk / vrefresh) / 512; 707 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); 708 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0); 709 710 /* 2 ms peripheral timeout for panel */ 711 timeout = 2 * bclk / 512 * 1000; 712 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); 713 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1); 714 715 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); 716 tegra_dsi_writel(dsi, value, DSI_TO_TALLY); 717 718 if (dsi->slave) 719 tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh); 720 } 721 722 static void tegra_dsi_disable(struct tegra_dsi *dsi) 723 { 724 u32 value; 725 726 if (dsi->slave) { 727 tegra_dsi_ganged_disable(dsi->slave); 728 tegra_dsi_ganged_disable(dsi); 729 } 730 731 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 732 value &= ~DSI_POWER_CONTROL_ENABLE; 733 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 734 735 if (dsi->slave) 736 tegra_dsi_disable(dsi->slave); 737 738 usleep_range(5000, 10000); 739 } 740 741 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi) 742 { 743 u32 value; 744 745 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 746 value &= ~DSI_POWER_CONTROL_ENABLE; 747 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 748 749 usleep_range(300, 1000); 750 751 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 752 value |= DSI_POWER_CONTROL_ENABLE; 753 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 754 755 usleep_range(300, 1000); 756 757 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 758 if (value) 759 tegra_dsi_writel(dsi, 0, DSI_TRIGGER); 760 761 if (dsi->slave) 762 tegra_dsi_soft_reset(dsi->slave); 763 } 764 765 static void tegra_dsi_connector_reset(struct drm_connector *connector) 766 { 767 struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 768 769 if (!state) 770 return; 771 772 if (connector->state) { 773 __drm_atomic_helper_connector_destroy_state(connector->state); 774 kfree(connector->state); 775 } 776 777 __drm_atomic_helper_connector_reset(connector, &state->base); 778 } 779 780 static struct drm_connector_state * 781 tegra_dsi_connector_duplicate_state(struct drm_connector *connector) 782 { 783 struct tegra_dsi_state *state = to_dsi_state(connector->state); 784 struct tegra_dsi_state *copy; 785 786 copy = kmemdup(state, sizeof(*state), GFP_KERNEL); 787 if (!copy) 788 return NULL; 789 790 __drm_atomic_helper_connector_duplicate_state(connector, 791 ©->base); 792 793 return ©->base; 794 } 795 796 static const struct drm_connector_funcs tegra_dsi_connector_funcs = { 797 .reset = tegra_dsi_connector_reset, 798 .detect = tegra_output_connector_detect, 799 .fill_modes = drm_helper_probe_single_connector_modes, 800 .destroy = tegra_output_connector_destroy, 801 .atomic_duplicate_state = tegra_dsi_connector_duplicate_state, 802 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 803 .late_register = tegra_dsi_late_register, 804 .early_unregister = tegra_dsi_early_unregister, 805 }; 806 807 static enum drm_mode_status 808 tegra_dsi_connector_mode_valid(struct drm_connector *connector, 809 struct drm_display_mode *mode) 810 { 811 return MODE_OK; 812 } 813 814 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = { 815 .get_modes = tegra_output_connector_get_modes, 816 .mode_valid = tegra_dsi_connector_mode_valid, 817 }; 818 819 static void tegra_dsi_unprepare(struct tegra_dsi *dsi) 820 { 821 int err; 822 823 if (dsi->slave) 824 tegra_dsi_unprepare(dsi->slave); 825 826 err = tegra_mipi_disable(dsi->mipi); 827 if (err < 0) 828 dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n", 829 err); 830 831 err = host1x_client_suspend(&dsi->client); 832 if (err < 0) 833 dev_err(dsi->dev, "failed to suspend: %d\n", err); 834 } 835 836 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder) 837 { 838 struct tegra_output *output = encoder_to_output(encoder); 839 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 840 struct tegra_dsi *dsi = to_dsi(output); 841 u32 value; 842 int err; 843 844 if (output->panel) 845 drm_panel_disable(output->panel); 846 847 tegra_dsi_video_disable(dsi); 848 849 /* 850 * The following accesses registers of the display controller, so make 851 * sure it's only executed when the output is attached to one. 852 */ 853 if (dc) { 854 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 855 value &= ~DSI_ENABLE; 856 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 857 858 tegra_dc_commit(dc); 859 } 860 861 err = tegra_dsi_wait_idle(dsi, 100); 862 if (err < 0) 863 dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err); 864 865 tegra_dsi_soft_reset(dsi); 866 867 if (output->panel) 868 drm_panel_unprepare(output->panel); 869 870 tegra_dsi_disable(dsi); 871 872 tegra_dsi_unprepare(dsi); 873 } 874 875 static int tegra_dsi_prepare(struct tegra_dsi *dsi) 876 { 877 int err; 878 879 err = host1x_client_resume(&dsi->client); 880 if (err < 0) { 881 dev_err(dsi->dev, "failed to resume: %d\n", err); 882 return err; 883 } 884 885 err = tegra_mipi_enable(dsi->mipi); 886 if (err < 0) 887 dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n", 888 err); 889 890 err = tegra_dsi_pad_calibrate(dsi); 891 if (err < 0) 892 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err); 893 894 if (dsi->slave) 895 tegra_dsi_prepare(dsi->slave); 896 897 return 0; 898 } 899 900 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder) 901 { 902 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 903 struct tegra_output *output = encoder_to_output(encoder); 904 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); 905 struct tegra_dsi *dsi = to_dsi(output); 906 struct tegra_dsi_state *state; 907 u32 value; 908 int err; 909 910 err = tegra_dsi_prepare(dsi); 911 if (err < 0) { 912 dev_err(dsi->dev, "failed to prepare: %d\n", err); 913 return; 914 } 915 916 state = tegra_dsi_get_state(dsi); 917 918 tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh); 919 920 /* 921 * The D-PHY timing fields are expressed in byte-clock cycles, so 922 * multiply the period by 8. 923 */ 924 tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing); 925 926 if (output->panel) 927 drm_panel_prepare(output->panel); 928 929 tegra_dsi_configure(dsi, dc->pipe, mode); 930 931 /* enable display controller */ 932 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 933 value |= DSI_ENABLE; 934 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 935 936 tegra_dc_commit(dc); 937 938 /* enable DSI controller */ 939 tegra_dsi_enable(dsi); 940 941 if (output->panel) 942 drm_panel_enable(output->panel); 943 } 944 945 static int 946 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder, 947 struct drm_crtc_state *crtc_state, 948 struct drm_connector_state *conn_state) 949 { 950 struct tegra_output *output = encoder_to_output(encoder); 951 struct tegra_dsi_state *state = to_dsi_state(conn_state); 952 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); 953 struct tegra_dsi *dsi = to_dsi(output); 954 unsigned int scdiv; 955 unsigned long plld; 956 int err; 957 958 state->pclk = crtc_state->mode.clock * 1000; 959 960 err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div); 961 if (err < 0) 962 return err; 963 964 state->lanes = tegra_dsi_get_lanes(dsi); 965 966 err = tegra_dsi_get_format(dsi->format, &state->format); 967 if (err < 0) 968 return err; 969 970 state->vrefresh = drm_mode_vrefresh(&crtc_state->mode); 971 972 /* compute byte clock */ 973 state->bclk = (state->pclk * state->mul) / (state->div * state->lanes); 974 975 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div, 976 state->lanes); 977 DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format, 978 state->vrefresh); 979 DRM_DEBUG_KMS("bclk: %lu\n", state->bclk); 980 981 /* 982 * Compute bit clock and round up to the next MHz. 983 */ 984 plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC; 985 state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld); 986 987 err = mipi_dphy_timing_get_default(&state->timing, state->period); 988 if (err < 0) 989 return err; 990 991 err = mipi_dphy_timing_validate(&state->timing, state->period); 992 if (err < 0) { 993 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err); 994 return err; 995 } 996 997 /* 998 * We divide the frequency by two here, but we make up for that by 999 * setting the shift clock divider (further below) to half of the 1000 * correct value. 1001 */ 1002 plld /= 2; 1003 1004 /* 1005 * Derive pixel clock from bit clock using the shift clock divider. 1006 * Note that this is only half of what we would expect, but we need 1007 * that to make up for the fact that we divided the bit clock by a 1008 * factor of two above. 1009 * 1010 * It's not clear exactly why this is necessary, but the display is 1011 * not working properly otherwise. Perhaps the PLLs cannot generate 1012 * frequencies sufficiently high. 1013 */ 1014 scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2; 1015 1016 err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent, 1017 plld, scdiv); 1018 if (err < 0) { 1019 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); 1020 return err; 1021 } 1022 1023 return err; 1024 } 1025 1026 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = { 1027 .disable = tegra_dsi_encoder_disable, 1028 .enable = tegra_dsi_encoder_enable, 1029 .atomic_check = tegra_dsi_encoder_atomic_check, 1030 }; 1031 1032 static int tegra_dsi_init(struct host1x_client *client) 1033 { 1034 struct drm_device *drm = dev_get_drvdata(client->host); 1035 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1036 int err; 1037 1038 /* Gangsters must not register their own outputs. */ 1039 if (!dsi->master) { 1040 dsi->output.dev = client->dev; 1041 1042 drm_connector_init(drm, &dsi->output.connector, 1043 &tegra_dsi_connector_funcs, 1044 DRM_MODE_CONNECTOR_DSI); 1045 drm_connector_helper_add(&dsi->output.connector, 1046 &tegra_dsi_connector_helper_funcs); 1047 dsi->output.connector.dpms = DRM_MODE_DPMS_OFF; 1048 1049 drm_simple_encoder_init(drm, &dsi->output.encoder, 1050 DRM_MODE_ENCODER_DSI); 1051 drm_encoder_helper_add(&dsi->output.encoder, 1052 &tegra_dsi_encoder_helper_funcs); 1053 1054 drm_connector_attach_encoder(&dsi->output.connector, 1055 &dsi->output.encoder); 1056 drm_connector_register(&dsi->output.connector); 1057 1058 err = tegra_output_init(drm, &dsi->output); 1059 if (err < 0) 1060 dev_err(dsi->dev, "failed to initialize output: %d\n", 1061 err); 1062 1063 dsi->output.encoder.possible_crtcs = 0x3; 1064 } 1065 1066 return 0; 1067 } 1068 1069 static int tegra_dsi_exit(struct host1x_client *client) 1070 { 1071 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1072 1073 tegra_output_exit(&dsi->output); 1074 1075 return 0; 1076 } 1077 1078 static int tegra_dsi_runtime_suspend(struct host1x_client *client) 1079 { 1080 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1081 struct device *dev = client->dev; 1082 int err; 1083 1084 if (dsi->rst) { 1085 err = reset_control_assert(dsi->rst); 1086 if (err < 0) { 1087 dev_err(dev, "failed to assert reset: %d\n", err); 1088 return err; 1089 } 1090 } 1091 1092 usleep_range(1000, 2000); 1093 1094 clk_disable_unprepare(dsi->clk_lp); 1095 clk_disable_unprepare(dsi->clk); 1096 1097 regulator_disable(dsi->vdd); 1098 pm_runtime_put_sync(dev); 1099 1100 return 0; 1101 } 1102 1103 static int tegra_dsi_runtime_resume(struct host1x_client *client) 1104 { 1105 struct tegra_dsi *dsi = host1x_client_to_dsi(client); 1106 struct device *dev = client->dev; 1107 int err; 1108 1109 err = pm_runtime_get_sync(dev); 1110 if (err < 0) { 1111 dev_err(dev, "failed to get runtime PM: %d\n", err); 1112 return err; 1113 } 1114 1115 err = regulator_enable(dsi->vdd); 1116 if (err < 0) { 1117 dev_err(dev, "failed to enable VDD supply: %d\n", err); 1118 goto put_rpm; 1119 } 1120 1121 err = clk_prepare_enable(dsi->clk); 1122 if (err < 0) { 1123 dev_err(dev, "cannot enable DSI clock: %d\n", err); 1124 goto disable_vdd; 1125 } 1126 1127 err = clk_prepare_enable(dsi->clk_lp); 1128 if (err < 0) { 1129 dev_err(dev, "cannot enable low-power clock: %d\n", err); 1130 goto disable_clk; 1131 } 1132 1133 usleep_range(1000, 2000); 1134 1135 if (dsi->rst) { 1136 err = reset_control_deassert(dsi->rst); 1137 if (err < 0) { 1138 dev_err(dev, "cannot assert reset: %d\n", err); 1139 goto disable_clk_lp; 1140 } 1141 } 1142 1143 return 0; 1144 1145 disable_clk_lp: 1146 clk_disable_unprepare(dsi->clk_lp); 1147 disable_clk: 1148 clk_disable_unprepare(dsi->clk); 1149 disable_vdd: 1150 regulator_disable(dsi->vdd); 1151 put_rpm: 1152 pm_runtime_put_sync(dev); 1153 return err; 1154 } 1155 1156 static const struct host1x_client_ops dsi_client_ops = { 1157 .init = tegra_dsi_init, 1158 .exit = tegra_dsi_exit, 1159 .suspend = tegra_dsi_runtime_suspend, 1160 .resume = tegra_dsi_runtime_resume, 1161 }; 1162 1163 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi) 1164 { 1165 struct clk *parent; 1166 int err; 1167 1168 parent = clk_get_parent(dsi->clk); 1169 if (!parent) 1170 return -EINVAL; 1171 1172 err = clk_set_parent(parent, dsi->clk_parent); 1173 if (err < 0) 1174 return err; 1175 1176 return 0; 1177 } 1178 1179 static const char * const error_report[16] = { 1180 "SoT Error", 1181 "SoT Sync Error", 1182 "EoT Sync Error", 1183 "Escape Mode Entry Command Error", 1184 "Low-Power Transmit Sync Error", 1185 "Peripheral Timeout Error", 1186 "False Control Error", 1187 "Contention Detected", 1188 "ECC Error, single-bit", 1189 "ECC Error, multi-bit", 1190 "Checksum Error", 1191 "DSI Data Type Not Recognized", 1192 "DSI VC ID Invalid", 1193 "Invalid Transmission Length", 1194 "Reserved", 1195 "DSI Protocol Violation", 1196 }; 1197 1198 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi, 1199 const struct mipi_dsi_msg *msg, 1200 size_t count) 1201 { 1202 u8 *rx = msg->rx_buf; 1203 unsigned int i, j, k; 1204 size_t size = 0; 1205 u16 errors; 1206 u32 value; 1207 1208 /* read and parse packet header */ 1209 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1210 1211 switch (value & 0x3f) { 1212 case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT: 1213 errors = (value >> 8) & 0xffff; 1214 dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n", 1215 errors); 1216 for (i = 0; i < ARRAY_SIZE(error_report); i++) 1217 if (errors & BIT(i)) 1218 dev_dbg(dsi->dev, " %2u: %s\n", i, 1219 error_report[i]); 1220 break; 1221 1222 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE: 1223 rx[0] = (value >> 8) & 0xff; 1224 size = 1; 1225 break; 1226 1227 case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE: 1228 rx[0] = (value >> 8) & 0xff; 1229 rx[1] = (value >> 16) & 0xff; 1230 size = 2; 1231 break; 1232 1233 case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE: 1234 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1235 break; 1236 1237 case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE: 1238 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); 1239 break; 1240 1241 default: 1242 dev_err(dsi->dev, "unhandled response type: %02x\n", 1243 value & 0x3f); 1244 return -EPROTO; 1245 } 1246 1247 size = min(size, msg->rx_len); 1248 1249 if (msg->rx_buf && size > 0) { 1250 for (i = 0, j = 0; i < count - 1; i++, j += 4) { 1251 u8 *rx = msg->rx_buf + j; 1252 1253 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1254 1255 for (k = 0; k < 4 && (j + k) < msg->rx_len; k++) 1256 rx[j + k] = (value >> (k << 3)) & 0xff; 1257 } 1258 } 1259 1260 return size; 1261 } 1262 1263 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout) 1264 { 1265 tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER); 1266 1267 timeout = jiffies + msecs_to_jiffies(timeout); 1268 1269 while (time_before(jiffies, timeout)) { 1270 u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER); 1271 if ((value & DSI_TRIGGER_HOST) == 0) 1272 return 0; 1273 1274 usleep_range(1000, 2000); 1275 } 1276 1277 DRM_DEBUG_KMS("timeout waiting for transmission to complete\n"); 1278 return -ETIMEDOUT; 1279 } 1280 1281 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi, 1282 unsigned long timeout) 1283 { 1284 timeout = jiffies + msecs_to_jiffies(250); 1285 1286 while (time_before(jiffies, timeout)) { 1287 u32 value = tegra_dsi_readl(dsi, DSI_STATUS); 1288 u8 count = value & 0x1f; 1289 1290 if (count > 0) 1291 return count; 1292 1293 usleep_range(1000, 2000); 1294 } 1295 1296 DRM_DEBUG_KMS("peripheral returned no data\n"); 1297 return -ETIMEDOUT; 1298 } 1299 1300 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset, 1301 const void *buffer, size_t size) 1302 { 1303 const u8 *buf = buffer; 1304 size_t i, j; 1305 u32 value; 1306 1307 for (j = 0; j < size; j += 4) { 1308 value = 0; 1309 1310 for (i = 0; i < 4 && j + i < size; i++) 1311 value |= buf[j + i] << (i << 3); 1312 1313 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1314 } 1315 } 1316 1317 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host, 1318 const struct mipi_dsi_msg *msg) 1319 { 1320 struct tegra_dsi *dsi = host_to_tegra(host); 1321 struct mipi_dsi_packet packet; 1322 const u8 *header; 1323 size_t count; 1324 ssize_t err; 1325 u32 value; 1326 1327 err = mipi_dsi_create_packet(&packet, msg); 1328 if (err < 0) 1329 return err; 1330 1331 header = packet.header; 1332 1333 /* maximum FIFO depth is 1920 words */ 1334 if (packet.size > dsi->video_fifo_depth * 4) 1335 return -ENOSPC; 1336 1337 /* reset underflow/overflow flags */ 1338 value = tegra_dsi_readl(dsi, DSI_STATUS); 1339 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { 1340 value = DSI_HOST_CONTROL_FIFO_RESET; 1341 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1342 usleep_range(10, 20); 1343 } 1344 1345 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL); 1346 value |= DSI_POWER_CONTROL_ENABLE; 1347 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL); 1348 1349 usleep_range(5000, 10000); 1350 1351 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | 1352 DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC; 1353 1354 if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0) 1355 value |= DSI_HOST_CONTROL_HS; 1356 1357 /* 1358 * The host FIFO has a maximum of 64 words, so larger transmissions 1359 * need to use the video FIFO. 1360 */ 1361 if (packet.size > dsi->host_fifo_depth * 4) 1362 value |= DSI_HOST_CONTROL_FIFO_SEL; 1363 1364 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1365 1366 /* 1367 * For reads and messages with explicitly requested ACK, generate a 1368 * BTA sequence after the transmission of the packet. 1369 */ 1370 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1371 (msg->rx_buf && msg->rx_len > 0)) { 1372 value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL); 1373 value |= DSI_HOST_CONTROL_PKT_BTA; 1374 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL); 1375 } 1376 1377 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; 1378 tegra_dsi_writel(dsi, value, DSI_CONTROL); 1379 1380 /* write packet header, ECC is generated by hardware */ 1381 value = header[2] << 16 | header[1] << 8 | header[0]; 1382 tegra_dsi_writel(dsi, value, DSI_WR_DATA); 1383 1384 /* write payload (if any) */ 1385 if (packet.payload_length > 0) 1386 tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload, 1387 packet.payload_length); 1388 1389 err = tegra_dsi_transmit(dsi, 250); 1390 if (err < 0) 1391 return err; 1392 1393 if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) || 1394 (msg->rx_buf && msg->rx_len > 0)) { 1395 err = tegra_dsi_wait_for_response(dsi, 250); 1396 if (err < 0) 1397 return err; 1398 1399 count = err; 1400 1401 value = tegra_dsi_readl(dsi, DSI_RD_DATA); 1402 switch (value) { 1403 case 0x84: 1404 /* 1405 dev_dbg(dsi->dev, "ACK\n"); 1406 */ 1407 break; 1408 1409 case 0x87: 1410 /* 1411 dev_dbg(dsi->dev, "ESCAPE\n"); 1412 */ 1413 break; 1414 1415 default: 1416 dev_err(dsi->dev, "unknown status: %08x\n", value); 1417 break; 1418 } 1419 1420 if (count > 1) { 1421 err = tegra_dsi_read_response(dsi, msg, count); 1422 if (err < 0) 1423 dev_err(dsi->dev, 1424 "failed to parse response: %zd\n", 1425 err); 1426 else { 1427 /* 1428 * For read commands, return the number of 1429 * bytes returned by the peripheral. 1430 */ 1431 count = err; 1432 } 1433 } 1434 } else { 1435 /* 1436 * For write commands, we have transmitted the 4-byte header 1437 * plus the variable-length payload. 1438 */ 1439 count = 4 + packet.payload_length; 1440 } 1441 1442 return count; 1443 } 1444 1445 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi) 1446 { 1447 struct clk *parent; 1448 int err; 1449 1450 /* make sure both DSI controllers share the same PLL */ 1451 parent = clk_get_parent(dsi->slave->clk); 1452 if (!parent) 1453 return -EINVAL; 1454 1455 err = clk_set_parent(parent, dsi->clk_parent); 1456 if (err < 0) 1457 return err; 1458 1459 return 0; 1460 } 1461 1462 static int tegra_dsi_host_attach(struct mipi_dsi_host *host, 1463 struct mipi_dsi_device *device) 1464 { 1465 struct tegra_dsi *dsi = host_to_tegra(host); 1466 1467 dsi->flags = device->mode_flags; 1468 dsi->format = device->format; 1469 dsi->lanes = device->lanes; 1470 1471 if (dsi->slave) { 1472 int err; 1473 1474 dev_dbg(dsi->dev, "attaching dual-channel device %s\n", 1475 dev_name(&device->dev)); 1476 1477 err = tegra_dsi_ganged_setup(dsi); 1478 if (err < 0) { 1479 dev_err(dsi->dev, "failed to set up ganged mode: %d\n", 1480 err); 1481 return err; 1482 } 1483 } 1484 1485 /* 1486 * Slaves don't have a panel associated with them, so they provide 1487 * merely the second channel. 1488 */ 1489 if (!dsi->master) { 1490 struct tegra_output *output = &dsi->output; 1491 1492 output->panel = of_drm_find_panel(device->dev.of_node); 1493 if (IS_ERR(output->panel)) 1494 output->panel = NULL; 1495 1496 if (output->panel && output->connector.dev) { 1497 drm_panel_attach(output->panel, &output->connector); 1498 drm_helper_hpd_irq_event(output->connector.dev); 1499 } 1500 } 1501 1502 return 0; 1503 } 1504 1505 static int tegra_dsi_host_detach(struct mipi_dsi_host *host, 1506 struct mipi_dsi_device *device) 1507 { 1508 struct tegra_dsi *dsi = host_to_tegra(host); 1509 struct tegra_output *output = &dsi->output; 1510 1511 if (output->panel && &device->dev == output->panel->dev) { 1512 output->panel = NULL; 1513 1514 if (output->connector.dev) 1515 drm_helper_hpd_irq_event(output->connector.dev); 1516 } 1517 1518 return 0; 1519 } 1520 1521 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = { 1522 .attach = tegra_dsi_host_attach, 1523 .detach = tegra_dsi_host_detach, 1524 .transfer = tegra_dsi_host_transfer, 1525 }; 1526 1527 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi) 1528 { 1529 struct device_node *np; 1530 1531 np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0); 1532 if (np) { 1533 struct platform_device *gangster = of_find_device_by_node(np); 1534 1535 dsi->slave = platform_get_drvdata(gangster); 1536 of_node_put(np); 1537 1538 if (!dsi->slave) 1539 return -EPROBE_DEFER; 1540 1541 dsi->slave->master = dsi; 1542 } 1543 1544 return 0; 1545 } 1546 1547 static int tegra_dsi_probe(struct platform_device *pdev) 1548 { 1549 struct tegra_dsi *dsi; 1550 struct resource *regs; 1551 int err; 1552 1553 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL); 1554 if (!dsi) 1555 return -ENOMEM; 1556 1557 dsi->output.dev = dsi->dev = &pdev->dev; 1558 dsi->video_fifo_depth = 1920; 1559 dsi->host_fifo_depth = 64; 1560 1561 err = tegra_dsi_ganged_probe(dsi); 1562 if (err < 0) 1563 return err; 1564 1565 err = tegra_output_probe(&dsi->output); 1566 if (err < 0) 1567 return err; 1568 1569 dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD; 1570 1571 /* 1572 * Assume these values by default. When a DSI peripheral driver 1573 * attaches to the DSI host, the parameters will be taken from 1574 * the attached device. 1575 */ 1576 dsi->flags = MIPI_DSI_MODE_VIDEO; 1577 dsi->format = MIPI_DSI_FMT_RGB888; 1578 dsi->lanes = 4; 1579 1580 if (!pdev->dev.pm_domain) { 1581 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi"); 1582 if (IS_ERR(dsi->rst)) 1583 return PTR_ERR(dsi->rst); 1584 } 1585 1586 dsi->clk = devm_clk_get(&pdev->dev, NULL); 1587 if (IS_ERR(dsi->clk)) { 1588 dev_err(&pdev->dev, "cannot get DSI clock\n"); 1589 return PTR_ERR(dsi->clk); 1590 } 1591 1592 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp"); 1593 if (IS_ERR(dsi->clk_lp)) { 1594 dev_err(&pdev->dev, "cannot get low-power clock\n"); 1595 return PTR_ERR(dsi->clk_lp); 1596 } 1597 1598 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent"); 1599 if (IS_ERR(dsi->clk_parent)) { 1600 dev_err(&pdev->dev, "cannot get parent clock\n"); 1601 return PTR_ERR(dsi->clk_parent); 1602 } 1603 1604 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi"); 1605 if (IS_ERR(dsi->vdd)) { 1606 dev_err(&pdev->dev, "cannot get VDD supply\n"); 1607 return PTR_ERR(dsi->vdd); 1608 } 1609 1610 err = tegra_dsi_setup_clocks(dsi); 1611 if (err < 0) { 1612 dev_err(&pdev->dev, "cannot setup clocks\n"); 1613 return err; 1614 } 1615 1616 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1617 dsi->regs = devm_ioremap_resource(&pdev->dev, regs); 1618 if (IS_ERR(dsi->regs)) 1619 return PTR_ERR(dsi->regs); 1620 1621 dsi->mipi = tegra_mipi_request(&pdev->dev); 1622 if (IS_ERR(dsi->mipi)) 1623 return PTR_ERR(dsi->mipi); 1624 1625 dsi->host.ops = &tegra_dsi_host_ops; 1626 dsi->host.dev = &pdev->dev; 1627 1628 err = mipi_dsi_host_register(&dsi->host); 1629 if (err < 0) { 1630 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err); 1631 goto mipi_free; 1632 } 1633 1634 platform_set_drvdata(pdev, dsi); 1635 pm_runtime_enable(&pdev->dev); 1636 1637 INIT_LIST_HEAD(&dsi->client.list); 1638 dsi->client.ops = &dsi_client_ops; 1639 dsi->client.dev = &pdev->dev; 1640 1641 err = host1x_client_register(&dsi->client); 1642 if (err < 0) { 1643 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1644 err); 1645 goto unregister; 1646 } 1647 1648 return 0; 1649 1650 unregister: 1651 mipi_dsi_host_unregister(&dsi->host); 1652 mipi_free: 1653 tegra_mipi_free(dsi->mipi); 1654 return err; 1655 } 1656 1657 static int tegra_dsi_remove(struct platform_device *pdev) 1658 { 1659 struct tegra_dsi *dsi = platform_get_drvdata(pdev); 1660 int err; 1661 1662 pm_runtime_disable(&pdev->dev); 1663 1664 err = host1x_client_unregister(&dsi->client); 1665 if (err < 0) { 1666 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1667 err); 1668 return err; 1669 } 1670 1671 tegra_output_remove(&dsi->output); 1672 1673 mipi_dsi_host_unregister(&dsi->host); 1674 tegra_mipi_free(dsi->mipi); 1675 1676 return 0; 1677 } 1678 1679 static const struct of_device_id tegra_dsi_of_match[] = { 1680 { .compatible = "nvidia,tegra210-dsi", }, 1681 { .compatible = "nvidia,tegra132-dsi", }, 1682 { .compatible = "nvidia,tegra124-dsi", }, 1683 { .compatible = "nvidia,tegra114-dsi", }, 1684 { }, 1685 }; 1686 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match); 1687 1688 struct platform_driver tegra_dsi_driver = { 1689 .driver = { 1690 .name = "tegra-dsi", 1691 .of_match_table = tegra_dsi_of_match, 1692 }, 1693 .probe = tegra_dsi_probe, 1694 .remove = tegra_dsi_remove, 1695 }; 1696