1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012-2013 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef HOST1X_DRM_H 11 #define HOST1X_DRM_H 1 12 13 #include <uapi/drm/tegra_drm.h> 14 #include <linux/host1x.h> 15 16 #include <drm/drmP.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <drm/drm_edid.h> 19 #include <drm/drm_fb_helper.h> 20 #include <drm/drm_fixed.h> 21 22 struct reset_control; 23 24 struct tegra_fb { 25 struct drm_framebuffer base; 26 struct tegra_bo **planes; 27 unsigned int num_planes; 28 }; 29 30 #ifdef CONFIG_DRM_TEGRA_FBDEV 31 struct tegra_fbdev { 32 struct drm_fb_helper base; 33 struct tegra_fb *fb; 34 }; 35 #endif 36 37 struct tegra_drm { 38 struct drm_device *drm; 39 40 struct mutex clients_lock; 41 struct list_head clients; 42 43 #ifdef CONFIG_DRM_TEGRA_FBDEV 44 struct tegra_fbdev *fbdev; 45 #endif 46 }; 47 48 struct tegra_drm_client; 49 50 struct tegra_drm_context { 51 struct tegra_drm_client *client; 52 struct host1x_channel *channel; 53 struct list_head list; 54 }; 55 56 struct tegra_drm_client_ops { 57 int (*open_channel)(struct tegra_drm_client *client, 58 struct tegra_drm_context *context); 59 void (*close_channel)(struct tegra_drm_context *context); 60 int (*is_addr_reg)(struct device *dev, u32 class, u32 offset); 61 int (*submit)(struct tegra_drm_context *context, 62 struct drm_tegra_submit *args, struct drm_device *drm, 63 struct drm_file *file); 64 }; 65 66 int tegra_drm_submit(struct tegra_drm_context *context, 67 struct drm_tegra_submit *args, struct drm_device *drm, 68 struct drm_file *file); 69 70 struct tegra_drm_client { 71 struct host1x_client base; 72 struct list_head list; 73 74 const struct tegra_drm_client_ops *ops; 75 }; 76 77 static inline struct tegra_drm_client * 78 host1x_to_drm_client(struct host1x_client *client) 79 { 80 return container_of(client, struct tegra_drm_client, base); 81 } 82 83 extern int tegra_drm_register_client(struct tegra_drm *tegra, 84 struct tegra_drm_client *client); 85 extern int tegra_drm_unregister_client(struct tegra_drm *tegra, 86 struct tegra_drm_client *client); 87 88 extern int tegra_drm_init(struct tegra_drm *tegra, struct drm_device *drm); 89 extern int tegra_drm_exit(struct tegra_drm *tegra); 90 91 struct tegra_dc_soc_info; 92 struct tegra_output; 93 94 struct tegra_dc { 95 struct host1x_client client; 96 struct device *dev; 97 spinlock_t lock; 98 99 struct drm_crtc base; 100 int pipe; 101 102 struct clk *clk; 103 struct reset_control *rst; 104 void __iomem *regs; 105 int irq; 106 107 struct tegra_output *rgb; 108 109 struct list_head list; 110 111 struct drm_info_list *debugfs_files; 112 struct drm_minor *minor; 113 struct dentry *debugfs; 114 115 /* page-flip handling */ 116 struct drm_pending_vblank_event *event; 117 118 const struct tegra_dc_soc_info *soc; 119 }; 120 121 static inline struct tegra_dc * 122 host1x_client_to_dc(struct host1x_client *client) 123 { 124 return container_of(client, struct tegra_dc, client); 125 } 126 127 static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) 128 { 129 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; 130 } 131 132 static inline void tegra_dc_writel(struct tegra_dc *dc, unsigned long value, 133 unsigned long reg) 134 { 135 writel(value, dc->regs + (reg << 2)); 136 } 137 138 static inline unsigned long tegra_dc_readl(struct tegra_dc *dc, 139 unsigned long reg) 140 { 141 return readl(dc->regs + (reg << 2)); 142 } 143 144 struct tegra_dc_window { 145 struct { 146 unsigned int x; 147 unsigned int y; 148 unsigned int w; 149 unsigned int h; 150 } src; 151 struct { 152 unsigned int x; 153 unsigned int y; 154 unsigned int w; 155 unsigned int h; 156 } dst; 157 unsigned int bits_per_pixel; 158 unsigned int format; 159 unsigned int stride[2]; 160 unsigned long base[3]; 161 bool bottom_up; 162 bool tiled; 163 }; 164 165 /* from dc.c */ 166 extern unsigned int tegra_dc_format(uint32_t format); 167 extern int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, 168 const struct tegra_dc_window *window); 169 extern void tegra_dc_enable_vblank(struct tegra_dc *dc); 170 extern void tegra_dc_disable_vblank(struct tegra_dc *dc); 171 extern void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, 172 struct drm_file *file); 173 174 struct tegra_output_ops { 175 int (*enable)(struct tegra_output *output); 176 int (*disable)(struct tegra_output *output); 177 int (*setup_clock)(struct tegra_output *output, struct clk *clk, 178 unsigned long pclk); 179 int (*check_mode)(struct tegra_output *output, 180 struct drm_display_mode *mode, 181 enum drm_mode_status *status); 182 }; 183 184 enum tegra_output_type { 185 TEGRA_OUTPUT_RGB, 186 TEGRA_OUTPUT_HDMI, 187 TEGRA_OUTPUT_DSI, 188 }; 189 190 struct tegra_output { 191 struct device_node *of_node; 192 struct device *dev; 193 194 const struct tegra_output_ops *ops; 195 enum tegra_output_type type; 196 197 struct drm_panel *panel; 198 struct i2c_adapter *ddc; 199 const struct edid *edid; 200 unsigned int hpd_irq; 201 int hpd_gpio; 202 203 struct drm_encoder encoder; 204 struct drm_connector connector; 205 }; 206 207 static inline struct tegra_output *encoder_to_output(struct drm_encoder *e) 208 { 209 return container_of(e, struct tegra_output, encoder); 210 } 211 212 static inline struct tegra_output *connector_to_output(struct drm_connector *c) 213 { 214 return container_of(c, struct tegra_output, connector); 215 } 216 217 static inline int tegra_output_enable(struct tegra_output *output) 218 { 219 if (output && output->ops && output->ops->enable) 220 return output->ops->enable(output); 221 222 return output ? -ENOSYS : -EINVAL; 223 } 224 225 static inline int tegra_output_disable(struct tegra_output *output) 226 { 227 if (output && output->ops && output->ops->disable) 228 return output->ops->disable(output); 229 230 return output ? -ENOSYS : -EINVAL; 231 } 232 233 static inline int tegra_output_setup_clock(struct tegra_output *output, 234 struct clk *clk, unsigned long pclk) 235 { 236 if (output && output->ops && output->ops->setup_clock) 237 return output->ops->setup_clock(output, clk, pclk); 238 239 return output ? -ENOSYS : -EINVAL; 240 } 241 242 static inline int tegra_output_check_mode(struct tegra_output *output, 243 struct drm_display_mode *mode, 244 enum drm_mode_status *status) 245 { 246 if (output && output->ops && output->ops->check_mode) 247 return output->ops->check_mode(output, mode, status); 248 249 return output ? -ENOSYS : -EINVAL; 250 } 251 252 /* from bus.c */ 253 int drm_host1x_init(struct drm_driver *driver, struct host1x_device *device); 254 void drm_host1x_exit(struct drm_driver *driver, struct host1x_device *device); 255 256 /* from rgb.c */ 257 extern int tegra_dc_rgb_probe(struct tegra_dc *dc); 258 extern int tegra_dc_rgb_remove(struct tegra_dc *dc); 259 extern int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); 260 extern int tegra_dc_rgb_exit(struct tegra_dc *dc); 261 262 /* from output.c */ 263 extern int tegra_output_probe(struct tegra_output *output); 264 extern int tegra_output_remove(struct tegra_output *output); 265 extern int tegra_output_init(struct drm_device *drm, struct tegra_output *output); 266 extern int tegra_output_exit(struct tegra_output *output); 267 268 /* from fb.c */ 269 struct tegra_bo *tegra_fb_get_plane(struct drm_framebuffer *framebuffer, 270 unsigned int index); 271 bool tegra_fb_is_bottom_up(struct drm_framebuffer *framebuffer); 272 bool tegra_fb_is_tiled(struct drm_framebuffer *framebuffer); 273 extern int tegra_drm_fb_init(struct drm_device *drm); 274 extern void tegra_drm_fb_exit(struct drm_device *drm); 275 #ifdef CONFIG_DRM_TEGRA_FBDEV 276 extern void tegra_fbdev_restore_mode(struct tegra_fbdev *fbdev); 277 #endif 278 279 extern struct platform_driver tegra_dc_driver; 280 extern struct platform_driver tegra_dsi_driver; 281 extern struct platform_driver tegra_hdmi_driver; 282 extern struct platform_driver tegra_gr2d_driver; 283 extern struct platform_driver tegra_gr3d_driver; 284 285 #endif /* HOST1X_DRM_H */ 286