1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012-2016 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/bitops.h> 8 #include <linux/host1x.h> 9 #include <linux/idr.h> 10 #include <linux/iommu.h> 11 #include <linux/module.h> 12 #include <linux/platform_device.h> 13 #include <linux/pm_runtime.h> 14 15 #include <drm/drm_aperture.h> 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_debugfs.h> 19 #include <drm/drm_drv.h> 20 #include <drm/drm_fourcc.h> 21 #include <drm/drm_framebuffer.h> 22 #include <drm/drm_ioctl.h> 23 #include <drm/drm_prime.h> 24 #include <drm/drm_vblank.h> 25 26 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 27 #include <asm/dma-iommu.h> 28 #endif 29 30 #include "dc.h" 31 #include "drm.h" 32 #include "gem.h" 33 #include "uapi.h" 34 35 #define DRIVER_NAME "tegra" 36 #define DRIVER_DESC "NVIDIA Tegra graphics" 37 #define DRIVER_DATE "20120330" 38 #define DRIVER_MAJOR 1 39 #define DRIVER_MINOR 0 40 #define DRIVER_PATCHLEVEL 0 41 42 #define CARVEOUT_SZ SZ_64M 43 #define CDMA_GATHER_FETCHES_MAX_NB 16383 44 45 static int tegra_atomic_check(struct drm_device *drm, 46 struct drm_atomic_state *state) 47 { 48 int err; 49 50 err = drm_atomic_helper_check(drm, state); 51 if (err < 0) 52 return err; 53 54 return tegra_display_hub_atomic_check(drm, state); 55 } 56 57 static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = { 58 .fb_create = tegra_fb_create, 59 .atomic_check = tegra_atomic_check, 60 .atomic_commit = drm_atomic_helper_commit, 61 }; 62 63 static void tegra_atomic_post_commit(struct drm_device *drm, 64 struct drm_atomic_state *old_state) 65 { 66 struct drm_crtc_state *old_crtc_state __maybe_unused; 67 struct drm_crtc *crtc; 68 unsigned int i; 69 70 for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i) 71 tegra_crtc_atomic_post_commit(crtc, old_state); 72 } 73 74 static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state) 75 { 76 struct drm_device *drm = old_state->dev; 77 struct tegra_drm *tegra = drm->dev_private; 78 79 if (tegra->hub) { 80 bool fence_cookie = dma_fence_begin_signalling(); 81 82 drm_atomic_helper_commit_modeset_disables(drm, old_state); 83 tegra_display_hub_atomic_commit(drm, old_state); 84 drm_atomic_helper_commit_planes(drm, old_state, 0); 85 drm_atomic_helper_commit_modeset_enables(drm, old_state); 86 drm_atomic_helper_commit_hw_done(old_state); 87 dma_fence_end_signalling(fence_cookie); 88 drm_atomic_helper_wait_for_vblanks(drm, old_state); 89 drm_atomic_helper_cleanup_planes(drm, old_state); 90 } else { 91 drm_atomic_helper_commit_tail_rpm(old_state); 92 } 93 94 tegra_atomic_post_commit(drm, old_state); 95 } 96 97 static const struct drm_mode_config_helper_funcs 98 tegra_drm_mode_config_helpers = { 99 .atomic_commit_tail = tegra_atomic_commit_tail, 100 }; 101 102 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp) 103 { 104 struct tegra_drm_file *fpriv; 105 106 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL); 107 if (!fpriv) 108 return -ENOMEM; 109 110 idr_init_base(&fpriv->legacy_contexts, 1); 111 xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1); 112 xa_init(&fpriv->syncpoints); 113 mutex_init(&fpriv->lock); 114 filp->driver_priv = fpriv; 115 116 return 0; 117 } 118 119 static void tegra_drm_context_free(struct tegra_drm_context *context) 120 { 121 context->client->ops->close_channel(context); 122 pm_runtime_put(context->client->base.dev); 123 kfree(context); 124 } 125 126 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest, 127 struct drm_tegra_reloc __user *src, 128 struct drm_device *drm, 129 struct drm_file *file) 130 { 131 u32 cmdbuf, target; 132 int err; 133 134 err = get_user(cmdbuf, &src->cmdbuf.handle); 135 if (err < 0) 136 return err; 137 138 err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset); 139 if (err < 0) 140 return err; 141 142 err = get_user(target, &src->target.handle); 143 if (err < 0) 144 return err; 145 146 err = get_user(dest->target.offset, &src->target.offset); 147 if (err < 0) 148 return err; 149 150 err = get_user(dest->shift, &src->shift); 151 if (err < 0) 152 return err; 153 154 dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE; 155 156 dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf); 157 if (!dest->cmdbuf.bo) 158 return -ENOENT; 159 160 dest->target.bo = tegra_gem_lookup(file, target); 161 if (!dest->target.bo) 162 return -ENOENT; 163 164 return 0; 165 } 166 167 int tegra_drm_submit(struct tegra_drm_context *context, 168 struct drm_tegra_submit *args, struct drm_device *drm, 169 struct drm_file *file) 170 { 171 struct host1x_client *client = &context->client->base; 172 unsigned int num_cmdbufs = args->num_cmdbufs; 173 unsigned int num_relocs = args->num_relocs; 174 struct drm_tegra_cmdbuf __user *user_cmdbufs; 175 struct drm_tegra_reloc __user *user_relocs; 176 struct drm_tegra_syncpt __user *user_syncpt; 177 struct drm_tegra_syncpt syncpt; 178 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 179 struct drm_gem_object **refs; 180 struct host1x_syncpt *sp = NULL; 181 struct host1x_job *job; 182 unsigned int num_refs; 183 int err; 184 185 user_cmdbufs = u64_to_user_ptr(args->cmdbufs); 186 user_relocs = u64_to_user_ptr(args->relocs); 187 user_syncpt = u64_to_user_ptr(args->syncpts); 188 189 /* We don't yet support other than one syncpt_incr struct per submit */ 190 if (args->num_syncpts != 1) 191 return -EINVAL; 192 193 /* We don't yet support waitchks */ 194 if (args->num_waitchks != 0) 195 return -EINVAL; 196 197 job = host1x_job_alloc(context->channel, args->num_cmdbufs, 198 args->num_relocs, false); 199 if (!job) 200 return -ENOMEM; 201 202 job->num_relocs = args->num_relocs; 203 job->client = client; 204 job->class = client->class; 205 job->serialize = true; 206 job->syncpt_recovery = true; 207 208 /* 209 * Track referenced BOs so that they can be unreferenced after the 210 * submission is complete. 211 */ 212 num_refs = num_cmdbufs + num_relocs * 2; 213 214 refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL); 215 if (!refs) { 216 err = -ENOMEM; 217 goto put; 218 } 219 220 /* reuse as an iterator later */ 221 num_refs = 0; 222 223 while (num_cmdbufs) { 224 struct drm_tegra_cmdbuf cmdbuf; 225 struct host1x_bo *bo; 226 struct tegra_bo *obj; 227 u64 offset; 228 229 if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) { 230 err = -EFAULT; 231 goto fail; 232 } 233 234 /* 235 * The maximum number of CDMA gather fetches is 16383, a higher 236 * value means the words count is malformed. 237 */ 238 if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) { 239 err = -EINVAL; 240 goto fail; 241 } 242 243 bo = tegra_gem_lookup(file, cmdbuf.handle); 244 if (!bo) { 245 err = -ENOENT; 246 goto fail; 247 } 248 249 offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32); 250 obj = host1x_to_tegra_bo(bo); 251 refs[num_refs++] = &obj->gem; 252 253 /* 254 * Gather buffer base address must be 4-bytes aligned, 255 * unaligned offset is malformed and cause commands stream 256 * corruption on the buffer address relocation. 257 */ 258 if (offset & 3 || offset > obj->gem.size) { 259 err = -EINVAL; 260 goto fail; 261 } 262 263 host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset); 264 num_cmdbufs--; 265 user_cmdbufs++; 266 } 267 268 /* copy and resolve relocations from submit */ 269 while (num_relocs--) { 270 struct host1x_reloc *reloc; 271 struct tegra_bo *obj; 272 273 err = host1x_reloc_copy_from_user(&job->relocs[num_relocs], 274 &user_relocs[num_relocs], drm, 275 file); 276 if (err < 0) 277 goto fail; 278 279 reloc = &job->relocs[num_relocs]; 280 obj = host1x_to_tegra_bo(reloc->cmdbuf.bo); 281 refs[num_refs++] = &obj->gem; 282 283 /* 284 * The unaligned cmdbuf offset will cause an unaligned write 285 * during of the relocations patching, corrupting the commands 286 * stream. 287 */ 288 if (reloc->cmdbuf.offset & 3 || 289 reloc->cmdbuf.offset >= obj->gem.size) { 290 err = -EINVAL; 291 goto fail; 292 } 293 294 obj = host1x_to_tegra_bo(reloc->target.bo); 295 refs[num_refs++] = &obj->gem; 296 297 if (reloc->target.offset >= obj->gem.size) { 298 err = -EINVAL; 299 goto fail; 300 } 301 } 302 303 if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) { 304 err = -EFAULT; 305 goto fail; 306 } 307 308 /* Syncpoint ref will be dropped on job release. */ 309 sp = host1x_syncpt_get_by_id(host1x, syncpt.id); 310 if (!sp) { 311 err = -ENOENT; 312 goto fail; 313 } 314 315 job->is_addr_reg = context->client->ops->is_addr_reg; 316 job->is_valid_class = context->client->ops->is_valid_class; 317 job->syncpt_incrs = syncpt.incrs; 318 job->syncpt = sp; 319 job->timeout = 10000; 320 321 if (args->timeout && args->timeout < 10000) 322 job->timeout = args->timeout; 323 324 err = host1x_job_pin(job, context->client->base.dev); 325 if (err) 326 goto fail; 327 328 err = host1x_job_submit(job); 329 if (err) { 330 host1x_job_unpin(job); 331 goto fail; 332 } 333 334 args->fence = job->syncpt_end; 335 336 fail: 337 while (num_refs--) 338 drm_gem_object_put(refs[num_refs]); 339 340 kfree(refs); 341 342 put: 343 host1x_job_put(job); 344 return err; 345 } 346 347 348 #ifdef CONFIG_DRM_TEGRA_STAGING 349 static int tegra_gem_create(struct drm_device *drm, void *data, 350 struct drm_file *file) 351 { 352 struct drm_tegra_gem_create *args = data; 353 struct tegra_bo *bo; 354 355 bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags, 356 &args->handle); 357 if (IS_ERR(bo)) 358 return PTR_ERR(bo); 359 360 return 0; 361 } 362 363 static int tegra_gem_mmap(struct drm_device *drm, void *data, 364 struct drm_file *file) 365 { 366 struct drm_tegra_gem_mmap *args = data; 367 struct drm_gem_object *gem; 368 struct tegra_bo *bo; 369 370 gem = drm_gem_object_lookup(file, args->handle); 371 if (!gem) 372 return -EINVAL; 373 374 bo = to_tegra_bo(gem); 375 376 args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node); 377 378 drm_gem_object_put(gem); 379 380 return 0; 381 } 382 383 static int tegra_syncpt_read(struct drm_device *drm, void *data, 384 struct drm_file *file) 385 { 386 struct host1x *host = dev_get_drvdata(drm->dev->parent); 387 struct drm_tegra_syncpt_read *args = data; 388 struct host1x_syncpt *sp; 389 390 sp = host1x_syncpt_get_by_id_noref(host, args->id); 391 if (!sp) 392 return -EINVAL; 393 394 args->value = host1x_syncpt_read_min(sp); 395 return 0; 396 } 397 398 static int tegra_syncpt_incr(struct drm_device *drm, void *data, 399 struct drm_file *file) 400 { 401 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 402 struct drm_tegra_syncpt_incr *args = data; 403 struct host1x_syncpt *sp; 404 405 sp = host1x_syncpt_get_by_id_noref(host1x, args->id); 406 if (!sp) 407 return -EINVAL; 408 409 return host1x_syncpt_incr(sp); 410 } 411 412 static int tegra_syncpt_wait(struct drm_device *drm, void *data, 413 struct drm_file *file) 414 { 415 struct host1x *host1x = dev_get_drvdata(drm->dev->parent); 416 struct drm_tegra_syncpt_wait *args = data; 417 struct host1x_syncpt *sp; 418 419 sp = host1x_syncpt_get_by_id_noref(host1x, args->id); 420 if (!sp) 421 return -EINVAL; 422 423 return host1x_syncpt_wait(sp, args->thresh, 424 msecs_to_jiffies(args->timeout), 425 &args->value); 426 } 427 428 static int tegra_client_open(struct tegra_drm_file *fpriv, 429 struct tegra_drm_client *client, 430 struct tegra_drm_context *context) 431 { 432 int err; 433 434 err = pm_runtime_resume_and_get(client->base.dev); 435 if (err) 436 return err; 437 438 err = client->ops->open_channel(client, context); 439 if (err < 0) { 440 pm_runtime_put(client->base.dev); 441 return err; 442 } 443 444 err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL); 445 if (err < 0) { 446 client->ops->close_channel(context); 447 pm_runtime_put(client->base.dev); 448 return err; 449 } 450 451 context->client = client; 452 context->id = err; 453 454 return 0; 455 } 456 457 static int tegra_open_channel(struct drm_device *drm, void *data, 458 struct drm_file *file) 459 { 460 struct tegra_drm_file *fpriv = file->driver_priv; 461 struct tegra_drm *tegra = drm->dev_private; 462 struct drm_tegra_open_channel *args = data; 463 struct tegra_drm_context *context; 464 struct tegra_drm_client *client; 465 int err = -ENODEV; 466 467 context = kzalloc(sizeof(*context), GFP_KERNEL); 468 if (!context) 469 return -ENOMEM; 470 471 mutex_lock(&fpriv->lock); 472 473 list_for_each_entry(client, &tegra->clients, list) 474 if (client->base.class == args->client) { 475 err = tegra_client_open(fpriv, client, context); 476 if (err < 0) 477 break; 478 479 args->context = context->id; 480 break; 481 } 482 483 if (err < 0) 484 kfree(context); 485 486 mutex_unlock(&fpriv->lock); 487 return err; 488 } 489 490 static int tegra_close_channel(struct drm_device *drm, void *data, 491 struct drm_file *file) 492 { 493 struct tegra_drm_file *fpriv = file->driver_priv; 494 struct drm_tegra_close_channel *args = data; 495 struct tegra_drm_context *context; 496 int err = 0; 497 498 mutex_lock(&fpriv->lock); 499 500 context = idr_find(&fpriv->legacy_contexts, args->context); 501 if (!context) { 502 err = -EINVAL; 503 goto unlock; 504 } 505 506 idr_remove(&fpriv->legacy_contexts, context->id); 507 tegra_drm_context_free(context); 508 509 unlock: 510 mutex_unlock(&fpriv->lock); 511 return err; 512 } 513 514 static int tegra_get_syncpt(struct drm_device *drm, void *data, 515 struct drm_file *file) 516 { 517 struct tegra_drm_file *fpriv = file->driver_priv; 518 struct drm_tegra_get_syncpt *args = data; 519 struct tegra_drm_context *context; 520 struct host1x_syncpt *syncpt; 521 int err = 0; 522 523 mutex_lock(&fpriv->lock); 524 525 context = idr_find(&fpriv->legacy_contexts, args->context); 526 if (!context) { 527 err = -ENODEV; 528 goto unlock; 529 } 530 531 if (args->index >= context->client->base.num_syncpts) { 532 err = -EINVAL; 533 goto unlock; 534 } 535 536 syncpt = context->client->base.syncpts[args->index]; 537 args->id = host1x_syncpt_id(syncpt); 538 539 unlock: 540 mutex_unlock(&fpriv->lock); 541 return err; 542 } 543 544 static int tegra_submit(struct drm_device *drm, void *data, 545 struct drm_file *file) 546 { 547 struct tegra_drm_file *fpriv = file->driver_priv; 548 struct drm_tegra_submit *args = data; 549 struct tegra_drm_context *context; 550 int err; 551 552 mutex_lock(&fpriv->lock); 553 554 context = idr_find(&fpriv->legacy_contexts, args->context); 555 if (!context) { 556 err = -ENODEV; 557 goto unlock; 558 } 559 560 err = context->client->ops->submit(context, args, drm, file); 561 562 unlock: 563 mutex_unlock(&fpriv->lock); 564 return err; 565 } 566 567 static int tegra_get_syncpt_base(struct drm_device *drm, void *data, 568 struct drm_file *file) 569 { 570 struct tegra_drm_file *fpriv = file->driver_priv; 571 struct drm_tegra_get_syncpt_base *args = data; 572 struct tegra_drm_context *context; 573 struct host1x_syncpt_base *base; 574 struct host1x_syncpt *syncpt; 575 int err = 0; 576 577 mutex_lock(&fpriv->lock); 578 579 context = idr_find(&fpriv->legacy_contexts, args->context); 580 if (!context) { 581 err = -ENODEV; 582 goto unlock; 583 } 584 585 if (args->syncpt >= context->client->base.num_syncpts) { 586 err = -EINVAL; 587 goto unlock; 588 } 589 590 syncpt = context->client->base.syncpts[args->syncpt]; 591 592 base = host1x_syncpt_get_base(syncpt); 593 if (!base) { 594 err = -ENXIO; 595 goto unlock; 596 } 597 598 args->id = host1x_syncpt_base_id(base); 599 600 unlock: 601 mutex_unlock(&fpriv->lock); 602 return err; 603 } 604 605 static int tegra_gem_set_tiling(struct drm_device *drm, void *data, 606 struct drm_file *file) 607 { 608 struct drm_tegra_gem_set_tiling *args = data; 609 enum tegra_bo_tiling_mode mode; 610 struct drm_gem_object *gem; 611 unsigned long value = 0; 612 struct tegra_bo *bo; 613 614 switch (args->mode) { 615 case DRM_TEGRA_GEM_TILING_MODE_PITCH: 616 mode = TEGRA_BO_TILING_MODE_PITCH; 617 618 if (args->value != 0) 619 return -EINVAL; 620 621 break; 622 623 case DRM_TEGRA_GEM_TILING_MODE_TILED: 624 mode = TEGRA_BO_TILING_MODE_TILED; 625 626 if (args->value != 0) 627 return -EINVAL; 628 629 break; 630 631 case DRM_TEGRA_GEM_TILING_MODE_BLOCK: 632 mode = TEGRA_BO_TILING_MODE_BLOCK; 633 634 if (args->value > 5) 635 return -EINVAL; 636 637 value = args->value; 638 break; 639 640 default: 641 return -EINVAL; 642 } 643 644 gem = drm_gem_object_lookup(file, args->handle); 645 if (!gem) 646 return -ENOENT; 647 648 bo = to_tegra_bo(gem); 649 650 bo->tiling.mode = mode; 651 bo->tiling.value = value; 652 653 drm_gem_object_put(gem); 654 655 return 0; 656 } 657 658 static int tegra_gem_get_tiling(struct drm_device *drm, void *data, 659 struct drm_file *file) 660 { 661 struct drm_tegra_gem_get_tiling *args = data; 662 struct drm_gem_object *gem; 663 struct tegra_bo *bo; 664 int err = 0; 665 666 gem = drm_gem_object_lookup(file, args->handle); 667 if (!gem) 668 return -ENOENT; 669 670 bo = to_tegra_bo(gem); 671 672 switch (bo->tiling.mode) { 673 case TEGRA_BO_TILING_MODE_PITCH: 674 args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH; 675 args->value = 0; 676 break; 677 678 case TEGRA_BO_TILING_MODE_TILED: 679 args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED; 680 args->value = 0; 681 break; 682 683 case TEGRA_BO_TILING_MODE_BLOCK: 684 args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK; 685 args->value = bo->tiling.value; 686 break; 687 688 default: 689 err = -EINVAL; 690 break; 691 } 692 693 drm_gem_object_put(gem); 694 695 return err; 696 } 697 698 static int tegra_gem_set_flags(struct drm_device *drm, void *data, 699 struct drm_file *file) 700 { 701 struct drm_tegra_gem_set_flags *args = data; 702 struct drm_gem_object *gem; 703 struct tegra_bo *bo; 704 705 if (args->flags & ~DRM_TEGRA_GEM_FLAGS) 706 return -EINVAL; 707 708 gem = drm_gem_object_lookup(file, args->handle); 709 if (!gem) 710 return -ENOENT; 711 712 bo = to_tegra_bo(gem); 713 bo->flags = 0; 714 715 if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP) 716 bo->flags |= TEGRA_BO_BOTTOM_UP; 717 718 drm_gem_object_put(gem); 719 720 return 0; 721 } 722 723 static int tegra_gem_get_flags(struct drm_device *drm, void *data, 724 struct drm_file *file) 725 { 726 struct drm_tegra_gem_get_flags *args = data; 727 struct drm_gem_object *gem; 728 struct tegra_bo *bo; 729 730 gem = drm_gem_object_lookup(file, args->handle); 731 if (!gem) 732 return -ENOENT; 733 734 bo = to_tegra_bo(gem); 735 args->flags = 0; 736 737 if (bo->flags & TEGRA_BO_BOTTOM_UP) 738 args->flags |= DRM_TEGRA_GEM_BOTTOM_UP; 739 740 drm_gem_object_put(gem); 741 742 return 0; 743 } 744 #endif 745 746 static const struct drm_ioctl_desc tegra_drm_ioctls[] = { 747 #ifdef CONFIG_DRM_TEGRA_STAGING 748 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open, 749 DRM_RENDER_ALLOW), 750 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close, 751 DRM_RENDER_ALLOW), 752 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map, 753 DRM_RENDER_ALLOW), 754 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap, 755 DRM_RENDER_ALLOW), 756 DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_SUBMIT, tegra_drm_ioctl_channel_submit, 757 DRM_RENDER_ALLOW), 758 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_ALLOCATE, tegra_drm_ioctl_syncpoint_allocate, 759 DRM_RENDER_ALLOW), 760 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_FREE, tegra_drm_ioctl_syncpoint_free, 761 DRM_RENDER_ALLOW), 762 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_WAIT, tegra_drm_ioctl_syncpoint_wait, 763 DRM_RENDER_ALLOW), 764 765 DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_RENDER_ALLOW), 766 DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_RENDER_ALLOW), 767 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read, 768 DRM_RENDER_ALLOW), 769 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr, 770 DRM_RENDER_ALLOW), 771 DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait, 772 DRM_RENDER_ALLOW), 773 DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel, 774 DRM_RENDER_ALLOW), 775 DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel, 776 DRM_RENDER_ALLOW), 777 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt, 778 DRM_RENDER_ALLOW), 779 DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit, 780 DRM_RENDER_ALLOW), 781 DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base, 782 DRM_RENDER_ALLOW), 783 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling, 784 DRM_RENDER_ALLOW), 785 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling, 786 DRM_RENDER_ALLOW), 787 DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags, 788 DRM_RENDER_ALLOW), 789 DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags, 790 DRM_RENDER_ALLOW), 791 #endif 792 }; 793 794 static const struct file_operations tegra_drm_fops = { 795 .owner = THIS_MODULE, 796 .open = drm_open, 797 .release = drm_release, 798 .unlocked_ioctl = drm_ioctl, 799 .mmap = tegra_drm_mmap, 800 .poll = drm_poll, 801 .read = drm_read, 802 .compat_ioctl = drm_compat_ioctl, 803 .llseek = noop_llseek, 804 }; 805 806 static int tegra_drm_context_cleanup(int id, void *p, void *data) 807 { 808 struct tegra_drm_context *context = p; 809 810 tegra_drm_context_free(context); 811 812 return 0; 813 } 814 815 static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file) 816 { 817 struct tegra_drm_file *fpriv = file->driver_priv; 818 819 mutex_lock(&fpriv->lock); 820 idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL); 821 tegra_drm_uapi_close_file(fpriv); 822 mutex_unlock(&fpriv->lock); 823 824 idr_destroy(&fpriv->legacy_contexts); 825 mutex_destroy(&fpriv->lock); 826 kfree(fpriv); 827 } 828 829 #ifdef CONFIG_DEBUG_FS 830 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data) 831 { 832 struct drm_info_node *node = (struct drm_info_node *)s->private; 833 struct drm_device *drm = node->minor->dev; 834 struct drm_framebuffer *fb; 835 836 mutex_lock(&drm->mode_config.fb_lock); 837 838 list_for_each_entry(fb, &drm->mode_config.fb_list, head) { 839 seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n", 840 fb->base.id, fb->width, fb->height, 841 fb->format->depth, 842 fb->format->cpp[0] * 8, 843 drm_framebuffer_read_refcount(fb)); 844 } 845 846 mutex_unlock(&drm->mode_config.fb_lock); 847 848 return 0; 849 } 850 851 static int tegra_debugfs_iova(struct seq_file *s, void *data) 852 { 853 struct drm_info_node *node = (struct drm_info_node *)s->private; 854 struct drm_device *drm = node->minor->dev; 855 struct tegra_drm *tegra = drm->dev_private; 856 struct drm_printer p = drm_seq_file_printer(s); 857 858 if (tegra->domain) { 859 mutex_lock(&tegra->mm_lock); 860 drm_mm_print(&tegra->mm, &p); 861 mutex_unlock(&tegra->mm_lock); 862 } 863 864 return 0; 865 } 866 867 static struct drm_info_list tegra_debugfs_list[] = { 868 { "framebuffers", tegra_debugfs_framebuffers, 0 }, 869 { "iova", tegra_debugfs_iova, 0 }, 870 }; 871 872 static void tegra_debugfs_init(struct drm_minor *minor) 873 { 874 drm_debugfs_create_files(tegra_debugfs_list, 875 ARRAY_SIZE(tegra_debugfs_list), 876 minor->debugfs_root, minor); 877 } 878 #endif 879 880 static const struct drm_driver tegra_drm_driver = { 881 .driver_features = DRIVER_MODESET | DRIVER_GEM | 882 DRIVER_ATOMIC | DRIVER_RENDER | DRIVER_SYNCOBJ, 883 .open = tegra_drm_open, 884 .postclose = tegra_drm_postclose, 885 886 #if defined(CONFIG_DEBUG_FS) 887 .debugfs_init = tegra_debugfs_init, 888 #endif 889 890 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 891 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 892 .gem_prime_import = tegra_gem_prime_import, 893 894 .dumb_create = tegra_bo_dumb_create, 895 896 .ioctls = tegra_drm_ioctls, 897 .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls), 898 .fops = &tegra_drm_fops, 899 900 .name = DRIVER_NAME, 901 .desc = DRIVER_DESC, 902 .date = DRIVER_DATE, 903 .major = DRIVER_MAJOR, 904 .minor = DRIVER_MINOR, 905 .patchlevel = DRIVER_PATCHLEVEL, 906 }; 907 908 int tegra_drm_register_client(struct tegra_drm *tegra, 909 struct tegra_drm_client *client) 910 { 911 /* 912 * When MLOCKs are implemented, change to allocate a shared channel 913 * only when MLOCKs are disabled. 914 */ 915 client->shared_channel = host1x_channel_request(&client->base); 916 if (!client->shared_channel) 917 return -EBUSY; 918 919 mutex_lock(&tegra->clients_lock); 920 list_add_tail(&client->list, &tegra->clients); 921 client->drm = tegra; 922 mutex_unlock(&tegra->clients_lock); 923 924 return 0; 925 } 926 927 int tegra_drm_unregister_client(struct tegra_drm *tegra, 928 struct tegra_drm_client *client) 929 { 930 mutex_lock(&tegra->clients_lock); 931 list_del_init(&client->list); 932 client->drm = NULL; 933 mutex_unlock(&tegra->clients_lock); 934 935 if (client->shared_channel) 936 host1x_channel_put(client->shared_channel); 937 938 return 0; 939 } 940 941 int host1x_client_iommu_attach(struct host1x_client *client) 942 { 943 struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev); 944 struct drm_device *drm = dev_get_drvdata(client->host); 945 struct tegra_drm *tegra = drm->dev_private; 946 struct iommu_group *group = NULL; 947 int err; 948 949 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU) 950 if (client->dev->archdata.mapping) { 951 struct dma_iommu_mapping *mapping = 952 to_dma_iommu_mapping(client->dev); 953 arm_iommu_detach_device(client->dev); 954 arm_iommu_release_mapping(mapping); 955 956 domain = iommu_get_domain_for_dev(client->dev); 957 } 958 #endif 959 960 /* 961 * If the host1x client is already attached to an IOMMU domain that is 962 * not the shared IOMMU domain, don't try to attach it to a different 963 * domain. This allows using the IOMMU-backed DMA API. 964 */ 965 if (domain && domain != tegra->domain) 966 return 0; 967 968 if (tegra->domain) { 969 group = iommu_group_get(client->dev); 970 if (!group) 971 return -ENODEV; 972 973 if (domain != tegra->domain) { 974 err = iommu_attach_group(tegra->domain, group); 975 if (err < 0) { 976 iommu_group_put(group); 977 return err; 978 } 979 } 980 981 tegra->use_explicit_iommu = true; 982 } 983 984 client->group = group; 985 986 return 0; 987 } 988 989 void host1x_client_iommu_detach(struct host1x_client *client) 990 { 991 struct drm_device *drm = dev_get_drvdata(client->host); 992 struct tegra_drm *tegra = drm->dev_private; 993 struct iommu_domain *domain; 994 995 if (client->group) { 996 /* 997 * Devices that are part of the same group may no longer be 998 * attached to a domain at this point because their group may 999 * have been detached by an earlier client. 1000 */ 1001 domain = iommu_get_domain_for_dev(client->dev); 1002 if (domain) 1003 iommu_detach_group(tegra->domain, client->group); 1004 1005 iommu_group_put(client->group); 1006 client->group = NULL; 1007 } 1008 } 1009 1010 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma) 1011 { 1012 struct iova *alloc; 1013 void *virt; 1014 gfp_t gfp; 1015 int err; 1016 1017 if (tegra->domain) 1018 size = iova_align(&tegra->carveout.domain, size); 1019 else 1020 size = PAGE_ALIGN(size); 1021 1022 gfp = GFP_KERNEL | __GFP_ZERO; 1023 if (!tegra->domain) { 1024 /* 1025 * Many units only support 32-bit addresses, even on 64-bit 1026 * SoCs. If there is no IOMMU to translate into a 32-bit IO 1027 * virtual address space, force allocations to be in the 1028 * lower 32-bit range. 1029 */ 1030 gfp |= GFP_DMA; 1031 } 1032 1033 virt = (void *)__get_free_pages(gfp, get_order(size)); 1034 if (!virt) 1035 return ERR_PTR(-ENOMEM); 1036 1037 if (!tegra->domain) { 1038 /* 1039 * If IOMMU is disabled, devices address physical memory 1040 * directly. 1041 */ 1042 *dma = virt_to_phys(virt); 1043 return virt; 1044 } 1045 1046 alloc = alloc_iova(&tegra->carveout.domain, 1047 size >> tegra->carveout.shift, 1048 tegra->carveout.limit, true); 1049 if (!alloc) { 1050 err = -EBUSY; 1051 goto free_pages; 1052 } 1053 1054 *dma = iova_dma_addr(&tegra->carveout.domain, alloc); 1055 err = iommu_map(tegra->domain, *dma, virt_to_phys(virt), 1056 size, IOMMU_READ | IOMMU_WRITE, GFP_KERNEL); 1057 if (err < 0) 1058 goto free_iova; 1059 1060 return virt; 1061 1062 free_iova: 1063 __free_iova(&tegra->carveout.domain, alloc); 1064 free_pages: 1065 free_pages((unsigned long)virt, get_order(size)); 1066 1067 return ERR_PTR(err); 1068 } 1069 1070 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt, 1071 dma_addr_t dma) 1072 { 1073 if (tegra->domain) 1074 size = iova_align(&tegra->carveout.domain, size); 1075 else 1076 size = PAGE_ALIGN(size); 1077 1078 if (tegra->domain) { 1079 iommu_unmap(tegra->domain, dma, size); 1080 free_iova(&tegra->carveout.domain, 1081 iova_pfn(&tegra->carveout.domain, dma)); 1082 } 1083 1084 free_pages((unsigned long)virt, get_order(size)); 1085 } 1086 1087 static bool host1x_drm_wants_iommu(struct host1x_device *dev) 1088 { 1089 struct host1x *host1x = dev_get_drvdata(dev->dev.parent); 1090 struct iommu_domain *domain; 1091 1092 /* Our IOMMU usage policy doesn't currently play well with GART */ 1093 if (of_machine_is_compatible("nvidia,tegra20")) 1094 return false; 1095 1096 /* 1097 * If the Tegra DRM clients are backed by an IOMMU, push buffers are 1098 * likely to be allocated beyond the 32-bit boundary if sufficient 1099 * system memory is available. This is problematic on earlier Tegra 1100 * generations where host1x supports a maximum of 32 address bits in 1101 * the GATHER opcode. In this case, unless host1x is behind an IOMMU 1102 * as well it won't be able to process buffers allocated beyond the 1103 * 32-bit boundary. 1104 * 1105 * The DMA API will use bounce buffers in this case, so that could 1106 * perhaps still be made to work, even if less efficient, but there 1107 * is another catch: in order to perform cache maintenance on pages 1108 * allocated for discontiguous buffers we need to map and unmap the 1109 * SG table representing these buffers. This is fine for something 1110 * small like a push buffer, but it exhausts the bounce buffer pool 1111 * (typically on the order of a few MiB) for framebuffers (many MiB 1112 * for any modern resolution). 1113 * 1114 * Work around this by making sure that Tegra DRM clients only use 1115 * an IOMMU if the parent host1x also uses an IOMMU. 1116 * 1117 * Note that there's still a small gap here that we don't cover: if 1118 * the DMA API is backed by an IOMMU there's no way to control which 1119 * device is attached to an IOMMU and which isn't, except via wiring 1120 * up the device tree appropriately. This is considered an problem 1121 * of integration, so care must be taken for the DT to be consistent. 1122 */ 1123 domain = iommu_get_domain_for_dev(dev->dev.parent); 1124 1125 /* 1126 * Tegra20 and Tegra30 don't support addressing memory beyond the 1127 * 32-bit boundary, so the regular GATHER opcodes will always be 1128 * sufficient and whether or not the host1x is attached to an IOMMU 1129 * doesn't matter. 1130 */ 1131 if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32)) 1132 return true; 1133 1134 return domain != NULL; 1135 } 1136 1137 static int host1x_drm_probe(struct host1x_device *dev) 1138 { 1139 struct tegra_drm *tegra; 1140 struct drm_device *drm; 1141 int err; 1142 1143 drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev); 1144 if (IS_ERR(drm)) 1145 return PTR_ERR(drm); 1146 1147 tegra = kzalloc(sizeof(*tegra), GFP_KERNEL); 1148 if (!tegra) { 1149 err = -ENOMEM; 1150 goto put; 1151 } 1152 1153 if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) { 1154 tegra->domain = iommu_domain_alloc(&platform_bus_type); 1155 if (!tegra->domain) { 1156 err = -ENOMEM; 1157 goto free; 1158 } 1159 1160 err = iova_cache_get(); 1161 if (err < 0) 1162 goto domain; 1163 } 1164 1165 mutex_init(&tegra->clients_lock); 1166 INIT_LIST_HEAD(&tegra->clients); 1167 1168 dev_set_drvdata(&dev->dev, drm); 1169 drm->dev_private = tegra; 1170 tegra->drm = drm; 1171 1172 drm_mode_config_init(drm); 1173 1174 drm->mode_config.min_width = 0; 1175 drm->mode_config.min_height = 0; 1176 drm->mode_config.max_width = 0; 1177 drm->mode_config.max_height = 0; 1178 1179 drm->mode_config.normalize_zpos = true; 1180 1181 drm->mode_config.funcs = &tegra_drm_mode_config_funcs; 1182 drm->mode_config.helper_private = &tegra_drm_mode_config_helpers; 1183 1184 drm_kms_helper_poll_init(drm); 1185 1186 err = host1x_device_init(dev); 1187 if (err < 0) 1188 goto poll; 1189 1190 /* 1191 * Now that all display controller have been initialized, the maximum 1192 * supported resolution is known and the bitmask for horizontal and 1193 * vertical bitfields can be computed. 1194 */ 1195 tegra->hmask = drm->mode_config.max_width - 1; 1196 tegra->vmask = drm->mode_config.max_height - 1; 1197 1198 if (tegra->use_explicit_iommu) { 1199 u64 carveout_start, carveout_end, gem_start, gem_end; 1200 u64 dma_mask = dma_get_mask(&dev->dev); 1201 dma_addr_t start, end; 1202 unsigned long order; 1203 1204 start = tegra->domain->geometry.aperture_start & dma_mask; 1205 end = tegra->domain->geometry.aperture_end & dma_mask; 1206 1207 gem_start = start; 1208 gem_end = end - CARVEOUT_SZ; 1209 carveout_start = gem_end + 1; 1210 carveout_end = end; 1211 1212 order = __ffs(tegra->domain->pgsize_bitmap); 1213 init_iova_domain(&tegra->carveout.domain, 1UL << order, 1214 carveout_start >> order); 1215 1216 tegra->carveout.shift = iova_shift(&tegra->carveout.domain); 1217 tegra->carveout.limit = carveout_end >> tegra->carveout.shift; 1218 1219 drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1); 1220 mutex_init(&tegra->mm_lock); 1221 1222 DRM_DEBUG_DRIVER("IOMMU apertures:\n"); 1223 DRM_DEBUG_DRIVER(" GEM: %#llx-%#llx\n", gem_start, gem_end); 1224 DRM_DEBUG_DRIVER(" Carveout: %#llx-%#llx\n", carveout_start, 1225 carveout_end); 1226 } else if (tegra->domain) { 1227 iommu_domain_free(tegra->domain); 1228 tegra->domain = NULL; 1229 iova_cache_put(); 1230 } 1231 1232 if (tegra->hub) { 1233 err = tegra_display_hub_prepare(tegra->hub); 1234 if (err < 0) 1235 goto device; 1236 } 1237 1238 /* syncpoints are used for full 32-bit hardware VBLANK counters */ 1239 drm->max_vblank_count = 0xffffffff; 1240 1241 err = drm_vblank_init(drm, drm->mode_config.num_crtc); 1242 if (err < 0) 1243 goto hub; 1244 1245 drm_mode_config_reset(drm); 1246 1247 err = drm_aperture_remove_framebuffers(false, &tegra_drm_driver); 1248 if (err < 0) 1249 goto hub; 1250 1251 err = drm_dev_register(drm, 0); 1252 if (err < 0) 1253 goto hub; 1254 1255 tegra_fbdev_setup(drm); 1256 1257 return 0; 1258 1259 hub: 1260 if (tegra->hub) 1261 tegra_display_hub_cleanup(tegra->hub); 1262 device: 1263 if (tegra->domain) { 1264 mutex_destroy(&tegra->mm_lock); 1265 drm_mm_takedown(&tegra->mm); 1266 put_iova_domain(&tegra->carveout.domain); 1267 iova_cache_put(); 1268 } 1269 1270 host1x_device_exit(dev); 1271 poll: 1272 drm_kms_helper_poll_fini(drm); 1273 drm_mode_config_cleanup(drm); 1274 domain: 1275 if (tegra->domain) 1276 iommu_domain_free(tegra->domain); 1277 free: 1278 kfree(tegra); 1279 put: 1280 drm_dev_put(drm); 1281 return err; 1282 } 1283 1284 static int host1x_drm_remove(struct host1x_device *dev) 1285 { 1286 struct drm_device *drm = dev_get_drvdata(&dev->dev); 1287 struct tegra_drm *tegra = drm->dev_private; 1288 int err; 1289 1290 drm_dev_unregister(drm); 1291 1292 drm_kms_helper_poll_fini(drm); 1293 drm_atomic_helper_shutdown(drm); 1294 drm_mode_config_cleanup(drm); 1295 1296 if (tegra->hub) 1297 tegra_display_hub_cleanup(tegra->hub); 1298 1299 err = host1x_device_exit(dev); 1300 if (err < 0) 1301 dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err); 1302 1303 if (tegra->domain) { 1304 mutex_destroy(&tegra->mm_lock); 1305 drm_mm_takedown(&tegra->mm); 1306 put_iova_domain(&tegra->carveout.domain); 1307 iova_cache_put(); 1308 iommu_domain_free(tegra->domain); 1309 } 1310 1311 kfree(tegra); 1312 drm_dev_put(drm); 1313 1314 return 0; 1315 } 1316 1317 #ifdef CONFIG_PM_SLEEP 1318 static int host1x_drm_suspend(struct device *dev) 1319 { 1320 struct drm_device *drm = dev_get_drvdata(dev); 1321 1322 return drm_mode_config_helper_suspend(drm); 1323 } 1324 1325 static int host1x_drm_resume(struct device *dev) 1326 { 1327 struct drm_device *drm = dev_get_drvdata(dev); 1328 1329 return drm_mode_config_helper_resume(drm); 1330 } 1331 #endif 1332 1333 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend, 1334 host1x_drm_resume); 1335 1336 static const struct of_device_id host1x_drm_subdevs[] = { 1337 { .compatible = "nvidia,tegra20-dc", }, 1338 { .compatible = "nvidia,tegra20-hdmi", }, 1339 { .compatible = "nvidia,tegra20-gr2d", }, 1340 { .compatible = "nvidia,tegra20-gr3d", }, 1341 { .compatible = "nvidia,tegra30-dc", }, 1342 { .compatible = "nvidia,tegra30-hdmi", }, 1343 { .compatible = "nvidia,tegra30-gr2d", }, 1344 { .compatible = "nvidia,tegra30-gr3d", }, 1345 { .compatible = "nvidia,tegra114-dc", }, 1346 { .compatible = "nvidia,tegra114-dsi", }, 1347 { .compatible = "nvidia,tegra114-hdmi", }, 1348 { .compatible = "nvidia,tegra114-gr2d", }, 1349 { .compatible = "nvidia,tegra114-gr3d", }, 1350 { .compatible = "nvidia,tegra124-dc", }, 1351 { .compatible = "nvidia,tegra124-sor", }, 1352 { .compatible = "nvidia,tegra124-hdmi", }, 1353 { .compatible = "nvidia,tegra124-dsi", }, 1354 { .compatible = "nvidia,tegra124-vic", }, 1355 { .compatible = "nvidia,tegra132-dsi", }, 1356 { .compatible = "nvidia,tegra210-dc", }, 1357 { .compatible = "nvidia,tegra210-dsi", }, 1358 { .compatible = "nvidia,tegra210-sor", }, 1359 { .compatible = "nvidia,tegra210-sor1", }, 1360 { .compatible = "nvidia,tegra210-vic", }, 1361 { .compatible = "nvidia,tegra210-nvdec", }, 1362 { .compatible = "nvidia,tegra186-display", }, 1363 { .compatible = "nvidia,tegra186-dc", }, 1364 { .compatible = "nvidia,tegra186-sor", }, 1365 { .compatible = "nvidia,tegra186-sor1", }, 1366 { .compatible = "nvidia,tegra186-vic", }, 1367 { .compatible = "nvidia,tegra186-nvdec", }, 1368 { .compatible = "nvidia,tegra194-display", }, 1369 { .compatible = "nvidia,tegra194-dc", }, 1370 { .compatible = "nvidia,tegra194-sor", }, 1371 { .compatible = "nvidia,tegra194-vic", }, 1372 { .compatible = "nvidia,tegra194-nvdec", }, 1373 { .compatible = "nvidia,tegra234-vic", }, 1374 { .compatible = "nvidia,tegra234-nvdec", }, 1375 { /* sentinel */ } 1376 }; 1377 1378 static struct host1x_driver host1x_drm_driver = { 1379 .driver = { 1380 .name = "drm", 1381 .pm = &host1x_drm_pm_ops, 1382 }, 1383 .probe = host1x_drm_probe, 1384 .remove = host1x_drm_remove, 1385 .subdevs = host1x_drm_subdevs, 1386 }; 1387 1388 static struct platform_driver * const drivers[] = { 1389 &tegra_display_hub_driver, 1390 &tegra_dc_driver, 1391 &tegra_hdmi_driver, 1392 &tegra_dsi_driver, 1393 &tegra_dpaux_driver, 1394 &tegra_sor_driver, 1395 &tegra_gr2d_driver, 1396 &tegra_gr3d_driver, 1397 &tegra_vic_driver, 1398 &tegra_nvdec_driver, 1399 }; 1400 1401 static int __init host1x_drm_init(void) 1402 { 1403 int err; 1404 1405 if (drm_firmware_drivers_only()) 1406 return -ENODEV; 1407 1408 err = host1x_driver_register(&host1x_drm_driver); 1409 if (err < 0) 1410 return err; 1411 1412 err = platform_register_drivers(drivers, ARRAY_SIZE(drivers)); 1413 if (err < 0) 1414 goto unregister_host1x; 1415 1416 return 0; 1417 1418 unregister_host1x: 1419 host1x_driver_unregister(&host1x_drm_driver); 1420 return err; 1421 } 1422 module_init(host1x_drm_init); 1423 1424 static void __exit host1x_drm_exit(void) 1425 { 1426 platform_unregister_drivers(drivers, ARRAY_SIZE(drivers)); 1427 host1x_driver_unregister(&host1x_drm_driver); 1428 } 1429 module_exit(host1x_drm_exit); 1430 1431 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>"); 1432 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver"); 1433 MODULE_LICENSE("GPL v2"); 1434