1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 NVIDIA Corporation 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/interrupt.h> 9 #include <linux/io.h> 10 #include <linux/module.h> 11 #include <linux/of_device.h> 12 #include <linux/pinctrl/pinconf-generic.h> 13 #include <linux/pinctrl/pinctrl.h> 14 #include <linux/pinctrl/pinmux.h> 15 #include <linux/platform_device.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 #include <linux/workqueue.h> 20 21 #include <drm/drm_dp_helper.h> 22 #include <drm/drm_dp_aux_bus.h> 23 #include <drm/drm_panel.h> 24 25 #include "dp.h" 26 #include "dpaux.h" 27 #include "drm.h" 28 #include "trace.h" 29 30 static DEFINE_MUTEX(dpaux_lock); 31 static LIST_HEAD(dpaux_list); 32 33 struct tegra_dpaux_soc { 34 unsigned int cmh; 35 unsigned int drvz; 36 unsigned int drvi; 37 }; 38 39 struct tegra_dpaux { 40 struct drm_dp_aux aux; 41 struct device *dev; 42 43 const struct tegra_dpaux_soc *soc; 44 45 void __iomem *regs; 46 int irq; 47 48 struct tegra_output *output; 49 50 struct reset_control *rst; 51 struct clk *clk_parent; 52 struct clk *clk; 53 54 struct regulator *vdd; 55 56 struct completion complete; 57 struct work_struct work; 58 struct list_head list; 59 60 #ifdef CONFIG_GENERIC_PINCONF 61 struct pinctrl_dev *pinctrl; 62 struct pinctrl_desc desc; 63 #endif 64 }; 65 66 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) 67 { 68 return container_of(aux, struct tegra_dpaux, aux); 69 } 70 71 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work) 72 { 73 return container_of(work, struct tegra_dpaux, work); 74 } 75 76 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, 77 unsigned int offset) 78 { 79 u32 value = readl(dpaux->regs + (offset << 2)); 80 81 trace_dpaux_readl(dpaux->dev, offset, value); 82 83 return value; 84 } 85 86 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, 87 u32 value, unsigned int offset) 88 { 89 trace_dpaux_writel(dpaux->dev, offset, value); 90 writel(value, dpaux->regs + (offset << 2)); 91 } 92 93 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, 94 size_t size) 95 { 96 size_t i, j; 97 98 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 99 size_t num = min_t(size_t, size - i * 4, 4); 100 u32 value = 0; 101 102 for (j = 0; j < num; j++) 103 value |= buffer[i * 4 + j] << (j * 8); 104 105 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); 106 } 107 } 108 109 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, 110 size_t size) 111 { 112 size_t i, j; 113 114 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 115 size_t num = min_t(size_t, size - i * 4, 4); 116 u32 value; 117 118 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); 119 120 for (j = 0; j < num; j++) 121 buffer[i * 4 + j] = value >> (j * 8); 122 } 123 } 124 125 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux, 126 struct drm_dp_aux_msg *msg) 127 { 128 unsigned long timeout = msecs_to_jiffies(250); 129 struct tegra_dpaux *dpaux = to_dpaux(aux); 130 unsigned long status; 131 ssize_t ret = 0; 132 u8 reply = 0; 133 u32 value; 134 135 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */ 136 if (msg->size > 16) 137 return -EINVAL; 138 139 /* 140 * Allow zero-sized messages only for I2C, in which case they specify 141 * address-only transactions. 142 */ 143 if (msg->size < 1) { 144 switch (msg->request & ~DP_AUX_I2C_MOT) { 145 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 146 case DP_AUX_I2C_WRITE: 147 case DP_AUX_I2C_READ: 148 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY; 149 break; 150 151 default: 152 return -EINVAL; 153 } 154 } else { 155 /* For non-zero-sized messages, set the CMDLEN field. */ 156 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); 157 } 158 159 switch (msg->request & ~DP_AUX_I2C_MOT) { 160 case DP_AUX_I2C_WRITE: 161 if (msg->request & DP_AUX_I2C_MOT) 162 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR; 163 else 164 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR; 165 166 break; 167 168 case DP_AUX_I2C_READ: 169 if (msg->request & DP_AUX_I2C_MOT) 170 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD; 171 else 172 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD; 173 174 break; 175 176 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 177 if (msg->request & DP_AUX_I2C_MOT) 178 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ; 179 else 180 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ; 181 182 break; 183 184 case DP_AUX_NATIVE_WRITE: 185 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR; 186 break; 187 188 case DP_AUX_NATIVE_READ: 189 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD; 190 break; 191 192 default: 193 return -EINVAL; 194 } 195 196 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); 197 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); 198 199 if ((msg->request & DP_AUX_I2C_READ) == 0) { 200 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); 201 ret = msg->size; 202 } 203 204 /* start transaction */ 205 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); 206 value |= DPAUX_DP_AUXCTL_TRANSACTREQ; 207 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); 208 209 status = wait_for_completion_timeout(&dpaux->complete, timeout); 210 if (!status) 211 return -ETIMEDOUT; 212 213 /* read status and clear errors */ 214 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); 215 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); 216 217 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR) 218 return -ETIMEDOUT; 219 220 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) || 221 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) || 222 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR)) 223 return -EIO; 224 225 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) { 226 case 0x00: 227 reply = DP_AUX_NATIVE_REPLY_ACK; 228 break; 229 230 case 0x01: 231 reply = DP_AUX_NATIVE_REPLY_NACK; 232 break; 233 234 case 0x02: 235 reply = DP_AUX_NATIVE_REPLY_DEFER; 236 break; 237 238 case 0x04: 239 reply = DP_AUX_I2C_REPLY_NACK; 240 break; 241 242 case 0x08: 243 reply = DP_AUX_I2C_REPLY_DEFER; 244 break; 245 } 246 247 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) { 248 if (msg->request & DP_AUX_I2C_READ) { 249 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK; 250 251 /* 252 * There might be a smarter way to do this, but since 253 * the DP helpers will already retry transactions for 254 * an -EBUSY return value, simply reuse that instead. 255 */ 256 if (count != msg->size) { 257 ret = -EBUSY; 258 goto out; 259 } 260 261 tegra_dpaux_read_fifo(dpaux, msg->buffer, count); 262 ret = count; 263 } 264 } 265 266 msg->reply = reply; 267 268 out: 269 return ret; 270 } 271 272 static void tegra_dpaux_hotplug(struct work_struct *work) 273 { 274 struct tegra_dpaux *dpaux = work_to_dpaux(work); 275 276 if (dpaux->output) 277 drm_helper_hpd_irq_event(dpaux->output->connector.dev); 278 } 279 280 static irqreturn_t tegra_dpaux_irq(int irq, void *data) 281 { 282 struct tegra_dpaux *dpaux = data; 283 irqreturn_t ret = IRQ_HANDLED; 284 u32 value; 285 286 /* clear interrupts */ 287 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); 288 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 289 290 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT)) 291 schedule_work(&dpaux->work); 292 293 if (value & DPAUX_INTR_IRQ_EVENT) { 294 /* TODO: handle this */ 295 } 296 297 if (value & DPAUX_INTR_AUX_DONE) 298 complete(&dpaux->complete); 299 300 return ret; 301 } 302 303 enum tegra_dpaux_functions { 304 DPAUX_PADCTL_FUNC_AUX, 305 DPAUX_PADCTL_FUNC_I2C, 306 DPAUX_PADCTL_FUNC_OFF, 307 }; 308 309 static void tegra_dpaux_pad_power_down(struct tegra_dpaux *dpaux) 310 { 311 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 312 313 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 314 315 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 316 } 317 318 static void tegra_dpaux_pad_power_up(struct tegra_dpaux *dpaux) 319 { 320 u32 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 321 322 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 323 324 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 325 } 326 327 static int tegra_dpaux_pad_config(struct tegra_dpaux *dpaux, unsigned function) 328 { 329 u32 value; 330 331 switch (function) { 332 case DPAUX_PADCTL_FUNC_AUX: 333 value = DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | 334 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | 335 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | 336 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV | 337 DPAUX_HYBRID_PADCTL_MODE_AUX; 338 break; 339 340 case DPAUX_PADCTL_FUNC_I2C: 341 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV | 342 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV | 343 DPAUX_HYBRID_PADCTL_AUX_CMH(dpaux->soc->cmh) | 344 DPAUX_HYBRID_PADCTL_AUX_DRVZ(dpaux->soc->drvz) | 345 DPAUX_HYBRID_PADCTL_AUX_DRVI(dpaux->soc->drvi) | 346 DPAUX_HYBRID_PADCTL_MODE_I2C; 347 break; 348 349 case DPAUX_PADCTL_FUNC_OFF: 350 tegra_dpaux_pad_power_down(dpaux); 351 return 0; 352 353 default: 354 return -ENOTSUPP; 355 } 356 357 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); 358 tegra_dpaux_pad_power_up(dpaux); 359 360 return 0; 361 } 362 363 #ifdef CONFIG_GENERIC_PINCONF 364 static const struct pinctrl_pin_desc tegra_dpaux_pins[] = { 365 PINCTRL_PIN(0, "DP_AUX_CHx_P"), 366 PINCTRL_PIN(1, "DP_AUX_CHx_N"), 367 }; 368 369 static const unsigned tegra_dpaux_pin_numbers[] = { 0, 1 }; 370 371 static const char * const tegra_dpaux_groups[] = { 372 "dpaux-io", 373 }; 374 375 static const char * const tegra_dpaux_functions[] = { 376 "aux", 377 "i2c", 378 "off", 379 }; 380 381 static int tegra_dpaux_get_groups_count(struct pinctrl_dev *pinctrl) 382 { 383 return ARRAY_SIZE(tegra_dpaux_groups); 384 } 385 386 static const char *tegra_dpaux_get_group_name(struct pinctrl_dev *pinctrl, 387 unsigned int group) 388 { 389 return tegra_dpaux_groups[group]; 390 } 391 392 static int tegra_dpaux_get_group_pins(struct pinctrl_dev *pinctrl, 393 unsigned group, const unsigned **pins, 394 unsigned *num_pins) 395 { 396 *pins = tegra_dpaux_pin_numbers; 397 *num_pins = ARRAY_SIZE(tegra_dpaux_pin_numbers); 398 399 return 0; 400 } 401 402 static const struct pinctrl_ops tegra_dpaux_pinctrl_ops = { 403 .get_groups_count = tegra_dpaux_get_groups_count, 404 .get_group_name = tegra_dpaux_get_group_name, 405 .get_group_pins = tegra_dpaux_get_group_pins, 406 .dt_node_to_map = pinconf_generic_dt_node_to_map_group, 407 .dt_free_map = pinconf_generic_dt_free_map, 408 }; 409 410 static int tegra_dpaux_get_functions_count(struct pinctrl_dev *pinctrl) 411 { 412 return ARRAY_SIZE(tegra_dpaux_functions); 413 } 414 415 static const char *tegra_dpaux_get_function_name(struct pinctrl_dev *pinctrl, 416 unsigned int function) 417 { 418 return tegra_dpaux_functions[function]; 419 } 420 421 static int tegra_dpaux_get_function_groups(struct pinctrl_dev *pinctrl, 422 unsigned int function, 423 const char * const **groups, 424 unsigned * const num_groups) 425 { 426 *num_groups = ARRAY_SIZE(tegra_dpaux_groups); 427 *groups = tegra_dpaux_groups; 428 429 return 0; 430 } 431 432 static int tegra_dpaux_set_mux(struct pinctrl_dev *pinctrl, 433 unsigned int function, unsigned int group) 434 { 435 struct tegra_dpaux *dpaux = pinctrl_dev_get_drvdata(pinctrl); 436 437 return tegra_dpaux_pad_config(dpaux, function); 438 } 439 440 static const struct pinmux_ops tegra_dpaux_pinmux_ops = { 441 .get_functions_count = tegra_dpaux_get_functions_count, 442 .get_function_name = tegra_dpaux_get_function_name, 443 .get_function_groups = tegra_dpaux_get_function_groups, 444 .set_mux = tegra_dpaux_set_mux, 445 }; 446 #endif 447 448 static int tegra_dpaux_probe(struct platform_device *pdev) 449 { 450 struct tegra_dpaux *dpaux; 451 struct resource *regs; 452 u32 value; 453 int err; 454 455 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); 456 if (!dpaux) 457 return -ENOMEM; 458 459 dpaux->soc = of_device_get_match_data(&pdev->dev); 460 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug); 461 init_completion(&dpaux->complete); 462 INIT_LIST_HEAD(&dpaux->list); 463 dpaux->dev = &pdev->dev; 464 465 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 466 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs); 467 if (IS_ERR(dpaux->regs)) 468 return PTR_ERR(dpaux->regs); 469 470 dpaux->irq = platform_get_irq(pdev, 0); 471 if (dpaux->irq < 0) 472 return -ENXIO; 473 474 if (!pdev->dev.pm_domain) { 475 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); 476 if (IS_ERR(dpaux->rst)) { 477 dev_err(&pdev->dev, 478 "failed to get reset control: %ld\n", 479 PTR_ERR(dpaux->rst)); 480 return PTR_ERR(dpaux->rst); 481 } 482 } 483 484 dpaux->clk = devm_clk_get(&pdev->dev, NULL); 485 if (IS_ERR(dpaux->clk)) { 486 dev_err(&pdev->dev, "failed to get module clock: %ld\n", 487 PTR_ERR(dpaux->clk)); 488 return PTR_ERR(dpaux->clk); 489 } 490 491 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); 492 if (IS_ERR(dpaux->clk_parent)) { 493 dev_err(&pdev->dev, "failed to get parent clock: %ld\n", 494 PTR_ERR(dpaux->clk_parent)); 495 return PTR_ERR(dpaux->clk_parent); 496 } 497 498 err = clk_set_rate(dpaux->clk_parent, 270000000); 499 if (err < 0) { 500 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", 501 err); 502 return err; 503 } 504 505 dpaux->vdd = devm_regulator_get_optional(&pdev->dev, "vdd"); 506 if (IS_ERR(dpaux->vdd)) { 507 if (PTR_ERR(dpaux->vdd) != -ENODEV) { 508 if (PTR_ERR(dpaux->vdd) != -EPROBE_DEFER) 509 dev_err(&pdev->dev, 510 "failed to get VDD supply: %ld\n", 511 PTR_ERR(dpaux->vdd)); 512 513 return PTR_ERR(dpaux->vdd); 514 } 515 516 dpaux->vdd = NULL; 517 } 518 519 platform_set_drvdata(pdev, dpaux); 520 pm_runtime_enable(&pdev->dev); 521 pm_runtime_get_sync(&pdev->dev); 522 523 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, 524 dev_name(dpaux->dev), dpaux); 525 if (err < 0) { 526 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", 527 dpaux->irq, err); 528 return err; 529 } 530 531 disable_irq(dpaux->irq); 532 533 dpaux->aux.transfer = tegra_dpaux_transfer; 534 dpaux->aux.dev = &pdev->dev; 535 536 drm_dp_aux_init(&dpaux->aux); 537 538 /* 539 * Assume that by default the DPAUX/I2C pads will be used for HDMI, 540 * so power them up and configure them in I2C mode. 541 * 542 * The DPAUX code paths reconfigure the pads in AUX mode, but there 543 * is no possibility to perform the I2C mode configuration in the 544 * HDMI path. 545 */ 546 err = tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_I2C); 547 if (err < 0) 548 return err; 549 550 #ifdef CONFIG_GENERIC_PINCONF 551 dpaux->desc.name = dev_name(&pdev->dev); 552 dpaux->desc.pins = tegra_dpaux_pins; 553 dpaux->desc.npins = ARRAY_SIZE(tegra_dpaux_pins); 554 dpaux->desc.pctlops = &tegra_dpaux_pinctrl_ops; 555 dpaux->desc.pmxops = &tegra_dpaux_pinmux_ops; 556 dpaux->desc.owner = THIS_MODULE; 557 558 dpaux->pinctrl = devm_pinctrl_register(&pdev->dev, &dpaux->desc, dpaux); 559 if (IS_ERR(dpaux->pinctrl)) { 560 dev_err(&pdev->dev, "failed to register pincontrol\n"); 561 return PTR_ERR(dpaux->pinctrl); 562 } 563 #endif 564 /* enable and clear all interrupts */ 565 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT | 566 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT; 567 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); 568 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 569 570 mutex_lock(&dpaux_lock); 571 list_add_tail(&dpaux->list, &dpaux_list); 572 mutex_unlock(&dpaux_lock); 573 574 err = devm_of_dp_aux_populate_ep_devices(&dpaux->aux); 575 if (err < 0) { 576 dev_err(dpaux->dev, "failed to populate AUX bus: %d\n", err); 577 return err; 578 } 579 580 return 0; 581 } 582 583 static int tegra_dpaux_remove(struct platform_device *pdev) 584 { 585 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); 586 587 cancel_work_sync(&dpaux->work); 588 589 /* make sure pads are powered down when not in use */ 590 tegra_dpaux_pad_power_down(dpaux); 591 592 pm_runtime_put_sync(&pdev->dev); 593 pm_runtime_disable(&pdev->dev); 594 595 mutex_lock(&dpaux_lock); 596 list_del(&dpaux->list); 597 mutex_unlock(&dpaux_lock); 598 599 return 0; 600 } 601 602 #ifdef CONFIG_PM 603 static int tegra_dpaux_suspend(struct device *dev) 604 { 605 struct tegra_dpaux *dpaux = dev_get_drvdata(dev); 606 int err = 0; 607 608 if (dpaux->rst) { 609 err = reset_control_assert(dpaux->rst); 610 if (err < 0) { 611 dev_err(dev, "failed to assert reset: %d\n", err); 612 return err; 613 } 614 } 615 616 usleep_range(1000, 2000); 617 618 clk_disable_unprepare(dpaux->clk_parent); 619 clk_disable_unprepare(dpaux->clk); 620 621 return err; 622 } 623 624 static int tegra_dpaux_resume(struct device *dev) 625 { 626 struct tegra_dpaux *dpaux = dev_get_drvdata(dev); 627 int err; 628 629 err = clk_prepare_enable(dpaux->clk); 630 if (err < 0) { 631 dev_err(dev, "failed to enable clock: %d\n", err); 632 return err; 633 } 634 635 err = clk_prepare_enable(dpaux->clk_parent); 636 if (err < 0) { 637 dev_err(dev, "failed to enable parent clock: %d\n", err); 638 goto disable_clk; 639 } 640 641 usleep_range(1000, 2000); 642 643 if (dpaux->rst) { 644 err = reset_control_deassert(dpaux->rst); 645 if (err < 0) { 646 dev_err(dev, "failed to deassert reset: %d\n", err); 647 goto disable_parent; 648 } 649 650 usleep_range(1000, 2000); 651 } 652 653 return 0; 654 655 disable_parent: 656 clk_disable_unprepare(dpaux->clk_parent); 657 disable_clk: 658 clk_disable_unprepare(dpaux->clk); 659 return err; 660 } 661 #endif 662 663 static const struct dev_pm_ops tegra_dpaux_pm_ops = { 664 SET_RUNTIME_PM_OPS(tegra_dpaux_suspend, tegra_dpaux_resume, NULL) 665 }; 666 667 static const struct tegra_dpaux_soc tegra124_dpaux_soc = { 668 .cmh = 0x02, 669 .drvz = 0x04, 670 .drvi = 0x18, 671 }; 672 673 static const struct tegra_dpaux_soc tegra210_dpaux_soc = { 674 .cmh = 0x02, 675 .drvz = 0x04, 676 .drvi = 0x30, 677 }; 678 679 static const struct tegra_dpaux_soc tegra194_dpaux_soc = { 680 .cmh = 0x02, 681 .drvz = 0x04, 682 .drvi = 0x2c, 683 }; 684 685 static const struct of_device_id tegra_dpaux_of_match[] = { 686 { .compatible = "nvidia,tegra194-dpaux", .data = &tegra194_dpaux_soc }, 687 { .compatible = "nvidia,tegra186-dpaux", .data = &tegra210_dpaux_soc }, 688 { .compatible = "nvidia,tegra210-dpaux", .data = &tegra210_dpaux_soc }, 689 { .compatible = "nvidia,tegra124-dpaux", .data = &tegra124_dpaux_soc }, 690 { }, 691 }; 692 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match); 693 694 struct platform_driver tegra_dpaux_driver = { 695 .driver = { 696 .name = "tegra-dpaux", 697 .of_match_table = tegra_dpaux_of_match, 698 .pm = &tegra_dpaux_pm_ops, 699 }, 700 .probe = tegra_dpaux_probe, 701 .remove = tegra_dpaux_remove, 702 }; 703 704 struct drm_dp_aux *drm_dp_aux_find_by_of_node(struct device_node *np) 705 { 706 struct tegra_dpaux *dpaux; 707 708 mutex_lock(&dpaux_lock); 709 710 list_for_each_entry(dpaux, &dpaux_list, list) 711 if (np == dpaux->dev->of_node) { 712 mutex_unlock(&dpaux_lock); 713 return &dpaux->aux; 714 } 715 716 mutex_unlock(&dpaux_lock); 717 718 return NULL; 719 } 720 721 int drm_dp_aux_attach(struct drm_dp_aux *aux, struct tegra_output *output) 722 { 723 struct tegra_dpaux *dpaux = to_dpaux(aux); 724 unsigned long timeout; 725 int err; 726 727 aux->drm_dev = output->connector.dev; 728 err = drm_dp_aux_register(aux); 729 if (err < 0) 730 return err; 731 732 output->connector.polled = DRM_CONNECTOR_POLL_HPD; 733 dpaux->output = output; 734 735 if (output->panel) { 736 enum drm_connector_status status; 737 738 if (dpaux->vdd) { 739 err = regulator_enable(dpaux->vdd); 740 if (err < 0) 741 return err; 742 } 743 744 timeout = jiffies + msecs_to_jiffies(250); 745 746 while (time_before(jiffies, timeout)) { 747 status = drm_dp_aux_detect(aux); 748 749 if (status == connector_status_connected) 750 break; 751 752 usleep_range(1000, 2000); 753 } 754 755 if (status != connector_status_connected) 756 return -ETIMEDOUT; 757 } 758 759 enable_irq(dpaux->irq); 760 return 0; 761 } 762 763 int drm_dp_aux_detach(struct drm_dp_aux *aux) 764 { 765 struct tegra_dpaux *dpaux = to_dpaux(aux); 766 unsigned long timeout; 767 int err; 768 769 drm_dp_aux_unregister(aux); 770 disable_irq(dpaux->irq); 771 772 if (dpaux->output->panel) { 773 enum drm_connector_status status; 774 775 if (dpaux->vdd) { 776 err = regulator_disable(dpaux->vdd); 777 if (err < 0) 778 return err; 779 } 780 781 timeout = jiffies + msecs_to_jiffies(250); 782 783 while (time_before(jiffies, timeout)) { 784 status = drm_dp_aux_detect(aux); 785 786 if (status == connector_status_disconnected) 787 break; 788 789 usleep_range(1000, 2000); 790 } 791 792 if (status != connector_status_disconnected) 793 return -ETIMEDOUT; 794 795 dpaux->output = NULL; 796 } 797 798 return 0; 799 } 800 801 enum drm_connector_status drm_dp_aux_detect(struct drm_dp_aux *aux) 802 { 803 struct tegra_dpaux *dpaux = to_dpaux(aux); 804 u32 value; 805 806 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); 807 808 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS) 809 return connector_status_connected; 810 811 return connector_status_disconnected; 812 } 813 814 int drm_dp_aux_enable(struct drm_dp_aux *aux) 815 { 816 struct tegra_dpaux *dpaux = to_dpaux(aux); 817 818 return tegra_dpaux_pad_config(dpaux, DPAUX_PADCTL_FUNC_AUX); 819 } 820 821 int drm_dp_aux_disable(struct drm_dp_aux *aux) 822 { 823 struct tegra_dpaux *dpaux = to_dpaux(aux); 824 825 tegra_dpaux_pad_power_down(dpaux); 826 827 return 0; 828 } 829