1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_gpio.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/workqueue.h> 19 20 #include <drm/drm_dp_helper.h> 21 #include <drm/drm_panel.h> 22 23 #include "dpaux.h" 24 #include "drm.h" 25 26 static DEFINE_MUTEX(dpaux_lock); 27 static LIST_HEAD(dpaux_list); 28 29 struct tegra_dpaux { 30 struct drm_dp_aux aux; 31 struct device *dev; 32 33 void __iomem *regs; 34 int irq; 35 36 struct tegra_output *output; 37 38 struct reset_control *rst; 39 struct clk *clk_parent; 40 struct clk *clk; 41 42 struct regulator *vdd; 43 44 struct completion complete; 45 struct work_struct work; 46 struct list_head list; 47 }; 48 49 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) 50 { 51 return container_of(aux, struct tegra_dpaux, aux); 52 } 53 54 static inline struct tegra_dpaux *work_to_dpaux(struct work_struct *work) 55 { 56 return container_of(work, struct tegra_dpaux, work); 57 } 58 59 static inline u32 tegra_dpaux_readl(struct tegra_dpaux *dpaux, 60 unsigned long offset) 61 { 62 return readl(dpaux->regs + (offset << 2)); 63 } 64 65 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, 66 u32 value, unsigned long offset) 67 { 68 writel(value, dpaux->regs + (offset << 2)); 69 } 70 71 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, 72 size_t size) 73 { 74 size_t i, j; 75 76 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 77 size_t num = min_t(size_t, size - i * 4, 4); 78 u32 value = 0; 79 80 for (j = 0; j < num; j++) 81 value |= buffer[i * 4 + j] << (j * 8); 82 83 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXDATA_WRITE(i)); 84 } 85 } 86 87 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, 88 size_t size) 89 { 90 size_t i, j; 91 92 for (i = 0; i < DIV_ROUND_UP(size, 4); i++) { 93 size_t num = min_t(size_t, size - i * 4, 4); 94 u32 value; 95 96 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXDATA_READ(i)); 97 98 for (j = 0; j < num; j++) 99 buffer[i * 4 + j] = value >> (j * 8); 100 } 101 } 102 103 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux, 104 struct drm_dp_aux_msg *msg) 105 { 106 unsigned long timeout = msecs_to_jiffies(250); 107 struct tegra_dpaux *dpaux = to_dpaux(aux); 108 unsigned long status; 109 ssize_t ret = 0; 110 u32 value; 111 112 /* Tegra has 4x4 byte DP AUX transmit and receive FIFOs. */ 113 if (msg->size > 16) 114 return -EINVAL; 115 116 /* 117 * Allow zero-sized messages only for I2C, in which case they specify 118 * address-only transactions. 119 */ 120 if (msg->size < 1) { 121 switch (msg->request & ~DP_AUX_I2C_MOT) { 122 case DP_AUX_I2C_WRITE: 123 case DP_AUX_I2C_READ: 124 value = DPAUX_DP_AUXCTL_CMD_ADDRESS_ONLY; 125 break; 126 127 default: 128 return -EINVAL; 129 } 130 } else { 131 /* For non-zero-sized messages, set the CMDLEN field. */ 132 value = DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); 133 } 134 135 switch (msg->request & ~DP_AUX_I2C_MOT) { 136 case DP_AUX_I2C_WRITE: 137 if (msg->request & DP_AUX_I2C_MOT) 138 value |= DPAUX_DP_AUXCTL_CMD_MOT_WR; 139 else 140 value |= DPAUX_DP_AUXCTL_CMD_I2C_WR; 141 142 break; 143 144 case DP_AUX_I2C_READ: 145 if (msg->request & DP_AUX_I2C_MOT) 146 value |= DPAUX_DP_AUXCTL_CMD_MOT_RD; 147 else 148 value |= DPAUX_DP_AUXCTL_CMD_I2C_RD; 149 150 break; 151 152 case DP_AUX_I2C_STATUS: 153 if (msg->request & DP_AUX_I2C_MOT) 154 value |= DPAUX_DP_AUXCTL_CMD_MOT_RQ; 155 else 156 value |= DPAUX_DP_AUXCTL_CMD_I2C_RQ; 157 158 break; 159 160 case DP_AUX_NATIVE_WRITE: 161 value |= DPAUX_DP_AUXCTL_CMD_AUX_WR; 162 break; 163 164 case DP_AUX_NATIVE_READ: 165 value |= DPAUX_DP_AUXCTL_CMD_AUX_RD; 166 break; 167 168 default: 169 return -EINVAL; 170 } 171 172 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); 173 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); 174 175 if ((msg->request & DP_AUX_I2C_READ) == 0) { 176 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); 177 ret = msg->size; 178 } 179 180 /* start transaction */ 181 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); 182 value |= DPAUX_DP_AUXCTL_TRANSACTREQ; 183 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); 184 185 status = wait_for_completion_timeout(&dpaux->complete, timeout); 186 if (!status) 187 return -ETIMEDOUT; 188 189 /* read status and clear errors */ 190 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); 191 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); 192 193 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR) 194 return -ETIMEDOUT; 195 196 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) || 197 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) || 198 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR)) 199 return -EIO; 200 201 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) { 202 case 0x00: 203 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 204 break; 205 206 case 0x01: 207 msg->reply = DP_AUX_NATIVE_REPLY_NACK; 208 break; 209 210 case 0x02: 211 msg->reply = DP_AUX_NATIVE_REPLY_DEFER; 212 break; 213 214 case 0x04: 215 msg->reply = DP_AUX_I2C_REPLY_NACK; 216 break; 217 218 case 0x08: 219 msg->reply = DP_AUX_I2C_REPLY_DEFER; 220 break; 221 } 222 223 if ((msg->size > 0) && (msg->reply == DP_AUX_NATIVE_REPLY_ACK)) { 224 if (msg->request & DP_AUX_I2C_READ) { 225 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK; 226 227 if (WARN_ON(count != msg->size)) 228 count = min_t(size_t, count, msg->size); 229 230 tegra_dpaux_read_fifo(dpaux, msg->buffer, count); 231 ret = count; 232 } 233 } 234 235 return ret; 236 } 237 238 static void tegra_dpaux_hotplug(struct work_struct *work) 239 { 240 struct tegra_dpaux *dpaux = work_to_dpaux(work); 241 242 if (dpaux->output) 243 drm_helper_hpd_irq_event(dpaux->output->connector.dev); 244 } 245 246 static irqreturn_t tegra_dpaux_irq(int irq, void *data) 247 { 248 struct tegra_dpaux *dpaux = data; 249 irqreturn_t ret = IRQ_HANDLED; 250 u32 value; 251 252 /* clear interrupts */ 253 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); 254 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 255 256 if (value & (DPAUX_INTR_PLUG_EVENT | DPAUX_INTR_UNPLUG_EVENT)) 257 schedule_work(&dpaux->work); 258 259 if (value & DPAUX_INTR_IRQ_EVENT) { 260 /* TODO: handle this */ 261 } 262 263 if (value & DPAUX_INTR_AUX_DONE) 264 complete(&dpaux->complete); 265 266 return ret; 267 } 268 269 static int tegra_dpaux_probe(struct platform_device *pdev) 270 { 271 struct tegra_dpaux *dpaux; 272 struct resource *regs; 273 u32 value; 274 int err; 275 276 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); 277 if (!dpaux) 278 return -ENOMEM; 279 280 INIT_WORK(&dpaux->work, tegra_dpaux_hotplug); 281 init_completion(&dpaux->complete); 282 INIT_LIST_HEAD(&dpaux->list); 283 dpaux->dev = &pdev->dev; 284 285 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 286 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs); 287 if (IS_ERR(dpaux->regs)) 288 return PTR_ERR(dpaux->regs); 289 290 dpaux->irq = platform_get_irq(pdev, 0); 291 if (dpaux->irq < 0) { 292 dev_err(&pdev->dev, "failed to get IRQ\n"); 293 return -ENXIO; 294 } 295 296 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); 297 if (IS_ERR(dpaux->rst)) { 298 dev_err(&pdev->dev, "failed to get reset control: %ld\n", 299 PTR_ERR(dpaux->rst)); 300 return PTR_ERR(dpaux->rst); 301 } 302 303 dpaux->clk = devm_clk_get(&pdev->dev, NULL); 304 if (IS_ERR(dpaux->clk)) { 305 dev_err(&pdev->dev, "failed to get module clock: %ld\n", 306 PTR_ERR(dpaux->clk)); 307 return PTR_ERR(dpaux->clk); 308 } 309 310 err = clk_prepare_enable(dpaux->clk); 311 if (err < 0) { 312 dev_err(&pdev->dev, "failed to enable module clock: %d\n", 313 err); 314 return err; 315 } 316 317 reset_control_deassert(dpaux->rst); 318 319 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); 320 if (IS_ERR(dpaux->clk_parent)) { 321 dev_err(&pdev->dev, "failed to get parent clock: %ld\n", 322 PTR_ERR(dpaux->clk_parent)); 323 return PTR_ERR(dpaux->clk_parent); 324 } 325 326 err = clk_prepare_enable(dpaux->clk_parent); 327 if (err < 0) { 328 dev_err(&pdev->dev, "failed to enable parent clock: %d\n", 329 err); 330 return err; 331 } 332 333 err = clk_set_rate(dpaux->clk_parent, 270000000); 334 if (err < 0) { 335 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", 336 err); 337 return err; 338 } 339 340 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); 341 if (IS_ERR(dpaux->vdd)) { 342 dev_err(&pdev->dev, "failed to get VDD supply: %ld\n", 343 PTR_ERR(dpaux->vdd)); 344 return PTR_ERR(dpaux->vdd); 345 } 346 347 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, 348 dev_name(dpaux->dev), dpaux); 349 if (err < 0) { 350 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", 351 dpaux->irq, err); 352 return err; 353 } 354 355 disable_irq(dpaux->irq); 356 357 dpaux->aux.transfer = tegra_dpaux_transfer; 358 dpaux->aux.dev = &pdev->dev; 359 360 err = drm_dp_aux_register(&dpaux->aux); 361 if (err < 0) 362 return err; 363 364 /* 365 * Assume that by default the DPAUX/I2C pads will be used for HDMI, 366 * so power them up and configure them in I2C mode. 367 * 368 * The DPAUX code paths reconfigure the pads in AUX mode, but there 369 * is no possibility to perform the I2C mode configuration in the 370 * HDMI path. 371 */ 372 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 373 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 374 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 375 376 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_PADCTL); 377 value = DPAUX_HYBRID_PADCTL_I2C_SDA_INPUT_RCV | 378 DPAUX_HYBRID_PADCTL_I2C_SCL_INPUT_RCV | 379 DPAUX_HYBRID_PADCTL_MODE_I2C; 380 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); 381 382 /* enable and clear all interrupts */ 383 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT | 384 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT; 385 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); 386 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 387 388 mutex_lock(&dpaux_lock); 389 list_add_tail(&dpaux->list, &dpaux_list); 390 mutex_unlock(&dpaux_lock); 391 392 platform_set_drvdata(pdev, dpaux); 393 394 return 0; 395 } 396 397 static int tegra_dpaux_remove(struct platform_device *pdev) 398 { 399 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); 400 u32 value; 401 402 /* make sure pads are powered down when not in use */ 403 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 404 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 405 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 406 407 drm_dp_aux_unregister(&dpaux->aux); 408 409 mutex_lock(&dpaux_lock); 410 list_del(&dpaux->list); 411 mutex_unlock(&dpaux_lock); 412 413 cancel_work_sync(&dpaux->work); 414 415 clk_disable_unprepare(dpaux->clk_parent); 416 reset_control_assert(dpaux->rst); 417 clk_disable_unprepare(dpaux->clk); 418 419 return 0; 420 } 421 422 static const struct of_device_id tegra_dpaux_of_match[] = { 423 { .compatible = "nvidia,tegra210-dpaux", }, 424 { .compatible = "nvidia,tegra124-dpaux", }, 425 { }, 426 }; 427 MODULE_DEVICE_TABLE(of, tegra_dpaux_of_match); 428 429 struct platform_driver tegra_dpaux_driver = { 430 .driver = { 431 .name = "tegra-dpaux", 432 .of_match_table = tegra_dpaux_of_match, 433 }, 434 .probe = tegra_dpaux_probe, 435 .remove = tegra_dpaux_remove, 436 }; 437 438 struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np) 439 { 440 struct tegra_dpaux *dpaux; 441 442 mutex_lock(&dpaux_lock); 443 444 list_for_each_entry(dpaux, &dpaux_list, list) 445 if (np == dpaux->dev->of_node) { 446 mutex_unlock(&dpaux_lock); 447 return dpaux; 448 } 449 450 mutex_unlock(&dpaux_lock); 451 452 return NULL; 453 } 454 455 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output) 456 { 457 unsigned long timeout; 458 int err; 459 460 output->connector.polled = DRM_CONNECTOR_POLL_HPD; 461 dpaux->output = output; 462 463 err = regulator_enable(dpaux->vdd); 464 if (err < 0) 465 return err; 466 467 timeout = jiffies + msecs_to_jiffies(250); 468 469 while (time_before(jiffies, timeout)) { 470 enum drm_connector_status status; 471 472 status = tegra_dpaux_detect(dpaux); 473 if (status == connector_status_connected) { 474 enable_irq(dpaux->irq); 475 return 0; 476 } 477 478 usleep_range(1000, 2000); 479 } 480 481 return -ETIMEDOUT; 482 } 483 484 int tegra_dpaux_detach(struct tegra_dpaux *dpaux) 485 { 486 unsigned long timeout; 487 int err; 488 489 disable_irq(dpaux->irq); 490 491 err = regulator_disable(dpaux->vdd); 492 if (err < 0) 493 return err; 494 495 timeout = jiffies + msecs_to_jiffies(250); 496 497 while (time_before(jiffies, timeout)) { 498 enum drm_connector_status status; 499 500 status = tegra_dpaux_detect(dpaux); 501 if (status == connector_status_disconnected) { 502 dpaux->output = NULL; 503 return 0; 504 } 505 506 usleep_range(1000, 2000); 507 } 508 509 return -ETIMEDOUT; 510 } 511 512 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux) 513 { 514 u32 value; 515 516 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); 517 518 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS) 519 return connector_status_connected; 520 521 return connector_status_disconnected; 522 } 523 524 int tegra_dpaux_enable(struct tegra_dpaux *dpaux) 525 { 526 u32 value; 527 528 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) | 529 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) | 530 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) | 531 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV | 532 DPAUX_HYBRID_PADCTL_MODE_AUX; 533 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); 534 535 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 536 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 537 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 538 539 return 0; 540 } 541 542 int tegra_dpaux_disable(struct tegra_dpaux *dpaux) 543 { 544 u32 value; 545 546 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 547 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 548 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 549 550 return 0; 551 } 552 553 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding) 554 { 555 int err; 556 557 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 558 encoding); 559 if (err < 0) 560 return err; 561 562 return 0; 563 } 564 565 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, 566 u8 pattern) 567 { 568 u8 tp = pattern & DP_TRAINING_PATTERN_MASK; 569 u8 status[DP_LINK_STATUS_SIZE], values[4]; 570 unsigned int i; 571 int err; 572 573 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern); 574 if (err < 0) 575 return err; 576 577 if (tp == DP_TRAINING_PATTERN_DISABLE) 578 return 0; 579 580 for (i = 0; i < link->num_lanes; i++) 581 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | 582 DP_TRAIN_PRE_EMPH_LEVEL_0 | 583 DP_TRAIN_MAX_SWING_REACHED | 584 DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 585 586 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values, 587 link->num_lanes); 588 if (err < 0) 589 return err; 590 591 usleep_range(500, 1000); 592 593 err = drm_dp_dpcd_read_link_status(&dpaux->aux, status); 594 if (err < 0) 595 return err; 596 597 switch (tp) { 598 case DP_TRAINING_PATTERN_1: 599 if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) 600 return -EAGAIN; 601 602 break; 603 604 case DP_TRAINING_PATTERN_2: 605 if (!drm_dp_channel_eq_ok(status, link->num_lanes)) 606 return -EAGAIN; 607 608 break; 609 610 default: 611 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp); 612 return -EINVAL; 613 } 614 615 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0); 616 if (err < 0) 617 return err; 618 619 return 0; 620 } 621