1 /* 2 * Copyright (C) 2013 NVIDIA Corporation 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/gpio.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/of_gpio.h> 15 #include <linux/platform_device.h> 16 #include <linux/reset.h> 17 #include <linux/regulator/consumer.h> 18 19 #include <drm/drm_dp_helper.h> 20 #include <drm/drm_panel.h> 21 22 #include "dpaux.h" 23 #include "drm.h" 24 25 static DEFINE_MUTEX(dpaux_lock); 26 static LIST_HEAD(dpaux_list); 27 28 struct tegra_dpaux { 29 struct drm_dp_aux aux; 30 struct device *dev; 31 32 void __iomem *regs; 33 int irq; 34 35 struct tegra_output *output; 36 37 struct reset_control *rst; 38 struct clk *clk_parent; 39 struct clk *clk; 40 41 struct regulator *vdd; 42 43 struct completion complete; 44 struct list_head list; 45 }; 46 47 static inline struct tegra_dpaux *to_dpaux(struct drm_dp_aux *aux) 48 { 49 return container_of(aux, struct tegra_dpaux, aux); 50 } 51 52 static inline unsigned long tegra_dpaux_readl(struct tegra_dpaux *dpaux, 53 unsigned long offset) 54 { 55 return readl(dpaux->regs + (offset << 2)); 56 } 57 58 static inline void tegra_dpaux_writel(struct tegra_dpaux *dpaux, 59 unsigned long value, 60 unsigned long offset) 61 { 62 writel(value, dpaux->regs + (offset << 2)); 63 } 64 65 static void tegra_dpaux_write_fifo(struct tegra_dpaux *dpaux, const u8 *buffer, 66 size_t size) 67 { 68 unsigned long offset = DPAUX_DP_AUXDATA_WRITE(0); 69 size_t i, j; 70 71 for (i = 0; i < size; i += 4) { 72 size_t num = min_t(size_t, size - i, 4); 73 unsigned long value = 0; 74 75 for (j = 0; j < num; j++) 76 value |= buffer[i + j] << (j * 8); 77 78 tegra_dpaux_writel(dpaux, value, offset++); 79 } 80 } 81 82 static void tegra_dpaux_read_fifo(struct tegra_dpaux *dpaux, u8 *buffer, 83 size_t size) 84 { 85 unsigned long offset = DPAUX_DP_AUXDATA_READ(0); 86 size_t i, j; 87 88 for (i = 0; i < size; i += 4) { 89 size_t num = min_t(size_t, size - i, 4); 90 unsigned long value; 91 92 value = tegra_dpaux_readl(dpaux, offset++); 93 94 for (j = 0; j < num; j++) 95 buffer[i + j] = value >> (j * 8); 96 } 97 } 98 99 static ssize_t tegra_dpaux_transfer(struct drm_dp_aux *aux, 100 struct drm_dp_aux_msg *msg) 101 { 102 unsigned long value = DPAUX_DP_AUXCTL_TRANSACTREQ; 103 unsigned long timeout = msecs_to_jiffies(250); 104 struct tegra_dpaux *dpaux = to_dpaux(aux); 105 unsigned long status; 106 ssize_t ret = 0; 107 108 if (msg->size < 1 || msg->size > 16) 109 return -EINVAL; 110 111 tegra_dpaux_writel(dpaux, msg->address, DPAUX_DP_AUXADDR); 112 113 switch (msg->request & ~DP_AUX_I2C_MOT) { 114 case DP_AUX_I2C_WRITE: 115 if (msg->request & DP_AUX_I2C_MOT) 116 value = DPAUX_DP_AUXCTL_CMD_MOT_WR; 117 else 118 value = DPAUX_DP_AUXCTL_CMD_I2C_WR; 119 120 break; 121 122 case DP_AUX_I2C_READ: 123 if (msg->request & DP_AUX_I2C_MOT) 124 value = DPAUX_DP_AUXCTL_CMD_MOT_RD; 125 else 126 value = DPAUX_DP_AUXCTL_CMD_I2C_RD; 127 128 break; 129 130 case DP_AUX_I2C_STATUS: 131 if (msg->request & DP_AUX_I2C_MOT) 132 value = DPAUX_DP_AUXCTL_CMD_MOT_RQ; 133 else 134 value = DPAUX_DP_AUXCTL_CMD_I2C_RQ; 135 136 break; 137 138 case DP_AUX_NATIVE_WRITE: 139 value = DPAUX_DP_AUXCTL_CMD_AUX_WR; 140 break; 141 142 case DP_AUX_NATIVE_READ: 143 value = DPAUX_DP_AUXCTL_CMD_AUX_RD; 144 break; 145 146 default: 147 return -EINVAL; 148 } 149 150 value |= DPAUX_DP_AUXCTL_CMDLEN(msg->size - 1); 151 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); 152 153 if ((msg->request & DP_AUX_I2C_READ) == 0) { 154 tegra_dpaux_write_fifo(dpaux, msg->buffer, msg->size); 155 ret = msg->size; 156 } 157 158 /* start transaction */ 159 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXCTL); 160 value |= DPAUX_DP_AUXCTL_TRANSACTREQ; 161 tegra_dpaux_writel(dpaux, value, DPAUX_DP_AUXCTL); 162 163 status = wait_for_completion_timeout(&dpaux->complete, timeout); 164 if (!status) 165 return -ETIMEDOUT; 166 167 /* read status and clear errors */ 168 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); 169 tegra_dpaux_writel(dpaux, 0xf00, DPAUX_DP_AUXSTAT); 170 171 if (value & DPAUX_DP_AUXSTAT_TIMEOUT_ERROR) 172 return -ETIMEDOUT; 173 174 if ((value & DPAUX_DP_AUXSTAT_RX_ERROR) || 175 (value & DPAUX_DP_AUXSTAT_SINKSTAT_ERROR) || 176 (value & DPAUX_DP_AUXSTAT_NO_STOP_ERROR)) 177 return -EIO; 178 179 switch ((value & DPAUX_DP_AUXSTAT_REPLY_TYPE_MASK) >> 16) { 180 case 0x00: 181 msg->reply = DP_AUX_NATIVE_REPLY_ACK; 182 break; 183 184 case 0x01: 185 msg->reply = DP_AUX_NATIVE_REPLY_NACK; 186 break; 187 188 case 0x02: 189 msg->reply = DP_AUX_NATIVE_REPLY_DEFER; 190 break; 191 192 case 0x04: 193 msg->reply = DP_AUX_I2C_REPLY_NACK; 194 break; 195 196 case 0x08: 197 msg->reply = DP_AUX_I2C_REPLY_DEFER; 198 break; 199 } 200 201 if (msg->reply == DP_AUX_NATIVE_REPLY_ACK) { 202 if (msg->request & DP_AUX_I2C_READ) { 203 size_t count = value & DPAUX_DP_AUXSTAT_REPLY_MASK; 204 205 if (WARN_ON(count != msg->size)) 206 count = min_t(size_t, count, msg->size); 207 208 tegra_dpaux_read_fifo(dpaux, msg->buffer, count); 209 ret = count; 210 } 211 } 212 213 return ret; 214 } 215 216 static irqreturn_t tegra_dpaux_irq(int irq, void *data) 217 { 218 struct tegra_dpaux *dpaux = data; 219 irqreturn_t ret = IRQ_HANDLED; 220 unsigned long value; 221 222 /* clear interrupts */ 223 value = tegra_dpaux_readl(dpaux, DPAUX_INTR_AUX); 224 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 225 226 if (value & DPAUX_INTR_PLUG_EVENT) { 227 if (dpaux->output) { 228 drm_helper_hpd_irq_event(dpaux->output->connector.dev); 229 } 230 } 231 232 if (value & DPAUX_INTR_UNPLUG_EVENT) { 233 if (dpaux->output) 234 drm_helper_hpd_irq_event(dpaux->output->connector.dev); 235 } 236 237 if (value & DPAUX_INTR_IRQ_EVENT) { 238 /* TODO: handle this */ 239 } 240 241 if (value & DPAUX_INTR_AUX_DONE) 242 complete(&dpaux->complete); 243 244 return ret; 245 } 246 247 static int tegra_dpaux_probe(struct platform_device *pdev) 248 { 249 struct tegra_dpaux *dpaux; 250 struct resource *regs; 251 unsigned long value; 252 int err; 253 254 dpaux = devm_kzalloc(&pdev->dev, sizeof(*dpaux), GFP_KERNEL); 255 if (!dpaux) 256 return -ENOMEM; 257 258 init_completion(&dpaux->complete); 259 INIT_LIST_HEAD(&dpaux->list); 260 dpaux->dev = &pdev->dev; 261 262 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 263 dpaux->regs = devm_ioremap_resource(&pdev->dev, regs); 264 if (IS_ERR(dpaux->regs)) 265 return PTR_ERR(dpaux->regs); 266 267 dpaux->irq = platform_get_irq(pdev, 0); 268 if (dpaux->irq < 0) { 269 dev_err(&pdev->dev, "failed to get IRQ\n"); 270 return -ENXIO; 271 } 272 273 dpaux->rst = devm_reset_control_get(&pdev->dev, "dpaux"); 274 if (IS_ERR(dpaux->rst)) 275 return PTR_ERR(dpaux->rst); 276 277 dpaux->clk = devm_clk_get(&pdev->dev, NULL); 278 if (IS_ERR(dpaux->clk)) 279 return PTR_ERR(dpaux->clk); 280 281 err = clk_prepare_enable(dpaux->clk); 282 if (err < 0) 283 return err; 284 285 reset_control_deassert(dpaux->rst); 286 287 dpaux->clk_parent = devm_clk_get(&pdev->dev, "parent"); 288 if (IS_ERR(dpaux->clk_parent)) 289 return PTR_ERR(dpaux->clk_parent); 290 291 err = clk_prepare_enable(dpaux->clk_parent); 292 if (err < 0) 293 return err; 294 295 err = clk_set_rate(dpaux->clk_parent, 270000000); 296 if (err < 0) { 297 dev_err(&pdev->dev, "failed to set clock to 270 MHz: %d\n", 298 err); 299 return err; 300 } 301 302 dpaux->vdd = devm_regulator_get(&pdev->dev, "vdd"); 303 if (IS_ERR(dpaux->vdd)) 304 return PTR_ERR(dpaux->vdd); 305 306 err = devm_request_irq(dpaux->dev, dpaux->irq, tegra_dpaux_irq, 0, 307 dev_name(dpaux->dev), dpaux); 308 if (err < 0) { 309 dev_err(dpaux->dev, "failed to request IRQ#%u: %d\n", 310 dpaux->irq, err); 311 return err; 312 } 313 314 dpaux->aux.transfer = tegra_dpaux_transfer; 315 dpaux->aux.dev = &pdev->dev; 316 317 err = drm_dp_aux_register_i2c_bus(&dpaux->aux); 318 if (err < 0) 319 return err; 320 321 /* enable and clear all interrupts */ 322 value = DPAUX_INTR_AUX_DONE | DPAUX_INTR_IRQ_EVENT | 323 DPAUX_INTR_UNPLUG_EVENT | DPAUX_INTR_PLUG_EVENT; 324 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_EN_AUX); 325 tegra_dpaux_writel(dpaux, value, DPAUX_INTR_AUX); 326 327 mutex_lock(&dpaux_lock); 328 list_add_tail(&dpaux->list, &dpaux_list); 329 mutex_unlock(&dpaux_lock); 330 331 platform_set_drvdata(pdev, dpaux); 332 333 return 0; 334 } 335 336 static int tegra_dpaux_remove(struct platform_device *pdev) 337 { 338 struct tegra_dpaux *dpaux = platform_get_drvdata(pdev); 339 340 drm_dp_aux_unregister_i2c_bus(&dpaux->aux); 341 342 mutex_lock(&dpaux_lock); 343 list_del(&dpaux->list); 344 mutex_unlock(&dpaux_lock); 345 346 clk_disable_unprepare(dpaux->clk_parent); 347 reset_control_assert(dpaux->rst); 348 clk_disable_unprepare(dpaux->clk); 349 350 return 0; 351 } 352 353 static const struct of_device_id tegra_dpaux_of_match[] = { 354 { .compatible = "nvidia,tegra124-dpaux", }, 355 { }, 356 }; 357 358 struct platform_driver tegra_dpaux_driver = { 359 .driver = { 360 .name = "tegra-dpaux", 361 .of_match_table = tegra_dpaux_of_match, 362 }, 363 .probe = tegra_dpaux_probe, 364 .remove = tegra_dpaux_remove, 365 }; 366 367 struct tegra_dpaux *tegra_dpaux_find_by_of_node(struct device_node *np) 368 { 369 struct tegra_dpaux *dpaux; 370 371 mutex_lock(&dpaux_lock); 372 373 list_for_each_entry(dpaux, &dpaux_list, list) 374 if (np == dpaux->dev->of_node) { 375 mutex_unlock(&dpaux_lock); 376 return dpaux; 377 } 378 379 mutex_unlock(&dpaux_lock); 380 381 return NULL; 382 } 383 384 int tegra_dpaux_attach(struct tegra_dpaux *dpaux, struct tegra_output *output) 385 { 386 unsigned long timeout; 387 int err; 388 389 dpaux->output = output; 390 391 err = regulator_enable(dpaux->vdd); 392 if (err < 0) 393 return err; 394 395 timeout = jiffies + msecs_to_jiffies(250); 396 397 while (time_before(jiffies, timeout)) { 398 enum drm_connector_status status; 399 400 status = tegra_dpaux_detect(dpaux); 401 if (status == connector_status_connected) 402 return 0; 403 404 usleep_range(1000, 2000); 405 } 406 407 return -ETIMEDOUT; 408 } 409 410 int tegra_dpaux_detach(struct tegra_dpaux *dpaux) 411 { 412 unsigned long timeout; 413 int err; 414 415 err = regulator_disable(dpaux->vdd); 416 if (err < 0) 417 return err; 418 419 timeout = jiffies + msecs_to_jiffies(250); 420 421 while (time_before(jiffies, timeout)) { 422 enum drm_connector_status status; 423 424 status = tegra_dpaux_detect(dpaux); 425 if (status == connector_status_disconnected) { 426 dpaux->output = NULL; 427 return 0; 428 } 429 430 usleep_range(1000, 2000); 431 } 432 433 return -ETIMEDOUT; 434 } 435 436 enum drm_connector_status tegra_dpaux_detect(struct tegra_dpaux *dpaux) 437 { 438 unsigned long value; 439 440 value = tegra_dpaux_readl(dpaux, DPAUX_DP_AUXSTAT); 441 442 if (value & DPAUX_DP_AUXSTAT_HPD_STATUS) 443 return connector_status_connected; 444 445 return connector_status_disconnected; 446 } 447 448 int tegra_dpaux_enable(struct tegra_dpaux *dpaux) 449 { 450 unsigned long value; 451 452 value = DPAUX_HYBRID_PADCTL_AUX_CMH(2) | 453 DPAUX_HYBRID_PADCTL_AUX_DRVZ(4) | 454 DPAUX_HYBRID_PADCTL_AUX_DRVI(0x18) | 455 DPAUX_HYBRID_PADCTL_AUX_INPUT_RCV | 456 DPAUX_HYBRID_PADCTL_MODE_AUX; 457 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_PADCTL); 458 459 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 460 value &= ~DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 461 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 462 463 return 0; 464 } 465 466 int tegra_dpaux_disable(struct tegra_dpaux *dpaux) 467 { 468 unsigned long value; 469 470 value = tegra_dpaux_readl(dpaux, DPAUX_HYBRID_SPARE); 471 value |= DPAUX_HYBRID_SPARE_PAD_POWER_DOWN; 472 tegra_dpaux_writel(dpaux, value, DPAUX_HYBRID_SPARE); 473 474 return 0; 475 } 476 477 int tegra_dpaux_prepare(struct tegra_dpaux *dpaux, u8 encoding) 478 { 479 int err; 480 481 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_MAIN_LINK_CHANNEL_CODING_SET, 482 encoding); 483 if (err < 0) 484 return err; 485 486 return 0; 487 } 488 489 int tegra_dpaux_train(struct tegra_dpaux *dpaux, struct drm_dp_link *link, 490 u8 pattern) 491 { 492 u8 tp = pattern & DP_TRAINING_PATTERN_MASK; 493 u8 status[DP_LINK_STATUS_SIZE], values[4]; 494 unsigned int i; 495 int err; 496 497 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_TRAINING_PATTERN_SET, pattern); 498 if (err < 0) 499 return err; 500 501 if (tp == DP_TRAINING_PATTERN_DISABLE) 502 return 0; 503 504 for (i = 0; i < link->num_lanes; i++) 505 values[i] = DP_TRAIN_MAX_PRE_EMPHASIS_REACHED | 506 DP_TRAIN_PRE_EMPHASIS_0 | 507 DP_TRAIN_MAX_SWING_REACHED | 508 DP_TRAIN_VOLTAGE_SWING_400; 509 510 err = drm_dp_dpcd_write(&dpaux->aux, DP_TRAINING_LANE0_SET, values, 511 link->num_lanes); 512 if (err < 0) 513 return err; 514 515 usleep_range(500, 1000); 516 517 err = drm_dp_dpcd_read_link_status(&dpaux->aux, status); 518 if (err < 0) 519 return err; 520 521 switch (tp) { 522 case DP_TRAINING_PATTERN_1: 523 if (!drm_dp_clock_recovery_ok(status, link->num_lanes)) 524 return -EAGAIN; 525 526 break; 527 528 case DP_TRAINING_PATTERN_2: 529 if (!drm_dp_channel_eq_ok(status, link->num_lanes)) 530 return -EAGAIN; 531 532 break; 533 534 default: 535 dev_err(dpaux->dev, "unsupported training pattern %u\n", tp); 536 return -EINVAL; 537 } 538 539 err = drm_dp_dpcd_writeb(&dpaux->aux, DP_EDP_CONFIGURATION_SET, 0); 540 if (err < 0) 541 return err; 542 543 return 0; 544 } 545