1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #ifndef TEGRA_DC_H 11 #define TEGRA_DC_H 1 12 13 #include <linux/host1x.h> 14 15 #include <drm/drm_crtc.h> 16 17 #include "drm.h" 18 19 struct tegra_output; 20 21 struct tegra_dc_stats { 22 unsigned long frames; 23 unsigned long vblank; 24 unsigned long underflow; 25 unsigned long overflow; 26 }; 27 28 struct tegra_dc_soc_info { 29 bool supports_border_color; 30 bool supports_interlacing; 31 bool supports_cursor; 32 bool supports_block_linear; 33 unsigned int pitch_align; 34 bool has_powergate; 35 bool broken_reset; 36 }; 37 38 struct tegra_dc { 39 struct host1x_client client; 40 struct host1x_syncpt *syncpt; 41 struct device *dev; 42 spinlock_t lock; 43 44 struct drm_crtc base; 45 unsigned int powergate; 46 int pipe; 47 48 struct clk *clk; 49 struct reset_control *rst; 50 void __iomem *regs; 51 int irq; 52 53 struct tegra_output *rgb; 54 55 struct tegra_dc_stats stats; 56 struct list_head list; 57 58 struct drm_info_list *debugfs_files; 59 struct drm_minor *minor; 60 struct dentry *debugfs; 61 62 /* page-flip handling */ 63 struct drm_pending_vblank_event *event; 64 65 const struct tegra_dc_soc_info *soc; 66 67 struct iommu_domain *domain; 68 }; 69 70 static inline struct tegra_dc * 71 host1x_client_to_dc(struct host1x_client *client) 72 { 73 return container_of(client, struct tegra_dc, client); 74 } 75 76 static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) 77 { 78 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; 79 } 80 81 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, 82 unsigned int offset) 83 { 84 trace_dc_writel(dc->dev, offset, value); 85 writel(value, dc->regs + (offset << 2)); 86 } 87 88 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) 89 { 90 u32 value = readl(dc->regs + (offset << 2)); 91 92 trace_dc_readl(dc->dev, offset, value); 93 94 return value; 95 } 96 97 struct tegra_dc_window { 98 struct { 99 unsigned int x; 100 unsigned int y; 101 unsigned int w; 102 unsigned int h; 103 } src; 104 struct { 105 unsigned int x; 106 unsigned int y; 107 unsigned int w; 108 unsigned int h; 109 } dst; 110 unsigned int bits_per_pixel; 111 unsigned int stride[2]; 112 unsigned long base[3]; 113 bool bottom_up; 114 115 struct tegra_bo_tiling tiling; 116 u32 format; 117 u32 swap; 118 }; 119 120 /* from dc.c */ 121 void tegra_dc_commit(struct tegra_dc *dc); 122 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 123 struct drm_crtc_state *crtc_state, 124 struct clk *clk, unsigned long pclk, 125 unsigned int div); 126 127 /* from rgb.c */ 128 int tegra_dc_rgb_probe(struct tegra_dc *dc); 129 int tegra_dc_rgb_remove(struct tegra_dc *dc); 130 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); 131 int tegra_dc_rgb_exit(struct tegra_dc *dc); 132 133 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 134 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 135 #define SYNCPT_CNTRL_NO_STALL (1 << 8) 136 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 137 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 138 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 139 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 140 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 141 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 142 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 143 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 144 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 145 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 146 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 147 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 148 #define SYNCPT_VSYNC_ENABLE (1 << 8) 149 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 150 #define DC_CMD_DISPLAY_COMMAND 0x032 151 #define DISP_CTRL_MODE_STOP (0 << 5) 152 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 153 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 154 #define DISP_CTRL_MODE_MASK (3 << 5) 155 #define DC_CMD_SIGNAL_RAISE 0x033 156 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 157 #define PW0_ENABLE (1 << 0) 158 #define PW1_ENABLE (1 << 2) 159 #define PW2_ENABLE (1 << 4) 160 #define PW3_ENABLE (1 << 6) 161 #define PW4_ENABLE (1 << 8) 162 #define PM0_ENABLE (1 << 16) 163 #define PM1_ENABLE (1 << 18) 164 165 #define DC_CMD_INT_STATUS 0x037 166 #define DC_CMD_INT_MASK 0x038 167 #define DC_CMD_INT_ENABLE 0x039 168 #define DC_CMD_INT_TYPE 0x03a 169 #define DC_CMD_INT_POLARITY 0x03b 170 #define CTXSW_INT (1 << 0) 171 #define FRAME_END_INT (1 << 1) 172 #define VBLANK_INT (1 << 2) 173 #define WIN_A_UF_INT (1 << 8) 174 #define WIN_B_UF_INT (1 << 9) 175 #define WIN_C_UF_INT (1 << 10) 176 #define WIN_A_OF_INT (1 << 14) 177 #define WIN_B_OF_INT (1 << 15) 178 #define WIN_C_OF_INT (1 << 16) 179 180 #define DC_CMD_SIGNAL_RAISE1 0x03c 181 #define DC_CMD_SIGNAL_RAISE2 0x03d 182 #define DC_CMD_SIGNAL_RAISE3 0x03e 183 184 #define DC_CMD_STATE_ACCESS 0x040 185 #define READ_MUX (1 << 0) 186 #define WRITE_MUX (1 << 2) 187 188 #define DC_CMD_STATE_CONTROL 0x041 189 #define GENERAL_ACT_REQ (1 << 0) 190 #define WIN_A_ACT_REQ (1 << 1) 191 #define WIN_B_ACT_REQ (1 << 2) 192 #define WIN_C_ACT_REQ (1 << 3) 193 #define CURSOR_ACT_REQ (1 << 7) 194 #define GENERAL_UPDATE (1 << 8) 195 #define WIN_A_UPDATE (1 << 9) 196 #define WIN_B_UPDATE (1 << 10) 197 #define WIN_C_UPDATE (1 << 11) 198 #define CURSOR_UPDATE (1 << 15) 199 #define NC_HOST_TRIG (1 << 24) 200 201 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 202 #define WINDOW_A_SELECT (1 << 4) 203 #define WINDOW_B_SELECT (1 << 5) 204 #define WINDOW_C_SELECT (1 << 6) 205 206 #define DC_CMD_REG_ACT_CONTROL 0x043 207 208 #define DC_COM_CRC_CONTROL 0x300 209 #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) 210 #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) 211 #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) 212 #define DC_COM_CRC_CONTROL_WAIT (1 << 1) 213 #define DC_COM_CRC_CONTROL_ENABLE (1 << 0) 214 #define DC_COM_CRC_CHECKSUM 0x301 215 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) 216 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) 217 #define LVS_OUTPUT_POLARITY_LOW (1 << 28) 218 #define LHS_OUTPUT_POLARITY_LOW (1 << 30) 219 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) 220 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) 221 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) 222 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) 223 224 #define DC_COM_PIN_MISC_CONTROL 0x31b 225 #define DC_COM_PIN_PM0_CONTROL 0x31c 226 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d 227 #define DC_COM_PIN_PM1_CONTROL 0x31e 228 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f 229 230 #define DC_COM_SPI_CONTROL 0x320 231 #define DC_COM_SPI_START_BYTE 0x321 232 #define DC_COM_HSPI_WRITE_DATA_AB 0x322 233 #define DC_COM_HSPI_WRITE_DATA_CD 0x323 234 #define DC_COM_HSPI_CS_DC 0x324 235 #define DC_COM_SCRATCH_REGISTER_A 0x325 236 #define DC_COM_SCRATCH_REGISTER_B 0x326 237 #define DC_COM_GPIO_CTRL 0x327 238 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 239 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 240 241 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 242 #define H_PULSE0_ENABLE (1 << 8) 243 #define H_PULSE1_ENABLE (1 << 10) 244 #define H_PULSE2_ENABLE (1 << 12) 245 246 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 247 248 #define DC_DISP_DISP_WIN_OPTIONS 0x402 249 #define HDMI_ENABLE (1 << 30) 250 #define DSI_ENABLE (1 << 29) 251 #define SOR1_TIMING_CYA (1 << 27) 252 #define SOR1_ENABLE (1 << 26) 253 #define SOR_ENABLE (1 << 25) 254 #define CURSOR_ENABLE (1 << 16) 255 256 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 257 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 258 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 259 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) 260 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) 261 262 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 263 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24) 264 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) 265 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) 266 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) 267 268 #define DC_DISP_DISP_TIMING_OPTIONS 0x405 269 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 270 271 #define DC_DISP_REF_TO_SYNC 0x406 272 #define DC_DISP_SYNC_WIDTH 0x407 273 #define DC_DISP_BACK_PORCH 0x408 274 #define DC_DISP_ACTIVE 0x409 275 #define DC_DISP_FRONT_PORCH 0x40a 276 #define DC_DISP_H_PULSE0_CONTROL 0x40b 277 #define DC_DISP_H_PULSE0_POSITION_A 0x40c 278 #define DC_DISP_H_PULSE0_POSITION_B 0x40d 279 #define DC_DISP_H_PULSE0_POSITION_C 0x40e 280 #define DC_DISP_H_PULSE0_POSITION_D 0x40f 281 #define DC_DISP_H_PULSE1_CONTROL 0x410 282 #define DC_DISP_H_PULSE1_POSITION_A 0x411 283 #define DC_DISP_H_PULSE1_POSITION_B 0x412 284 #define DC_DISP_H_PULSE1_POSITION_C 0x413 285 #define DC_DISP_H_PULSE1_POSITION_D 0x414 286 #define DC_DISP_H_PULSE2_CONTROL 0x415 287 #define DC_DISP_H_PULSE2_POSITION_A 0x416 288 #define DC_DISP_H_PULSE2_POSITION_B 0x417 289 #define DC_DISP_H_PULSE2_POSITION_C 0x418 290 #define DC_DISP_H_PULSE2_POSITION_D 0x419 291 #define DC_DISP_V_PULSE0_CONTROL 0x41a 292 #define DC_DISP_V_PULSE0_POSITION_A 0x41b 293 #define DC_DISP_V_PULSE0_POSITION_B 0x41c 294 #define DC_DISP_V_PULSE0_POSITION_C 0x41d 295 #define DC_DISP_V_PULSE1_CONTROL 0x41e 296 #define DC_DISP_V_PULSE1_POSITION_A 0x41f 297 #define DC_DISP_V_PULSE1_POSITION_B 0x420 298 #define DC_DISP_V_PULSE1_POSITION_C 0x421 299 #define DC_DISP_V_PULSE2_CONTROL 0x422 300 #define DC_DISP_V_PULSE2_POSITION_A 0x423 301 #define DC_DISP_V_PULSE3_CONTROL 0x424 302 #define DC_DISP_V_PULSE3_POSITION_A 0x425 303 #define DC_DISP_M0_CONTROL 0x426 304 #define DC_DISP_M1_CONTROL 0x427 305 #define DC_DISP_DI_CONTROL 0x428 306 #define DC_DISP_PP_CONTROL 0x429 307 #define DC_DISP_PP_SELECT_A 0x42a 308 #define DC_DISP_PP_SELECT_B 0x42b 309 #define DC_DISP_PP_SELECT_C 0x42c 310 #define DC_DISP_PP_SELECT_D 0x42d 311 312 #define PULSE_MODE_NORMAL (0 << 3) 313 #define PULSE_MODE_ONE_CLOCK (1 << 3) 314 #define PULSE_POLARITY_HIGH (0 << 4) 315 #define PULSE_POLARITY_LOW (1 << 4) 316 #define PULSE_QUAL_ALWAYS (0 << 6) 317 #define PULSE_QUAL_VACTIVE (2 << 6) 318 #define PULSE_QUAL_VACTIVE1 (3 << 6) 319 #define PULSE_LAST_START_A (0 << 8) 320 #define PULSE_LAST_END_A (1 << 8) 321 #define PULSE_LAST_START_B (2 << 8) 322 #define PULSE_LAST_END_B (3 << 8) 323 #define PULSE_LAST_START_C (4 << 8) 324 #define PULSE_LAST_END_C (5 << 8) 325 #define PULSE_LAST_START_D (6 << 8) 326 #define PULSE_LAST_END_D (7 << 8) 327 328 #define PULSE_START(x) (((x) & 0xfff) << 0) 329 #define PULSE_END(x) (((x) & 0xfff) << 16) 330 331 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e 332 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) 333 #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) 334 #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) 335 #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) 336 #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) 337 #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) 338 #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) 339 #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) 340 #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) 341 #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) 342 #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) 343 #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) 344 #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) 345 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 346 347 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 348 #define DISP_DATA_FORMAT_DF1P1C (0 << 0) 349 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) 350 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) 351 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) 352 #define DISP_DATA_FORMAT_DF2S (4 << 0) 353 #define DISP_DATA_FORMAT_DF3S (5 << 0) 354 #define DISP_DATA_FORMAT_DFSPI (6 << 0) 355 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) 356 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) 357 #define DISP_ALIGNMENT_MSB (0 << 8) 358 #define DISP_ALIGNMENT_LSB (1 << 8) 359 #define DISP_ORDER_RED_BLUE (0 << 9) 360 #define DISP_ORDER_BLUE_RED (1 << 9) 361 362 #define DC_DISP_DISP_COLOR_CONTROL 0x430 363 #define BASE_COLOR_SIZE666 (0 << 0) 364 #define BASE_COLOR_SIZE111 (1 << 0) 365 #define BASE_COLOR_SIZE222 (2 << 0) 366 #define BASE_COLOR_SIZE333 (3 << 0) 367 #define BASE_COLOR_SIZE444 (4 << 0) 368 #define BASE_COLOR_SIZE555 (5 << 0) 369 #define BASE_COLOR_SIZE565 (6 << 0) 370 #define BASE_COLOR_SIZE332 (7 << 0) 371 #define BASE_COLOR_SIZE888 (8 << 0) 372 #define DITHER_CONTROL_MASK (3 << 8) 373 #define DITHER_CONTROL_DISABLE (0 << 8) 374 #define DITHER_CONTROL_ORDERED (2 << 8) 375 #define DITHER_CONTROL_ERRDIFF (3 << 8) 376 #define BASE_COLOR_SIZE_MASK (0xf << 0) 377 #define BASE_COLOR_SIZE_666 (0 << 0) 378 #define BASE_COLOR_SIZE_111 (1 << 0) 379 #define BASE_COLOR_SIZE_222 (2 << 0) 380 #define BASE_COLOR_SIZE_333 (3 << 0) 381 #define BASE_COLOR_SIZE_444 (4 << 0) 382 #define BASE_COLOR_SIZE_555 (5 << 0) 383 #define BASE_COLOR_SIZE_565 (6 << 0) 384 #define BASE_COLOR_SIZE_332 (7 << 0) 385 #define BASE_COLOR_SIZE_888 (8 << 0) 386 387 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 388 #define SC1_H_QUALIFIER_NONE (1 << 16) 389 #define SC0_H_QUALIFIER_NONE (1 << 0) 390 391 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432 392 #define DE_SELECT_ACTIVE_BLANK (0 << 0) 393 #define DE_SELECT_ACTIVE (1 << 0) 394 #define DE_SELECT_ACTIVE_IS (2 << 0) 395 #define DE_CONTROL_ONECLK (0 << 2) 396 #define DE_CONTROL_NORMAL (1 << 2) 397 #define DE_CONTROL_EARLY_EXT (2 << 2) 398 #define DE_CONTROL_EARLY (3 << 2) 399 #define DE_CONTROL_ACTIVE_BLANK (4 << 2) 400 401 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 402 #define DC_DISP_LCD_SPI_OPTIONS 0x434 403 #define DC_DISP_BORDER_COLOR 0x435 404 #define DC_DISP_COLOR_KEY0_LOWER 0x436 405 #define DC_DISP_COLOR_KEY0_UPPER 0x437 406 #define DC_DISP_COLOR_KEY1_LOWER 0x438 407 #define DC_DISP_COLOR_KEY1_UPPER 0x439 408 409 #define DC_DISP_CURSOR_FOREGROUND 0x43c 410 #define DC_DISP_CURSOR_BACKGROUND 0x43d 411 412 #define DC_DISP_CURSOR_START_ADDR 0x43e 413 #define CURSOR_CLIP_DISPLAY (0 << 28) 414 #define CURSOR_CLIP_WIN_A (1 << 28) 415 #define CURSOR_CLIP_WIN_B (2 << 28) 416 #define CURSOR_CLIP_WIN_C (3 << 28) 417 #define CURSOR_SIZE_32x32 (0 << 24) 418 #define CURSOR_SIZE_64x64 (1 << 24) 419 #define CURSOR_SIZE_128x128 (2 << 24) 420 #define CURSOR_SIZE_256x256 (3 << 24) 421 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f 422 423 #define DC_DISP_CURSOR_POSITION 0x440 424 #define DC_DISP_CURSOR_POSITION_NS 0x441 425 426 #define DC_DISP_INIT_SEQ_CONTROL 0x442 427 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 428 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 429 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 430 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 431 432 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 433 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 434 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 435 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 436 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 437 438 #define DC_DISP_DAC_CRT_CTRL 0x4c0 439 #define DC_DISP_DISP_MISC_CONTROL 0x4c1 440 #define DC_DISP_SD_CONTROL 0x4c2 441 #define DC_DISP_SD_CSC_COEFF 0x4c3 442 #define DC_DISP_SD_LUT(x) (0x4c4 + (x)) 443 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd 444 #define DC_DISP_DC_PIXEL_COUNT 0x4ce 445 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) 446 #define DC_DISP_SD_BL_PARAMETERS 0x4d7 447 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) 448 #define DC_DISP_SD_BL_CONTROL 0x4dc 449 #define DC_DISP_SD_HW_K_VALUES 0x4dd 450 #define DC_DISP_SD_MAN_K_VALUES 0x4de 451 452 #define DC_DISP_INTERLACE_CONTROL 0x4e5 453 #define INTERLACE_STATUS (1 << 2) 454 #define INTERLACE_START (1 << 1) 455 #define INTERLACE_ENABLE (1 << 0) 456 457 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec 458 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 459 #define CURSOR_MODE_LEGACY (0 << 24) 460 #define CURSOR_MODE_NORMAL (1 << 24) 461 #define CURSOR_DST_BLEND_ZERO (0 << 16) 462 #define CURSOR_DST_BLEND_K1 (1 << 16) 463 #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) 464 #define CURSOR_DST_BLEND_MASK (3 << 16) 465 #define CURSOR_SRC_BLEND_K1 (0 << 8) 466 #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) 467 #define CURSOR_SRC_BLEND_MASK (3 << 8) 468 #define CURSOR_ALPHA 0xff 469 470 #define DC_WIN_CSC_YOF 0x611 471 #define DC_WIN_CSC_KYRGB 0x612 472 #define DC_WIN_CSC_KUR 0x613 473 #define DC_WIN_CSC_KVR 0x614 474 #define DC_WIN_CSC_KUG 0x615 475 #define DC_WIN_CSC_KVG 0x616 476 #define DC_WIN_CSC_KUB 0x617 477 #define DC_WIN_CSC_KVB 0x618 478 479 #define DC_WIN_WIN_OPTIONS 0x700 480 #define H_DIRECTION (1 << 0) 481 #define V_DIRECTION (1 << 2) 482 #define COLOR_EXPAND (1 << 6) 483 #define CSC_ENABLE (1 << 18) 484 #define WIN_ENABLE (1 << 30) 485 486 #define DC_WIN_BYTE_SWAP 0x701 487 #define BYTE_SWAP_NOSWAP (0 << 0) 488 #define BYTE_SWAP_SWAP2 (1 << 0) 489 #define BYTE_SWAP_SWAP4 (2 << 0) 490 #define BYTE_SWAP_SWAP4HW (3 << 0) 491 492 #define DC_WIN_BUFFER_CONTROL 0x702 493 #define BUFFER_CONTROL_HOST (0 << 0) 494 #define BUFFER_CONTROL_VI (1 << 0) 495 #define BUFFER_CONTROL_EPP (2 << 0) 496 #define BUFFER_CONTROL_MPEGE (3 << 0) 497 #define BUFFER_CONTROL_SB2D (4 << 0) 498 499 #define DC_WIN_COLOR_DEPTH 0x703 500 #define WIN_COLOR_DEPTH_P1 0 501 #define WIN_COLOR_DEPTH_P2 1 502 #define WIN_COLOR_DEPTH_P4 2 503 #define WIN_COLOR_DEPTH_P8 3 504 #define WIN_COLOR_DEPTH_B4G4R4A4 4 505 #define WIN_COLOR_DEPTH_B5G5R5A 5 506 #define WIN_COLOR_DEPTH_B5G6R5 6 507 #define WIN_COLOR_DEPTH_AB5G5R5 7 508 #define WIN_COLOR_DEPTH_B8G8R8A8 12 509 #define WIN_COLOR_DEPTH_R8G8B8A8 13 510 #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 511 #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 512 #define WIN_COLOR_DEPTH_YCbCr422 16 513 #define WIN_COLOR_DEPTH_YUV422 17 514 #define WIN_COLOR_DEPTH_YCbCr420P 18 515 #define WIN_COLOR_DEPTH_YUV420P 19 516 #define WIN_COLOR_DEPTH_YCbCr422P 20 517 #define WIN_COLOR_DEPTH_YUV422P 21 518 #define WIN_COLOR_DEPTH_YCbCr422R 22 519 #define WIN_COLOR_DEPTH_YUV422R 23 520 #define WIN_COLOR_DEPTH_YCbCr422RA 24 521 #define WIN_COLOR_DEPTH_YUV422RA 25 522 523 #define DC_WIN_POSITION 0x704 524 #define H_POSITION(x) (((x) & 0x1fff) << 0) 525 #define V_POSITION(x) (((x) & 0x1fff) << 16) 526 527 #define DC_WIN_SIZE 0x705 528 #define H_SIZE(x) (((x) & 0x1fff) << 0) 529 #define V_SIZE(x) (((x) & 0x1fff) << 16) 530 531 #define DC_WIN_PRESCALED_SIZE 0x706 532 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 533 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) 534 535 #define DC_WIN_H_INITIAL_DDA 0x707 536 #define DC_WIN_V_INITIAL_DDA 0x708 537 #define DC_WIN_DDA_INC 0x709 538 #define H_DDA_INC(x) (((x) & 0xffff) << 0) 539 #define V_DDA_INC(x) (((x) & 0xffff) << 16) 540 541 #define DC_WIN_LINE_STRIDE 0x70a 542 #define DC_WIN_BUF_STRIDE 0x70b 543 #define DC_WIN_UV_BUF_STRIDE 0x70c 544 #define DC_WIN_BUFFER_ADDR_MODE 0x70d 545 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) 546 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) 547 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) 548 #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) 549 #define DC_WIN_DV_CONTROL 0x70e 550 551 #define DC_WIN_BLEND_NOKEY 0x70f 552 #define DC_WIN_BLEND_1WIN 0x710 553 #define DC_WIN_BLEND_2WIN_X 0x711 554 #define DC_WIN_BLEND_2WIN_Y 0x712 555 #define DC_WIN_BLEND_3WIN_XY 0x713 556 557 #define DC_WIN_HP_FETCH_CONTROL 0x714 558 559 #define DC_WINBUF_START_ADDR 0x800 560 #define DC_WINBUF_START_ADDR_NS 0x801 561 #define DC_WINBUF_START_ADDR_U 0x802 562 #define DC_WINBUF_START_ADDR_U_NS 0x803 563 #define DC_WINBUF_START_ADDR_V 0x804 564 #define DC_WINBUF_START_ADDR_V_NS 0x805 565 566 #define DC_WINBUF_ADDR_H_OFFSET 0x806 567 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 568 #define DC_WINBUF_ADDR_V_OFFSET 0x808 569 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 570 571 #define DC_WINBUF_UFLOW_STATUS 0x80a 572 #define DC_WINBUF_SURFACE_KIND 0x80b 573 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) 574 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) 575 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) 576 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 577 578 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca 579 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca 580 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca 581 582 #endif /* TEGRA_DC_H */ 583