1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #ifndef TEGRA_DC_H 8 #define TEGRA_DC_H 1 9 10 #include <linux/host1x.h> 11 12 #include <drm/drm_crtc.h> 13 14 #include "drm.h" 15 16 struct tegra_output; 17 18 #define TEGRA_DC_LEGACY_PLANES_NUM 7 19 20 struct tegra_dc_state { 21 struct drm_crtc_state base; 22 23 struct clk *clk; 24 unsigned long pclk; 25 unsigned int div; 26 27 u32 planes; 28 }; 29 30 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) 31 { 32 if (state) 33 return container_of(state, struct tegra_dc_state, base); 34 35 return NULL; 36 } 37 38 static inline const struct tegra_dc_state * 39 to_const_dc_state(const struct drm_crtc_state *state) 40 { 41 return to_dc_state((struct drm_crtc_state *)state); 42 } 43 44 struct tegra_dc_stats { 45 unsigned long frames; 46 unsigned long vblank; 47 unsigned long underflow; 48 unsigned long overflow; 49 50 unsigned long frames_total; 51 unsigned long vblank_total; 52 unsigned long underflow_total; 53 unsigned long overflow_total; 54 }; 55 56 struct tegra_windowgroup_soc { 57 unsigned int index; 58 unsigned int dc; 59 const unsigned int *windows; 60 unsigned int num_windows; 61 }; 62 63 struct tegra_dc_soc_info { 64 bool supports_background_color; 65 bool supports_interlacing; 66 bool supports_cursor; 67 bool supports_block_linear; 68 bool supports_sector_layout; 69 bool has_legacy_blending; 70 unsigned int pitch_align; 71 bool has_powergate; 72 bool coupled_pm; 73 bool has_nvdisplay; 74 const struct tegra_windowgroup_soc *wgrps; 75 unsigned int num_wgrps; 76 const u32 *primary_formats; 77 unsigned int num_primary_formats; 78 const u32 *overlay_formats; 79 unsigned int num_overlay_formats; 80 const u64 *modifiers; 81 bool has_win_a_without_filters; 82 bool has_win_b_vfilter_mem_client; 83 bool has_win_c_without_vert_filter; 84 bool plane_tiled_memory_bandwidth_x2; 85 }; 86 87 struct tegra_dc { 88 struct host1x_client client; 89 struct host1x_syncpt *syncpt; 90 struct device *dev; 91 92 struct drm_crtc base; 93 unsigned int powergate; 94 int pipe; 95 96 struct clk *clk; 97 struct reset_control *rst; 98 void __iomem *regs; 99 int irq; 100 101 struct tegra_output *rgb; 102 103 struct tegra_dc_stats stats; 104 struct list_head list; 105 106 struct drm_info_list *debugfs_files; 107 108 const struct tegra_dc_soc_info *soc; 109 }; 110 111 static inline struct tegra_dc * 112 host1x_client_to_dc(struct host1x_client *client) 113 { 114 return container_of(client, struct tegra_dc, client); 115 } 116 117 static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) 118 { 119 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; 120 } 121 122 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, 123 unsigned int offset) 124 { 125 trace_dc_writel(dc->dev, offset, value); 126 writel(value, dc->regs + (offset << 2)); 127 } 128 129 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) 130 { 131 u32 value = readl(dc->regs + (offset << 2)); 132 133 trace_dc_readl(dc->dev, offset, value); 134 135 return value; 136 } 137 138 struct tegra_dc_window { 139 struct { 140 unsigned int x; 141 unsigned int y; 142 unsigned int w; 143 unsigned int h; 144 } src; 145 struct { 146 unsigned int x; 147 unsigned int y; 148 unsigned int w; 149 unsigned int h; 150 } dst; 151 unsigned int bits_per_pixel; 152 unsigned int stride[2]; 153 unsigned long base[3]; 154 unsigned int zpos; 155 bool reflect_x; 156 bool reflect_y; 157 158 struct tegra_bo_tiling tiling; 159 u32 format; 160 u32 swap; 161 }; 162 163 /* from dc.c */ 164 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev); 165 void tegra_dc_commit(struct tegra_dc *dc); 166 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 167 struct drm_crtc_state *crtc_state, 168 struct clk *clk, unsigned long pclk, 169 unsigned int div); 170 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, 171 struct drm_atomic_state *state); 172 173 /* from rgb.c */ 174 int tegra_dc_rgb_probe(struct tegra_dc *dc); 175 int tegra_dc_rgb_remove(struct tegra_dc *dc); 176 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); 177 int tegra_dc_rgb_exit(struct tegra_dc *dc); 178 179 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 180 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 181 #define SYNCPT_CNTRL_NO_STALL (1 << 8) 182 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 183 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 184 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 185 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 186 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 187 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 188 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 189 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 190 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 191 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 192 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 193 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 194 #define SYNCPT_VSYNC_ENABLE (1 << 8) 195 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 196 #define DC_CMD_DISPLAY_COMMAND 0x032 197 #define DISP_CTRL_MODE_STOP (0 << 5) 198 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 199 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 200 #define DISP_CTRL_MODE_MASK (3 << 5) 201 #define DC_CMD_SIGNAL_RAISE 0x033 202 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 203 #define PW0_ENABLE (1 << 0) 204 #define PW1_ENABLE (1 << 2) 205 #define PW2_ENABLE (1 << 4) 206 #define PW3_ENABLE (1 << 6) 207 #define PW4_ENABLE (1 << 8) 208 #define PM0_ENABLE (1 << 16) 209 #define PM1_ENABLE (1 << 18) 210 211 #define DC_CMD_INT_STATUS 0x037 212 #define DC_CMD_INT_MASK 0x038 213 #define DC_CMD_INT_ENABLE 0x039 214 #define DC_CMD_INT_TYPE 0x03a 215 #define DC_CMD_INT_POLARITY 0x03b 216 #define CTXSW_INT (1 << 0) 217 #define FRAME_END_INT (1 << 1) 218 #define VBLANK_INT (1 << 2) 219 #define V_PULSE3_INT (1 << 4) 220 #define V_PULSE2_INT (1 << 5) 221 #define REGION_CRC_INT (1 << 6) 222 #define REG_TMOUT_INT (1 << 7) 223 #define WIN_A_UF_INT (1 << 8) 224 #define WIN_B_UF_INT (1 << 9) 225 #define WIN_C_UF_INT (1 << 10) 226 #define MSF_INT (1 << 12) 227 #define WIN_A_OF_INT (1 << 14) 228 #define WIN_B_OF_INT (1 << 15) 229 #define WIN_C_OF_INT (1 << 16) 230 #define HEAD_UF_INT (1 << 23) 231 #define SD3_BUCKET_WALK_DONE_INT (1 << 24) 232 #define DSC_OBUF_UF_INT (1 << 26) 233 #define DSC_RBUF_UF_INT (1 << 27) 234 #define DSC_BBUF_UF_INT (1 << 28) 235 #define DSC_TO_UF_INT (1 << 29) 236 237 #define DC_CMD_SIGNAL_RAISE1 0x03c 238 #define DC_CMD_SIGNAL_RAISE2 0x03d 239 #define DC_CMD_SIGNAL_RAISE3 0x03e 240 241 #define DC_CMD_STATE_ACCESS 0x040 242 #define READ_MUX (1 << 0) 243 #define WRITE_MUX (1 << 2) 244 245 #define DC_CMD_STATE_CONTROL 0x041 246 #define GENERAL_ACT_REQ (1 << 0) 247 #define WIN_A_ACT_REQ (1 << 1) 248 #define WIN_B_ACT_REQ (1 << 2) 249 #define WIN_C_ACT_REQ (1 << 3) 250 #define CURSOR_ACT_REQ (1 << 7) 251 #define GENERAL_UPDATE (1 << 8) 252 #define WIN_A_UPDATE (1 << 9) 253 #define WIN_B_UPDATE (1 << 10) 254 #define WIN_C_UPDATE (1 << 11) 255 #define CURSOR_UPDATE (1 << 15) 256 #define COMMON_ACTREQ (1 << 16) 257 #define COMMON_UPDATE (1 << 17) 258 #define NC_HOST_TRIG (1 << 24) 259 260 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 261 #define WINDOW_A_SELECT (1 << 4) 262 #define WINDOW_B_SELECT (1 << 5) 263 #define WINDOW_C_SELECT (1 << 6) 264 265 #define DC_CMD_REG_ACT_CONTROL 0x043 266 267 #define DC_COM_CRC_CONTROL 0x300 268 #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) 269 #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) 270 #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) 271 #define DC_COM_CRC_CONTROL_WAIT (1 << 1) 272 #define DC_COM_CRC_CONTROL_ENABLE (1 << 0) 273 #define DC_COM_CRC_CHECKSUM 0x301 274 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) 275 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) 276 #define LVS_OUTPUT_POLARITY_LOW (1 << 28) 277 #define LHS_OUTPUT_POLARITY_LOW (1 << 30) 278 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) 279 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) 280 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) 281 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) 282 283 #define DC_COM_PIN_MISC_CONTROL 0x31b 284 #define DC_COM_PIN_PM0_CONTROL 0x31c 285 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d 286 #define DC_COM_PIN_PM1_CONTROL 0x31e 287 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f 288 289 #define DC_COM_SPI_CONTROL 0x320 290 #define DC_COM_SPI_START_BYTE 0x321 291 #define DC_COM_HSPI_WRITE_DATA_AB 0x322 292 #define DC_COM_HSPI_WRITE_DATA_CD 0x323 293 #define DC_COM_HSPI_CS_DC 0x324 294 #define DC_COM_SCRATCH_REGISTER_A 0x325 295 #define DC_COM_SCRATCH_REGISTER_B 0x326 296 #define DC_COM_GPIO_CTRL 0x327 297 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 298 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 299 300 #define DC_COM_RG_UNDERFLOW 0x365 301 #define UNDERFLOW_MODE_RED (1 << 8) 302 #define UNDERFLOW_REPORT_ENABLE (1 << 0) 303 304 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 305 #define H_PULSE0_ENABLE (1 << 8) 306 #define H_PULSE1_ENABLE (1 << 10) 307 #define H_PULSE2_ENABLE (1 << 12) 308 309 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 310 311 #define DC_DISP_DISP_WIN_OPTIONS 0x402 312 #define HDMI_ENABLE (1 << 30) 313 #define DSI_ENABLE (1 << 29) 314 #define SOR1_TIMING_CYA (1 << 27) 315 #define CURSOR_ENABLE (1 << 16) 316 317 #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x)))) 318 319 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 320 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 321 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 322 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) 323 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) 324 325 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 326 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24) 327 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) 328 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) 329 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) 330 331 #define DC_DISP_DISP_TIMING_OPTIONS 0x405 332 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 333 334 #define DC_DISP_REF_TO_SYNC 0x406 335 #define DC_DISP_SYNC_WIDTH 0x407 336 #define DC_DISP_BACK_PORCH 0x408 337 #define DC_DISP_ACTIVE 0x409 338 #define DC_DISP_FRONT_PORCH 0x40a 339 #define DC_DISP_H_PULSE0_CONTROL 0x40b 340 #define DC_DISP_H_PULSE0_POSITION_A 0x40c 341 #define DC_DISP_H_PULSE0_POSITION_B 0x40d 342 #define DC_DISP_H_PULSE0_POSITION_C 0x40e 343 #define DC_DISP_H_PULSE0_POSITION_D 0x40f 344 #define DC_DISP_H_PULSE1_CONTROL 0x410 345 #define DC_DISP_H_PULSE1_POSITION_A 0x411 346 #define DC_DISP_H_PULSE1_POSITION_B 0x412 347 #define DC_DISP_H_PULSE1_POSITION_C 0x413 348 #define DC_DISP_H_PULSE1_POSITION_D 0x414 349 #define DC_DISP_H_PULSE2_CONTROL 0x415 350 #define DC_DISP_H_PULSE2_POSITION_A 0x416 351 #define DC_DISP_H_PULSE2_POSITION_B 0x417 352 #define DC_DISP_H_PULSE2_POSITION_C 0x418 353 #define DC_DISP_H_PULSE2_POSITION_D 0x419 354 #define DC_DISP_V_PULSE0_CONTROL 0x41a 355 #define DC_DISP_V_PULSE0_POSITION_A 0x41b 356 #define DC_DISP_V_PULSE0_POSITION_B 0x41c 357 #define DC_DISP_V_PULSE0_POSITION_C 0x41d 358 #define DC_DISP_V_PULSE1_CONTROL 0x41e 359 #define DC_DISP_V_PULSE1_POSITION_A 0x41f 360 #define DC_DISP_V_PULSE1_POSITION_B 0x420 361 #define DC_DISP_V_PULSE1_POSITION_C 0x421 362 #define DC_DISP_V_PULSE2_CONTROL 0x422 363 #define DC_DISP_V_PULSE2_POSITION_A 0x423 364 #define DC_DISP_V_PULSE3_CONTROL 0x424 365 #define DC_DISP_V_PULSE3_POSITION_A 0x425 366 #define DC_DISP_M0_CONTROL 0x426 367 #define DC_DISP_M1_CONTROL 0x427 368 #define DC_DISP_DI_CONTROL 0x428 369 #define DC_DISP_PP_CONTROL 0x429 370 #define DC_DISP_PP_SELECT_A 0x42a 371 #define DC_DISP_PP_SELECT_B 0x42b 372 #define DC_DISP_PP_SELECT_C 0x42c 373 #define DC_DISP_PP_SELECT_D 0x42d 374 375 #define PULSE_MODE_NORMAL (0 << 3) 376 #define PULSE_MODE_ONE_CLOCK (1 << 3) 377 #define PULSE_POLARITY_HIGH (0 << 4) 378 #define PULSE_POLARITY_LOW (1 << 4) 379 #define PULSE_QUAL_ALWAYS (0 << 6) 380 #define PULSE_QUAL_VACTIVE (2 << 6) 381 #define PULSE_QUAL_VACTIVE1 (3 << 6) 382 #define PULSE_LAST_START_A (0 << 8) 383 #define PULSE_LAST_END_A (1 << 8) 384 #define PULSE_LAST_START_B (2 << 8) 385 #define PULSE_LAST_END_B (3 << 8) 386 #define PULSE_LAST_START_C (4 << 8) 387 #define PULSE_LAST_END_C (5 << 8) 388 #define PULSE_LAST_START_D (6 << 8) 389 #define PULSE_LAST_END_D (7 << 8) 390 391 #define PULSE_START(x) (((x) & 0xfff) << 0) 392 #define PULSE_END(x) (((x) & 0xfff) << 16) 393 394 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e 395 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) 396 #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) 397 #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) 398 #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) 399 #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) 400 #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) 401 #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) 402 #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) 403 #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) 404 #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) 405 #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) 406 #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) 407 #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) 408 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 409 410 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 411 #define DISP_DATA_FORMAT_DF1P1C (0 << 0) 412 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) 413 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) 414 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) 415 #define DISP_DATA_FORMAT_DF2S (4 << 0) 416 #define DISP_DATA_FORMAT_DF3S (5 << 0) 417 #define DISP_DATA_FORMAT_DFSPI (6 << 0) 418 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) 419 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) 420 #define DISP_ALIGNMENT_MSB (0 << 8) 421 #define DISP_ALIGNMENT_LSB (1 << 8) 422 #define DISP_ORDER_RED_BLUE (0 << 9) 423 #define DISP_ORDER_BLUE_RED (1 << 9) 424 425 #define DC_DISP_DISP_COLOR_CONTROL 0x430 426 #define BASE_COLOR_SIZE666 ( 0 << 0) 427 #define BASE_COLOR_SIZE111 ( 1 << 0) 428 #define BASE_COLOR_SIZE222 ( 2 << 0) 429 #define BASE_COLOR_SIZE333 ( 3 << 0) 430 #define BASE_COLOR_SIZE444 ( 4 << 0) 431 #define BASE_COLOR_SIZE555 ( 5 << 0) 432 #define BASE_COLOR_SIZE565 ( 6 << 0) 433 #define BASE_COLOR_SIZE332 ( 7 << 0) 434 #define BASE_COLOR_SIZE888 ( 8 << 0) 435 #define BASE_COLOR_SIZE101010 (10 << 0) 436 #define BASE_COLOR_SIZE121212 (12 << 0) 437 #define DITHER_CONTROL_MASK (3 << 8) 438 #define DITHER_CONTROL_DISABLE (0 << 8) 439 #define DITHER_CONTROL_ORDERED (2 << 8) 440 #define DITHER_CONTROL_ERRDIFF (3 << 8) 441 #define BASE_COLOR_SIZE_MASK (0xf << 0) 442 #define BASE_COLOR_SIZE_666 ( 0 << 0) 443 #define BASE_COLOR_SIZE_111 ( 1 << 0) 444 #define BASE_COLOR_SIZE_222 ( 2 << 0) 445 #define BASE_COLOR_SIZE_333 ( 3 << 0) 446 #define BASE_COLOR_SIZE_444 ( 4 << 0) 447 #define BASE_COLOR_SIZE_555 ( 5 << 0) 448 #define BASE_COLOR_SIZE_565 ( 6 << 0) 449 #define BASE_COLOR_SIZE_332 ( 7 << 0) 450 #define BASE_COLOR_SIZE_888 ( 8 << 0) 451 #define BASE_COLOR_SIZE_101010 ( 10 << 0) 452 #define BASE_COLOR_SIZE_121212 ( 12 << 0) 453 454 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 455 #define SC1_H_QUALIFIER_NONE (1 << 16) 456 #define SC0_H_QUALIFIER_NONE (1 << 0) 457 458 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432 459 #define DE_SELECT_ACTIVE_BLANK (0 << 0) 460 #define DE_SELECT_ACTIVE (1 << 0) 461 #define DE_SELECT_ACTIVE_IS (2 << 0) 462 #define DE_CONTROL_ONECLK (0 << 2) 463 #define DE_CONTROL_NORMAL (1 << 2) 464 #define DE_CONTROL_EARLY_EXT (2 << 2) 465 #define DE_CONTROL_EARLY (3 << 2) 466 #define DE_CONTROL_ACTIVE_BLANK (4 << 2) 467 468 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 469 #define DC_DISP_LCD_SPI_OPTIONS 0x434 470 #define DC_DISP_BORDER_COLOR 0x435 471 #define DC_DISP_COLOR_KEY0_LOWER 0x436 472 #define DC_DISP_COLOR_KEY0_UPPER 0x437 473 #define DC_DISP_COLOR_KEY1_LOWER 0x438 474 #define DC_DISP_COLOR_KEY1_UPPER 0x439 475 476 #define DC_DISP_CURSOR_FOREGROUND 0x43c 477 #define DC_DISP_CURSOR_BACKGROUND 0x43d 478 479 #define DC_DISP_CURSOR_START_ADDR 0x43e 480 #define CURSOR_CLIP_DISPLAY (0 << 28) 481 #define CURSOR_CLIP_WIN_A (1 << 28) 482 #define CURSOR_CLIP_WIN_B (2 << 28) 483 #define CURSOR_CLIP_WIN_C (3 << 28) 484 #define CURSOR_SIZE_32x32 (0 << 24) 485 #define CURSOR_SIZE_64x64 (1 << 24) 486 #define CURSOR_SIZE_128x128 (2 << 24) 487 #define CURSOR_SIZE_256x256 (3 << 24) 488 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f 489 490 #define DC_DISP_CURSOR_POSITION 0x440 491 #define DC_DISP_CURSOR_POSITION_NS 0x441 492 493 #define DC_DISP_INIT_SEQ_CONTROL 0x442 494 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 495 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 496 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 497 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 498 499 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 500 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 501 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 502 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 503 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 504 505 #define DC_DISP_DAC_CRT_CTRL 0x4c0 506 #define DC_DISP_DISP_MISC_CONTROL 0x4c1 507 #define DC_DISP_SD_CONTROL 0x4c2 508 #define DC_DISP_SD_CSC_COEFF 0x4c3 509 #define DC_DISP_SD_LUT(x) (0x4c4 + (x)) 510 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd 511 #define DC_DISP_DC_PIXEL_COUNT 0x4ce 512 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) 513 #define DC_DISP_SD_BL_PARAMETERS 0x4d7 514 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) 515 #define DC_DISP_SD_BL_CONTROL 0x4dc 516 #define DC_DISP_SD_HW_K_VALUES 0x4dd 517 #define DC_DISP_SD_MAN_K_VALUES 0x4de 518 519 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4 520 #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24) 521 #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16) 522 #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8) 523 #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0) 524 525 #define DC_DISP_INTERLACE_CONTROL 0x4e5 526 #define INTERLACE_STATUS (1 << 2) 527 #define INTERLACE_START (1 << 1) 528 #define INTERLACE_ENABLE (1 << 0) 529 530 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec 531 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 532 #define CURSOR_COMPOSITION_MODE_BLEND (0 << 25) 533 #define CURSOR_COMPOSITION_MODE_XOR (1 << 25) 534 #define CURSOR_MODE_LEGACY (0 << 24) 535 #define CURSOR_MODE_NORMAL (1 << 24) 536 #define CURSOR_DST_BLEND_ZERO (0 << 16) 537 #define CURSOR_DST_BLEND_K1 (1 << 16) 538 #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) 539 #define CURSOR_DST_BLEND_MASK (3 << 16) 540 #define CURSOR_SRC_BLEND_K1 (0 << 8) 541 #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) 542 #define CURSOR_SRC_BLEND_MASK (3 << 8) 543 #define CURSOR_ALPHA 0xff 544 545 #define DC_WIN_CORE_ACT_CONTROL 0x50e 546 #define VCOUNTER (0 << 0) 547 #define HCOUNTER (1 << 0) 548 549 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543 550 #define LATENCY_CTL_MODE_ENABLE (1 << 2) 551 552 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544 553 #define WATERMARK_MASK 0x1fffffff 554 555 #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560 556 #define PIPE_METER_INT(x) (((x) & 0xff) << 8) 557 #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0) 558 559 #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561 560 #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0) 561 562 #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562 563 #define SLOTS(x) (((x) & 0xff) << 0) 564 565 #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563 566 #define MODE_TWO_LINES (0 << 14) 567 #define MODE_FOUR_LINES (1 << 14) 568 569 #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568 570 #define THREAD_NUM_MASK (0x1f << 1) 571 #define THREAD_NUM(x) (((x) & 0x1f) << 1) 572 #define THREAD_GROUP_ENABLE (1 << 0) 573 574 #define DC_WIN_H_FILTER_P(p) (0x601 + (p)) 575 #define DC_WIN_V_FILTER_P(p) (0x619 + (p)) 576 577 #define DC_WIN_CSC_YOF 0x611 578 #define DC_WIN_CSC_KYRGB 0x612 579 #define DC_WIN_CSC_KUR 0x613 580 #define DC_WIN_CSC_KVR 0x614 581 #define DC_WIN_CSC_KUG 0x615 582 #define DC_WIN_CSC_KVG 0x616 583 #define DC_WIN_CSC_KUB 0x617 584 #define DC_WIN_CSC_KVB 0x618 585 586 #define DC_WIN_WIN_OPTIONS 0x700 587 #define H_DIRECTION (1 << 0) 588 #define V_DIRECTION (1 << 2) 589 #define COLOR_EXPAND (1 << 6) 590 #define H_FILTER (1 << 8) 591 #define V_FILTER (1 << 10) 592 #define CSC_ENABLE (1 << 18) 593 #define WIN_ENABLE (1 << 30) 594 595 #define DC_WIN_BYTE_SWAP 0x701 596 #define BYTE_SWAP_NOSWAP (0 << 0) 597 #define BYTE_SWAP_SWAP2 (1 << 0) 598 #define BYTE_SWAP_SWAP4 (2 << 0) 599 #define BYTE_SWAP_SWAP4HW (3 << 0) 600 601 #define DC_WIN_BUFFER_CONTROL 0x702 602 #define BUFFER_CONTROL_HOST (0 << 0) 603 #define BUFFER_CONTROL_VI (1 << 0) 604 #define BUFFER_CONTROL_EPP (2 << 0) 605 #define BUFFER_CONTROL_MPEGE (3 << 0) 606 #define BUFFER_CONTROL_SB2D (4 << 0) 607 608 #define DC_WIN_COLOR_DEPTH 0x703 609 #define WIN_COLOR_DEPTH_P1 0 610 #define WIN_COLOR_DEPTH_P2 1 611 #define WIN_COLOR_DEPTH_P4 2 612 #define WIN_COLOR_DEPTH_P8 3 613 #define WIN_COLOR_DEPTH_B4G4R4A4 4 614 #define WIN_COLOR_DEPTH_B5G5R5A1 5 615 #define WIN_COLOR_DEPTH_B5G6R5 6 616 #define WIN_COLOR_DEPTH_A1B5G5R5 7 617 #define WIN_COLOR_DEPTH_B8G8R8A8 12 618 #define WIN_COLOR_DEPTH_R8G8B8A8 13 619 #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 620 #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 621 #define WIN_COLOR_DEPTH_YCbCr422 16 622 #define WIN_COLOR_DEPTH_YUV422 17 623 #define WIN_COLOR_DEPTH_YCbCr420P 18 624 #define WIN_COLOR_DEPTH_YUV420P 19 625 #define WIN_COLOR_DEPTH_YCbCr422P 20 626 #define WIN_COLOR_DEPTH_YUV422P 21 627 #define WIN_COLOR_DEPTH_YCbCr422R 22 628 #define WIN_COLOR_DEPTH_YUV422R 23 629 #define WIN_COLOR_DEPTH_YCbCr422RA 24 630 #define WIN_COLOR_DEPTH_YUV422RA 25 631 #define WIN_COLOR_DEPTH_R4G4B4A4 27 632 #define WIN_COLOR_DEPTH_R5G5B5A 28 633 #define WIN_COLOR_DEPTH_AR5G5B5 29 634 #define WIN_COLOR_DEPTH_B5G5R5X1 30 635 #define WIN_COLOR_DEPTH_X1B5G5R5 31 636 #define WIN_COLOR_DEPTH_R5G5B5X1 32 637 #define WIN_COLOR_DEPTH_X1R5G5B5 33 638 #define WIN_COLOR_DEPTH_R5G6B5 34 639 #define WIN_COLOR_DEPTH_A8R8G8B8 35 640 #define WIN_COLOR_DEPTH_A8B8G8R8 36 641 #define WIN_COLOR_DEPTH_B8G8R8X8 37 642 #define WIN_COLOR_DEPTH_R8G8B8X8 38 643 #define WIN_COLOR_DEPTH_X8B8G8R8 65 644 #define WIN_COLOR_DEPTH_X8R8G8B8 66 645 646 #define DC_WIN_POSITION 0x704 647 #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ 648 #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 649 650 #define DC_WIN_SIZE 0x705 651 #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ 652 #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 653 654 #define DC_WIN_PRESCALED_SIZE 0x706 655 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 656 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 657 658 #define DC_WIN_H_INITIAL_DDA 0x707 659 #define DC_WIN_V_INITIAL_DDA 0x708 660 #define DC_WIN_DDA_INC 0x709 661 #define H_DDA_INC(x) (((x) & 0xffff) << 0) 662 #define V_DDA_INC(x) (((x) & 0xffff) << 16) 663 664 #define DC_WIN_LINE_STRIDE 0x70a 665 #define DC_WIN_BUF_STRIDE 0x70b 666 #define DC_WIN_UV_BUF_STRIDE 0x70c 667 #define DC_WIN_BUFFER_ADDR_MODE 0x70d 668 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) 669 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) 670 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) 671 #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) 672 673 #define DC_WIN_DV_CONTROL 0x70e 674 675 #define DC_WIN_BLEND_NOKEY 0x70f 676 #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16) 677 #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8) 678 679 #define DC_WIN_BLEND_1WIN 0x710 680 #define BLEND_CONTROL_FIX (0 << 2) 681 #define BLEND_CONTROL_ALPHA (1 << 2) 682 #define BLEND_COLOR_KEY_NONE (0 << 0) 683 #define BLEND_COLOR_KEY_0 (1 << 0) 684 #define BLEND_COLOR_KEY_1 (2 << 0) 685 #define BLEND_COLOR_KEY_BOTH (3 << 0) 686 687 #define DC_WIN_BLEND_2WIN_X 0x711 688 #define BLEND_CONTROL_DEPENDENT (2 << 2) 689 690 #define DC_WIN_BLEND_2WIN_Y 0x712 691 #define DC_WIN_BLEND_3WIN_XY 0x713 692 693 #define DC_WIN_HP_FETCH_CONTROL 0x714 694 695 #define DC_WINBUF_START_ADDR 0x800 696 #define DC_WINBUF_START_ADDR_NS 0x801 697 #define DC_WINBUF_START_ADDR_U 0x802 698 #define DC_WINBUF_START_ADDR_U_NS 0x803 699 #define DC_WINBUF_START_ADDR_V 0x804 700 #define DC_WINBUF_START_ADDR_V_NS 0x805 701 702 #define DC_WINBUF_ADDR_H_OFFSET 0x806 703 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 704 #define DC_WINBUF_ADDR_V_OFFSET 0x808 705 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 706 707 #define DC_WINBUF_UFLOW_STATUS 0x80a 708 #define DC_WINBUF_SURFACE_KIND 0x80b 709 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) 710 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) 711 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) 712 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 713 714 #define DC_WINBUF_START_ADDR_HI 0x80d 715 716 #define DC_WINBUF_START_ADDR_HI_U 0x80f 717 #define DC_WINBUF_START_ADDR_HI_V 0x811 718 719 #define DC_WINBUF_CDE_CONTROL 0x82f 720 #define ENABLE_SURFACE (1 << 0) 721 722 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca 723 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca 724 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca 725 726 /* Tegra186 and later */ 727 #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x)) 728 #define PROTOCOL_MASK (0xf << 8) 729 #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8) 730 731 #define DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR 0x442 732 #define DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR 0x446 733 734 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPA 0x500 735 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPB 0x501 736 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPC 0x502 737 #define MAX_PIXELS_5TAP444(x) ((x) & 0xffff) 738 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPD 0x503 739 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPE 0x504 740 #define MAX_PIXELS_2TAP444(x) ((x) & 0xffff) 741 #define DC_WINC_PRECOMP_WGRP_PIPE_CAPF 0x505 742 743 #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 744 #define OWNER_MASK (0xf << 0) 745 #define OWNER(x) (((x) & 0xf) << 0) 746 747 #define DC_WIN_CROPPED_SIZE 0x706 748 749 #define DC_WIN_SET_INPUT_SCALER_H_START_PHASE 0x707 750 #define DC_WIN_SET_INPUT_SCALER_V_START_PHASE 0x708 751 752 #define DC_WIN_PLANAR_STORAGE 0x709 753 #define PITCH(x) (((x) >> 6) & 0x1fff) 754 755 #define DC_WIN_PLANAR_STORAGE_UV 0x70a 756 #define PITCH_U(x) ((((x) >> 6) & 0x1fff) << 0) 757 #define PITCH_V(x) ((((x) >> 6) & 0x1fff) << 16) 758 759 #define DC_WIN_SET_INPUT_SCALER_HPHASE_INCR 0x70b 760 #define DC_WIN_SET_INPUT_SCALER_VPHASE_INCR 0x70c 761 762 #define DC_WIN_SET_PARAMS 0x70d 763 #define CLAMP_BEFORE_BLEND (1 << 15) 764 #define DEGAMMA_NONE (0 << 13) 765 #define DEGAMMA_SRGB (1 << 13) 766 #define DEGAMMA_YUV8_10 (2 << 13) 767 #define DEGAMMA_YUV12 (3 << 13) 768 #define INPUT_RANGE_BYPASS (0 << 10) 769 #define INPUT_RANGE_LIMITED (1 << 10) 770 #define INPUT_RANGE_FULL (2 << 10) 771 #define COLOR_SPACE_RGB (0 << 8) 772 #define COLOR_SPACE_YUV_601 (1 << 8) 773 #define COLOR_SPACE_YUV_709 (2 << 8) 774 #define COLOR_SPACE_YUV_2020 (3 << 8) 775 776 #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e 777 #define HORIZONTAL_TAPS_2 (1 << 3) 778 #define HORIZONTAL_TAPS_5 (4 << 3) 779 #define VERTICAL_TAPS_2 (1 << 0) 780 #define VERTICAL_TAPS_5 (4 << 0) 781 782 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_COEFF 0x70f 783 #define COEFF_INDEX(x) (((x) & 0xff) << 15) 784 #define COEFF_DATA(x) (((x) & 0x3ff) << 0) 785 786 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711 787 #define INPUT_SCALER_USE422 (1 << 2) 788 #define INPUT_SCALER_VBYPASS (1 << 1) 789 #define INPUT_SCALER_HBYPASS (1 << 0) 790 791 #define DC_WIN_BLEND_LAYER_CONTROL 0x716 792 #define COLOR_KEY_NONE (0 << 25) 793 #define COLOR_KEY_SRC (1 << 25) 794 #define COLOR_KEY_DST (2 << 25) 795 #define BLEND_BYPASS (1 << 24) 796 #define K2(x) (((x) & 0xff) << 16) 797 #define K1(x) (((x) & 0xff) << 8) 798 #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0) 799 800 #define DC_WIN_BLEND_MATCH_SELECT 0x717 801 #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12) 802 #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12) 803 #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12) 804 #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12) 805 #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8) 806 #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8) 807 #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8) 808 #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8) 809 #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4) 810 #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4) 811 #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4) 812 #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4) 813 #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4) 814 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4) 815 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4) 816 #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4) 817 #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0) 818 #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0) 819 #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0) 820 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0) 821 #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0) 822 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0) 823 824 #define DC_WIN_BLEND_NOMATCH_SELECT 0x718 825 826 #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724 827 #define SWAP_UV (1 << 0) 828 829 #define DC_WIN_WINDOW_SET_CONTROL 0x730 830 #define CONTROL_CSC_ENABLE (1 << 5) 831 832 #define DC_WINBUF_CROPPED_POINT 0x806 833 #define OFFSET_Y(x) (((x) & 0xffff) << 16) 834 #define OFFSET_X(x) (((x) & 0xffff) << 0) 835 836 #endif /* TEGRA_DC_H */ 837