1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #ifndef TEGRA_DC_H 8 #define TEGRA_DC_H 1 9 10 #include <linux/host1x.h> 11 12 #include <drm/drm_crtc.h> 13 14 #include "drm.h" 15 16 struct tegra_output; 17 18 struct tegra_dc_state { 19 struct drm_crtc_state base; 20 21 struct clk *clk; 22 unsigned long pclk; 23 unsigned int div; 24 25 u32 planes; 26 }; 27 28 static inline struct tegra_dc_state *to_dc_state(struct drm_crtc_state *state) 29 { 30 if (state) 31 return container_of(state, struct tegra_dc_state, base); 32 33 return NULL; 34 } 35 36 struct tegra_dc_stats { 37 unsigned long frames; 38 unsigned long vblank; 39 unsigned long underflow; 40 unsigned long overflow; 41 }; 42 43 struct tegra_windowgroup_soc { 44 unsigned int index; 45 unsigned int dc; 46 const unsigned int *windows; 47 unsigned int num_windows; 48 }; 49 50 struct tegra_dc_soc_info { 51 bool supports_background_color; 52 bool supports_interlacing; 53 bool supports_cursor; 54 bool supports_block_linear; 55 bool has_legacy_blending; 56 unsigned int pitch_align; 57 bool has_powergate; 58 bool coupled_pm; 59 bool has_nvdisplay; 60 const struct tegra_windowgroup_soc *wgrps; 61 unsigned int num_wgrps; 62 const u32 *primary_formats; 63 unsigned int num_primary_formats; 64 const u32 *overlay_formats; 65 unsigned int num_overlay_formats; 66 const u64 *modifiers; 67 bool has_win_a_without_filters; 68 bool has_win_c_without_vert_filter; 69 }; 70 71 struct tegra_dc { 72 struct host1x_client client; 73 struct host1x_syncpt *syncpt; 74 struct device *dev; 75 76 struct drm_crtc base; 77 unsigned int powergate; 78 int pipe; 79 80 struct clk *clk; 81 struct reset_control *rst; 82 void __iomem *regs; 83 int irq; 84 85 struct tegra_output *rgb; 86 87 struct tegra_dc_stats stats; 88 struct list_head list; 89 90 struct drm_info_list *debugfs_files; 91 92 const struct tegra_dc_soc_info *soc; 93 94 struct iommu_group *group; 95 }; 96 97 static inline struct tegra_dc * 98 host1x_client_to_dc(struct host1x_client *client) 99 { 100 return container_of(client, struct tegra_dc, client); 101 } 102 103 static inline struct tegra_dc *to_tegra_dc(struct drm_crtc *crtc) 104 { 105 return crtc ? container_of(crtc, struct tegra_dc, base) : NULL; 106 } 107 108 static inline void tegra_dc_writel(struct tegra_dc *dc, u32 value, 109 unsigned int offset) 110 { 111 trace_dc_writel(dc->dev, offset, value); 112 writel(value, dc->regs + (offset << 2)); 113 } 114 115 static inline u32 tegra_dc_readl(struct tegra_dc *dc, unsigned int offset) 116 { 117 u32 value = readl(dc->regs + (offset << 2)); 118 119 trace_dc_readl(dc->dev, offset, value); 120 121 return value; 122 } 123 124 struct tegra_dc_window { 125 struct { 126 unsigned int x; 127 unsigned int y; 128 unsigned int w; 129 unsigned int h; 130 } src; 131 struct { 132 unsigned int x; 133 unsigned int y; 134 unsigned int w; 135 unsigned int h; 136 } dst; 137 unsigned int bits_per_pixel; 138 unsigned int stride[2]; 139 unsigned long base[3]; 140 unsigned int zpos; 141 bool bottom_up; 142 143 struct tegra_bo_tiling tiling; 144 u32 format; 145 u32 swap; 146 }; 147 148 /* from dc.c */ 149 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev); 150 void tegra_dc_commit(struct tegra_dc *dc); 151 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 152 struct drm_crtc_state *crtc_state, 153 struct clk *clk, unsigned long pclk, 154 unsigned int div); 155 156 /* from rgb.c */ 157 int tegra_dc_rgb_probe(struct tegra_dc *dc); 158 int tegra_dc_rgb_remove(struct tegra_dc *dc); 159 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc); 160 int tegra_dc_rgb_exit(struct tegra_dc *dc); 161 162 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000 163 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001 164 #define SYNCPT_CNTRL_NO_STALL (1 << 8) 165 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0) 166 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002 167 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008 168 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009 169 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a 170 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010 171 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011 172 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012 173 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018 174 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019 175 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a 176 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028 177 #define SYNCPT_VSYNC_ENABLE (1 << 8) 178 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031 179 #define DC_CMD_DISPLAY_COMMAND 0x032 180 #define DISP_CTRL_MODE_STOP (0 << 5) 181 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5) 182 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5) 183 #define DISP_CTRL_MODE_MASK (3 << 5) 184 #define DC_CMD_SIGNAL_RAISE 0x033 185 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036 186 #define PW0_ENABLE (1 << 0) 187 #define PW1_ENABLE (1 << 2) 188 #define PW2_ENABLE (1 << 4) 189 #define PW3_ENABLE (1 << 6) 190 #define PW4_ENABLE (1 << 8) 191 #define PM0_ENABLE (1 << 16) 192 #define PM1_ENABLE (1 << 18) 193 194 #define DC_CMD_INT_STATUS 0x037 195 #define DC_CMD_INT_MASK 0x038 196 #define DC_CMD_INT_ENABLE 0x039 197 #define DC_CMD_INT_TYPE 0x03a 198 #define DC_CMD_INT_POLARITY 0x03b 199 #define CTXSW_INT (1 << 0) 200 #define FRAME_END_INT (1 << 1) 201 #define VBLANK_INT (1 << 2) 202 #define V_PULSE3_INT (1 << 4) 203 #define V_PULSE2_INT (1 << 5) 204 #define REGION_CRC_INT (1 << 6) 205 #define REG_TMOUT_INT (1 << 7) 206 #define WIN_A_UF_INT (1 << 8) 207 #define WIN_B_UF_INT (1 << 9) 208 #define WIN_C_UF_INT (1 << 10) 209 #define MSF_INT (1 << 12) 210 #define WIN_A_OF_INT (1 << 14) 211 #define WIN_B_OF_INT (1 << 15) 212 #define WIN_C_OF_INT (1 << 16) 213 #define HEAD_UF_INT (1 << 23) 214 #define SD3_BUCKET_WALK_DONE_INT (1 << 24) 215 #define DSC_OBUF_UF_INT (1 << 26) 216 #define DSC_RBUF_UF_INT (1 << 27) 217 #define DSC_BBUF_UF_INT (1 << 28) 218 #define DSC_TO_UF_INT (1 << 29) 219 220 #define DC_CMD_SIGNAL_RAISE1 0x03c 221 #define DC_CMD_SIGNAL_RAISE2 0x03d 222 #define DC_CMD_SIGNAL_RAISE3 0x03e 223 224 #define DC_CMD_STATE_ACCESS 0x040 225 #define READ_MUX (1 << 0) 226 #define WRITE_MUX (1 << 2) 227 228 #define DC_CMD_STATE_CONTROL 0x041 229 #define GENERAL_ACT_REQ (1 << 0) 230 #define WIN_A_ACT_REQ (1 << 1) 231 #define WIN_B_ACT_REQ (1 << 2) 232 #define WIN_C_ACT_REQ (1 << 3) 233 #define CURSOR_ACT_REQ (1 << 7) 234 #define GENERAL_UPDATE (1 << 8) 235 #define WIN_A_UPDATE (1 << 9) 236 #define WIN_B_UPDATE (1 << 10) 237 #define WIN_C_UPDATE (1 << 11) 238 #define CURSOR_UPDATE (1 << 15) 239 #define COMMON_ACTREQ (1 << 16) 240 #define COMMON_UPDATE (1 << 17) 241 #define NC_HOST_TRIG (1 << 24) 242 243 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042 244 #define WINDOW_A_SELECT (1 << 4) 245 #define WINDOW_B_SELECT (1 << 5) 246 #define WINDOW_C_SELECT (1 << 6) 247 248 #define DC_CMD_REG_ACT_CONTROL 0x043 249 250 #define DC_COM_CRC_CONTROL 0x300 251 #define DC_COM_CRC_CONTROL_ALWAYS (1 << 3) 252 #define DC_COM_CRC_CONTROL_FULL_FRAME (0 << 2) 253 #define DC_COM_CRC_CONTROL_ACTIVE_DATA (1 << 2) 254 #define DC_COM_CRC_CONTROL_WAIT (1 << 1) 255 #define DC_COM_CRC_CONTROL_ENABLE (1 << 0) 256 #define DC_COM_CRC_CHECKSUM 0x301 257 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x)) 258 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x)) 259 #define LVS_OUTPUT_POLARITY_LOW (1 << 28) 260 #define LHS_OUTPUT_POLARITY_LOW (1 << 30) 261 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x)) 262 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x)) 263 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x)) 264 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x)) 265 266 #define DC_COM_PIN_MISC_CONTROL 0x31b 267 #define DC_COM_PIN_PM0_CONTROL 0x31c 268 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d 269 #define DC_COM_PIN_PM1_CONTROL 0x31e 270 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f 271 272 #define DC_COM_SPI_CONTROL 0x320 273 #define DC_COM_SPI_START_BYTE 0x321 274 #define DC_COM_HSPI_WRITE_DATA_AB 0x322 275 #define DC_COM_HSPI_WRITE_DATA_CD 0x323 276 #define DC_COM_HSPI_CS_DC 0x324 277 #define DC_COM_SCRATCH_REGISTER_A 0x325 278 #define DC_COM_SCRATCH_REGISTER_B 0x326 279 #define DC_COM_GPIO_CTRL 0x327 280 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328 281 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329 282 283 #define DC_COM_RG_UNDERFLOW 0x365 284 #define UNDERFLOW_MODE_RED (1 << 8) 285 #define UNDERFLOW_REPORT_ENABLE (1 << 0) 286 287 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400 288 #define H_PULSE0_ENABLE (1 << 8) 289 #define H_PULSE1_ENABLE (1 << 10) 290 #define H_PULSE2_ENABLE (1 << 12) 291 292 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401 293 294 #define DC_DISP_DISP_WIN_OPTIONS 0x402 295 #define HDMI_ENABLE (1 << 30) 296 #define DSI_ENABLE (1 << 29) 297 #define SOR1_TIMING_CYA (1 << 27) 298 #define CURSOR_ENABLE (1 << 16) 299 300 #define SOR_ENABLE(x) (1 << (25 + (((x) > 1) ? ((x) + 1) : (x)))) 301 302 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403 303 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24) 304 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16) 305 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8) 306 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0) 307 308 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404 309 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24) 310 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16) 311 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8) 312 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0) 313 314 #define DC_DISP_DISP_TIMING_OPTIONS 0x405 315 #define VSYNC_H_POSITION(x) ((x) & 0xfff) 316 317 #define DC_DISP_REF_TO_SYNC 0x406 318 #define DC_DISP_SYNC_WIDTH 0x407 319 #define DC_DISP_BACK_PORCH 0x408 320 #define DC_DISP_ACTIVE 0x409 321 #define DC_DISP_FRONT_PORCH 0x40a 322 #define DC_DISP_H_PULSE0_CONTROL 0x40b 323 #define DC_DISP_H_PULSE0_POSITION_A 0x40c 324 #define DC_DISP_H_PULSE0_POSITION_B 0x40d 325 #define DC_DISP_H_PULSE0_POSITION_C 0x40e 326 #define DC_DISP_H_PULSE0_POSITION_D 0x40f 327 #define DC_DISP_H_PULSE1_CONTROL 0x410 328 #define DC_DISP_H_PULSE1_POSITION_A 0x411 329 #define DC_DISP_H_PULSE1_POSITION_B 0x412 330 #define DC_DISP_H_PULSE1_POSITION_C 0x413 331 #define DC_DISP_H_PULSE1_POSITION_D 0x414 332 #define DC_DISP_H_PULSE2_CONTROL 0x415 333 #define DC_DISP_H_PULSE2_POSITION_A 0x416 334 #define DC_DISP_H_PULSE2_POSITION_B 0x417 335 #define DC_DISP_H_PULSE2_POSITION_C 0x418 336 #define DC_DISP_H_PULSE2_POSITION_D 0x419 337 #define DC_DISP_V_PULSE0_CONTROL 0x41a 338 #define DC_DISP_V_PULSE0_POSITION_A 0x41b 339 #define DC_DISP_V_PULSE0_POSITION_B 0x41c 340 #define DC_DISP_V_PULSE0_POSITION_C 0x41d 341 #define DC_DISP_V_PULSE1_CONTROL 0x41e 342 #define DC_DISP_V_PULSE1_POSITION_A 0x41f 343 #define DC_DISP_V_PULSE1_POSITION_B 0x420 344 #define DC_DISP_V_PULSE1_POSITION_C 0x421 345 #define DC_DISP_V_PULSE2_CONTROL 0x422 346 #define DC_DISP_V_PULSE2_POSITION_A 0x423 347 #define DC_DISP_V_PULSE3_CONTROL 0x424 348 #define DC_DISP_V_PULSE3_POSITION_A 0x425 349 #define DC_DISP_M0_CONTROL 0x426 350 #define DC_DISP_M1_CONTROL 0x427 351 #define DC_DISP_DI_CONTROL 0x428 352 #define DC_DISP_PP_CONTROL 0x429 353 #define DC_DISP_PP_SELECT_A 0x42a 354 #define DC_DISP_PP_SELECT_B 0x42b 355 #define DC_DISP_PP_SELECT_C 0x42c 356 #define DC_DISP_PP_SELECT_D 0x42d 357 358 #define PULSE_MODE_NORMAL (0 << 3) 359 #define PULSE_MODE_ONE_CLOCK (1 << 3) 360 #define PULSE_POLARITY_HIGH (0 << 4) 361 #define PULSE_POLARITY_LOW (1 << 4) 362 #define PULSE_QUAL_ALWAYS (0 << 6) 363 #define PULSE_QUAL_VACTIVE (2 << 6) 364 #define PULSE_QUAL_VACTIVE1 (3 << 6) 365 #define PULSE_LAST_START_A (0 << 8) 366 #define PULSE_LAST_END_A (1 << 8) 367 #define PULSE_LAST_START_B (2 << 8) 368 #define PULSE_LAST_END_B (3 << 8) 369 #define PULSE_LAST_START_C (4 << 8) 370 #define PULSE_LAST_END_C (5 << 8) 371 #define PULSE_LAST_START_D (6 << 8) 372 #define PULSE_LAST_END_D (7 << 8) 373 374 #define PULSE_START(x) (((x) & 0xfff) << 0) 375 #define PULSE_END(x) (((x) & 0xfff) << 16) 376 377 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e 378 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8) 379 #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8) 380 #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8) 381 #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8) 382 #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8) 383 #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8) 384 #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8) 385 #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8) 386 #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8) 387 #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8) 388 #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8) 389 #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8) 390 #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8) 391 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff) 392 393 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f 394 #define DISP_DATA_FORMAT_DF1P1C (0 << 0) 395 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0) 396 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0) 397 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0) 398 #define DISP_DATA_FORMAT_DF2S (4 << 0) 399 #define DISP_DATA_FORMAT_DF3S (5 << 0) 400 #define DISP_DATA_FORMAT_DFSPI (6 << 0) 401 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0) 402 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0) 403 #define DISP_ALIGNMENT_MSB (0 << 8) 404 #define DISP_ALIGNMENT_LSB (1 << 8) 405 #define DISP_ORDER_RED_BLUE (0 << 9) 406 #define DISP_ORDER_BLUE_RED (1 << 9) 407 408 #define DC_DISP_DISP_COLOR_CONTROL 0x430 409 #define BASE_COLOR_SIZE666 ( 0 << 0) 410 #define BASE_COLOR_SIZE111 ( 1 << 0) 411 #define BASE_COLOR_SIZE222 ( 2 << 0) 412 #define BASE_COLOR_SIZE333 ( 3 << 0) 413 #define BASE_COLOR_SIZE444 ( 4 << 0) 414 #define BASE_COLOR_SIZE555 ( 5 << 0) 415 #define BASE_COLOR_SIZE565 ( 6 << 0) 416 #define BASE_COLOR_SIZE332 ( 7 << 0) 417 #define BASE_COLOR_SIZE888 ( 8 << 0) 418 #define BASE_COLOR_SIZE101010 (10 << 0) 419 #define BASE_COLOR_SIZE121212 (12 << 0) 420 #define DITHER_CONTROL_MASK (3 << 8) 421 #define DITHER_CONTROL_DISABLE (0 << 8) 422 #define DITHER_CONTROL_ORDERED (2 << 8) 423 #define DITHER_CONTROL_ERRDIFF (3 << 8) 424 #define BASE_COLOR_SIZE_MASK (0xf << 0) 425 #define BASE_COLOR_SIZE_666 ( 0 << 0) 426 #define BASE_COLOR_SIZE_111 ( 1 << 0) 427 #define BASE_COLOR_SIZE_222 ( 2 << 0) 428 #define BASE_COLOR_SIZE_333 ( 3 << 0) 429 #define BASE_COLOR_SIZE_444 ( 4 << 0) 430 #define BASE_COLOR_SIZE_555 ( 5 << 0) 431 #define BASE_COLOR_SIZE_565 ( 6 << 0) 432 #define BASE_COLOR_SIZE_332 ( 7 << 0) 433 #define BASE_COLOR_SIZE_888 ( 8 << 0) 434 #define BASE_COLOR_SIZE_101010 ( 10 << 0) 435 #define BASE_COLOR_SIZE_121212 ( 12 << 0) 436 437 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431 438 #define SC1_H_QUALIFIER_NONE (1 << 16) 439 #define SC0_H_QUALIFIER_NONE (1 << 0) 440 441 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432 442 #define DE_SELECT_ACTIVE_BLANK (0 << 0) 443 #define DE_SELECT_ACTIVE (1 << 0) 444 #define DE_SELECT_ACTIVE_IS (2 << 0) 445 #define DE_CONTROL_ONECLK (0 << 2) 446 #define DE_CONTROL_NORMAL (1 << 2) 447 #define DE_CONTROL_EARLY_EXT (2 << 2) 448 #define DE_CONTROL_EARLY (3 << 2) 449 #define DE_CONTROL_ACTIVE_BLANK (4 << 2) 450 451 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433 452 #define DC_DISP_LCD_SPI_OPTIONS 0x434 453 #define DC_DISP_BORDER_COLOR 0x435 454 #define DC_DISP_COLOR_KEY0_LOWER 0x436 455 #define DC_DISP_COLOR_KEY0_UPPER 0x437 456 #define DC_DISP_COLOR_KEY1_LOWER 0x438 457 #define DC_DISP_COLOR_KEY1_UPPER 0x439 458 459 #define DC_DISP_CURSOR_FOREGROUND 0x43c 460 #define DC_DISP_CURSOR_BACKGROUND 0x43d 461 462 #define DC_DISP_CURSOR_START_ADDR 0x43e 463 #define CURSOR_CLIP_DISPLAY (0 << 28) 464 #define CURSOR_CLIP_WIN_A (1 << 28) 465 #define CURSOR_CLIP_WIN_B (2 << 28) 466 #define CURSOR_CLIP_WIN_C (3 << 28) 467 #define CURSOR_SIZE_32x32 (0 << 24) 468 #define CURSOR_SIZE_64x64 (1 << 24) 469 #define CURSOR_SIZE_128x128 (2 << 24) 470 #define CURSOR_SIZE_256x256 (3 << 24) 471 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f 472 473 #define DC_DISP_CURSOR_POSITION 0x440 474 #define DC_DISP_CURSOR_POSITION_NS 0x441 475 476 #define DC_DISP_INIT_SEQ_CONTROL 0x442 477 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443 478 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444 479 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445 480 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446 481 482 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480 483 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481 484 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482 485 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483 486 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484 487 488 #define DC_DISP_DAC_CRT_CTRL 0x4c0 489 #define DC_DISP_DISP_MISC_CONTROL 0x4c1 490 #define DC_DISP_SD_CONTROL 0x4c2 491 #define DC_DISP_SD_CSC_COEFF 0x4c3 492 #define DC_DISP_SD_LUT(x) (0x4c4 + (x)) 493 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd 494 #define DC_DISP_DC_PIXEL_COUNT 0x4ce 495 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x)) 496 #define DC_DISP_SD_BL_PARAMETERS 0x4d7 497 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x)) 498 #define DC_DISP_SD_BL_CONTROL 0x4dc 499 #define DC_DISP_SD_HW_K_VALUES 0x4dd 500 #define DC_DISP_SD_MAN_K_VALUES 0x4de 501 502 #define DC_DISP_BLEND_BACKGROUND_COLOR 0x4e4 503 #define BACKGROUND_COLOR_ALPHA(x) (((x) & 0xff) << 24) 504 #define BACKGROUND_COLOR_BLUE(x) (((x) & 0xff) << 16) 505 #define BACKGROUND_COLOR_GREEN(x) (((x) & 0xff) << 8) 506 #define BACKGROUND_COLOR_RED(x) (((x) & 0xff) << 0) 507 508 #define DC_DISP_INTERLACE_CONTROL 0x4e5 509 #define INTERLACE_STATUS (1 << 2) 510 #define INTERLACE_START (1 << 1) 511 #define INTERLACE_ENABLE (1 << 0) 512 513 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec 514 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1 515 #define CURSOR_MODE_LEGACY (0 << 24) 516 #define CURSOR_MODE_NORMAL (1 << 24) 517 #define CURSOR_DST_BLEND_ZERO (0 << 16) 518 #define CURSOR_DST_BLEND_K1 (1 << 16) 519 #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16) 520 #define CURSOR_DST_BLEND_MASK (3 << 16) 521 #define CURSOR_SRC_BLEND_K1 (0 << 8) 522 #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8) 523 #define CURSOR_SRC_BLEND_MASK (3 << 8) 524 #define CURSOR_ALPHA 0xff 525 526 #define DC_WIN_CORE_ACT_CONTROL 0x50e 527 #define VCOUNTER (0 << 0) 528 #define HCOUNTER (1 << 0) 529 530 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLA 0x543 531 #define LATENCY_CTL_MODE_ENABLE (1 << 2) 532 533 #define DC_WIN_CORE_IHUB_WGRP_LATENCY_CTLB 0x544 534 #define WATERMARK_MASK 0x1fffffff 535 536 #define DC_WIN_CORE_PRECOMP_WGRP_PIPE_METER 0x560 537 #define PIPE_METER_INT(x) (((x) & 0xff) << 8) 538 #define PIPE_METER_FRAC(x) (((x) & 0xff) << 0) 539 540 #define DC_WIN_CORE_IHUB_WGRP_POOL_CONFIG 0x561 541 #define MEMPOOL_ENTRIES(x) (((x) & 0xffff) << 0) 542 543 #define DC_WIN_CORE_IHUB_WGRP_FETCH_METER 0x562 544 #define SLOTS(x) (((x) & 0xff) << 0) 545 546 #define DC_WIN_CORE_IHUB_LINEBUF_CONFIG 0x563 547 #define MODE_TWO_LINES (0 << 14) 548 #define MODE_FOUR_LINES (1 << 14) 549 550 #define DC_WIN_CORE_IHUB_THREAD_GROUP 0x568 551 #define THREAD_NUM_MASK (0x1f << 1) 552 #define THREAD_NUM(x) (((x) & 0x1f) << 1) 553 #define THREAD_GROUP_ENABLE (1 << 0) 554 555 #define DC_WIN_H_FILTER_P(p) (0x601 + (p)) 556 #define DC_WIN_V_FILTER_P(p) (0x619 + (p)) 557 558 #define DC_WIN_CSC_YOF 0x611 559 #define DC_WIN_CSC_KYRGB 0x612 560 #define DC_WIN_CSC_KUR 0x613 561 #define DC_WIN_CSC_KVR 0x614 562 #define DC_WIN_CSC_KUG 0x615 563 #define DC_WIN_CSC_KVG 0x616 564 #define DC_WIN_CSC_KUB 0x617 565 #define DC_WIN_CSC_KVB 0x618 566 567 #define DC_WIN_WIN_OPTIONS 0x700 568 #define H_DIRECTION (1 << 0) 569 #define V_DIRECTION (1 << 2) 570 #define COLOR_EXPAND (1 << 6) 571 #define H_FILTER (1 << 8) 572 #define V_FILTER (1 << 10) 573 #define CSC_ENABLE (1 << 18) 574 #define WIN_ENABLE (1 << 30) 575 576 #define DC_WIN_BYTE_SWAP 0x701 577 #define BYTE_SWAP_NOSWAP (0 << 0) 578 #define BYTE_SWAP_SWAP2 (1 << 0) 579 #define BYTE_SWAP_SWAP4 (2 << 0) 580 #define BYTE_SWAP_SWAP4HW (3 << 0) 581 582 #define DC_WIN_BUFFER_CONTROL 0x702 583 #define BUFFER_CONTROL_HOST (0 << 0) 584 #define BUFFER_CONTROL_VI (1 << 0) 585 #define BUFFER_CONTROL_EPP (2 << 0) 586 #define BUFFER_CONTROL_MPEGE (3 << 0) 587 #define BUFFER_CONTROL_SB2D (4 << 0) 588 589 #define DC_WIN_COLOR_DEPTH 0x703 590 #define WIN_COLOR_DEPTH_P1 0 591 #define WIN_COLOR_DEPTH_P2 1 592 #define WIN_COLOR_DEPTH_P4 2 593 #define WIN_COLOR_DEPTH_P8 3 594 #define WIN_COLOR_DEPTH_B4G4R4A4 4 595 #define WIN_COLOR_DEPTH_B5G5R5A1 5 596 #define WIN_COLOR_DEPTH_B5G6R5 6 597 #define WIN_COLOR_DEPTH_A1B5G5R5 7 598 #define WIN_COLOR_DEPTH_B8G8R8A8 12 599 #define WIN_COLOR_DEPTH_R8G8B8A8 13 600 #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14 601 #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15 602 #define WIN_COLOR_DEPTH_YCbCr422 16 603 #define WIN_COLOR_DEPTH_YUV422 17 604 #define WIN_COLOR_DEPTH_YCbCr420P 18 605 #define WIN_COLOR_DEPTH_YUV420P 19 606 #define WIN_COLOR_DEPTH_YCbCr422P 20 607 #define WIN_COLOR_DEPTH_YUV422P 21 608 #define WIN_COLOR_DEPTH_YCbCr422R 22 609 #define WIN_COLOR_DEPTH_YUV422R 23 610 #define WIN_COLOR_DEPTH_YCbCr422RA 24 611 #define WIN_COLOR_DEPTH_YUV422RA 25 612 #define WIN_COLOR_DEPTH_R4G4B4A4 27 613 #define WIN_COLOR_DEPTH_R5G5B5A 28 614 #define WIN_COLOR_DEPTH_AR5G5B5 29 615 #define WIN_COLOR_DEPTH_B5G5R5X1 30 616 #define WIN_COLOR_DEPTH_X1B5G5R5 31 617 #define WIN_COLOR_DEPTH_R5G5B5X1 32 618 #define WIN_COLOR_DEPTH_X1R5G5B5 33 619 #define WIN_COLOR_DEPTH_R5G6B5 34 620 #define WIN_COLOR_DEPTH_A8R8G8B8 35 621 #define WIN_COLOR_DEPTH_A8B8G8R8 36 622 #define WIN_COLOR_DEPTH_B8G8R8X8 37 623 #define WIN_COLOR_DEPTH_R8G8B8X8 38 624 #define WIN_COLOR_DEPTH_X8B8G8R8 65 625 #define WIN_COLOR_DEPTH_X8R8G8B8 66 626 627 #define DC_WIN_POSITION 0x704 628 #define H_POSITION(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ 629 #define V_POSITION(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 630 631 #define DC_WIN_SIZE 0x705 632 #define H_SIZE(x) (((x) & 0x1fff) << 0) /* XXX 0x7fff on Tegra186 */ 633 #define V_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 634 635 #define DC_WIN_PRESCALED_SIZE 0x706 636 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0) 637 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16) /* XXX 0x7fff on Tegra186 */ 638 639 #define DC_WIN_H_INITIAL_DDA 0x707 640 #define DC_WIN_V_INITIAL_DDA 0x708 641 #define DC_WIN_DDA_INC 0x709 642 #define H_DDA_INC(x) (((x) & 0xffff) << 0) 643 #define V_DDA_INC(x) (((x) & 0xffff) << 16) 644 645 #define DC_WIN_LINE_STRIDE 0x70a 646 #define DC_WIN_BUF_STRIDE 0x70b 647 #define DC_WIN_UV_BUF_STRIDE 0x70c 648 #define DC_WIN_BUFFER_ADDR_MODE 0x70d 649 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0) 650 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0) 651 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16) 652 #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16) 653 654 #define DC_WIN_DV_CONTROL 0x70e 655 656 #define DC_WIN_BLEND_NOKEY 0x70f 657 #define BLEND_WEIGHT1(x) (((x) & 0xff) << 16) 658 #define BLEND_WEIGHT0(x) (((x) & 0xff) << 8) 659 660 #define DC_WIN_BLEND_1WIN 0x710 661 #define BLEND_CONTROL_FIX (0 << 2) 662 #define BLEND_CONTROL_ALPHA (1 << 2) 663 #define BLEND_COLOR_KEY_NONE (0 << 0) 664 #define BLEND_COLOR_KEY_0 (1 << 0) 665 #define BLEND_COLOR_KEY_1 (2 << 0) 666 #define BLEND_COLOR_KEY_BOTH (3 << 0) 667 668 #define DC_WIN_BLEND_2WIN_X 0x711 669 #define BLEND_CONTROL_DEPENDENT (2 << 2) 670 671 #define DC_WIN_BLEND_2WIN_Y 0x712 672 #define DC_WIN_BLEND_3WIN_XY 0x713 673 674 #define DC_WIN_HP_FETCH_CONTROL 0x714 675 676 #define DC_WINBUF_START_ADDR 0x800 677 #define DC_WINBUF_START_ADDR_NS 0x801 678 #define DC_WINBUF_START_ADDR_U 0x802 679 #define DC_WINBUF_START_ADDR_U_NS 0x803 680 #define DC_WINBUF_START_ADDR_V 0x804 681 #define DC_WINBUF_START_ADDR_V_NS 0x805 682 683 #define DC_WINBUF_ADDR_H_OFFSET 0x806 684 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807 685 #define DC_WINBUF_ADDR_V_OFFSET 0x808 686 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809 687 688 #define DC_WINBUF_UFLOW_STATUS 0x80a 689 #define DC_WINBUF_SURFACE_KIND 0x80b 690 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0) 691 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0) 692 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0) 693 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4) 694 695 #define DC_WINBUF_START_ADDR_HI 0x80d 696 697 #define DC_WINBUF_CDE_CONTROL 0x82f 698 #define ENABLE_SURFACE (1 << 0) 699 700 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca 701 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca 702 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca 703 704 /* Tegra186 and later */ 705 #define DC_DISP_CORE_SOR_SET_CONTROL(x) (0x403 + (x)) 706 #define PROTOCOL_MASK (0xf << 8) 707 #define PROTOCOL_SINGLE_TMDS_A (0x1 << 8) 708 709 #define DC_WIN_CORE_WINDOWGROUP_SET_CONTROL 0x702 710 #define OWNER_MASK (0xf << 0) 711 #define OWNER(x) (((x) & 0xf) << 0) 712 713 #define DC_WIN_CROPPED_SIZE 0x706 714 715 #define DC_WIN_PLANAR_STORAGE 0x709 716 #define PITCH(x) (((x) >> 6) & 0x1fff) 717 718 #define DC_WIN_SET_PARAMS 0x70d 719 #define CLAMP_BEFORE_BLEND (1 << 15) 720 #define DEGAMMA_NONE (0 << 13) 721 #define DEGAMMA_SRGB (1 << 13) 722 #define DEGAMMA_YUV8_10 (2 << 13) 723 #define DEGAMMA_YUV12 (3 << 13) 724 #define INPUT_RANGE_BYPASS (0 << 10) 725 #define INPUT_RANGE_LIMITED (1 << 10) 726 #define INPUT_RANGE_FULL (2 << 10) 727 #define COLOR_SPACE_RGB (0 << 8) 728 #define COLOR_SPACE_YUV_601 (1 << 8) 729 #define COLOR_SPACE_YUV_709 (2 << 8) 730 #define COLOR_SPACE_YUV_2020 (3 << 8) 731 732 #define DC_WIN_WINDOWGROUP_SET_CONTROL_INPUT_SCALER 0x70e 733 #define HORIZONTAL_TAPS_2 (1 << 3) 734 #define HORIZONTAL_TAPS_5 (4 << 3) 735 #define VERTICAL_TAPS_2 (1 << 0) 736 #define VERTICAL_TAPS_5 (4 << 0) 737 738 #define DC_WIN_WINDOWGROUP_SET_INPUT_SCALER_USAGE 0x711 739 #define INPUT_SCALER_USE422 (1 << 2) 740 #define INPUT_SCALER_VBYPASS (1 << 1) 741 #define INPUT_SCALER_HBYPASS (1 << 0) 742 743 #define DC_WIN_BLEND_LAYER_CONTROL 0x716 744 #define COLOR_KEY_NONE (0 << 25) 745 #define COLOR_KEY_SRC (1 << 25) 746 #define COLOR_KEY_DST (2 << 25) 747 #define BLEND_BYPASS (1 << 24) 748 #define K2(x) (((x) & 0xff) << 16) 749 #define K1(x) (((x) & 0xff) << 8) 750 #define WINDOW_LAYER_DEPTH(x) (((x) & 0xff) << 0) 751 752 #define DC_WIN_BLEND_MATCH_SELECT 0x717 753 #define BLEND_FACTOR_DST_ALPHA_ZERO (0 << 12) 754 #define BLEND_FACTOR_DST_ALPHA_ONE (1 << 12) 755 #define BLEND_FACTOR_DST_ALPHA_NEG_K1_TIMES_SRC (2 << 12) 756 #define BLEND_FACTOR_DST_ALPHA_K2 (3 << 12) 757 #define BLEND_FACTOR_SRC_ALPHA_ZERO (0 << 8) 758 #define BLEND_FACTOR_SRC_ALPHA_K1 (1 << 8) 759 #define BLEND_FACTOR_SRC_ALPHA_K2 (2 << 8) 760 #define BLEND_FACTOR_SRC_ALPHA_NEG_K1_TIMES_DST (3 << 8) 761 #define BLEND_FACTOR_DST_COLOR_ZERO (0 << 4) 762 #define BLEND_FACTOR_DST_COLOR_ONE (1 << 4) 763 #define BLEND_FACTOR_DST_COLOR_K1 (2 << 4) 764 #define BLEND_FACTOR_DST_COLOR_K2 (3 << 4) 765 #define BLEND_FACTOR_DST_COLOR_K1_TIMES_DST (4 << 4) 766 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_DST (5 << 4) 767 #define BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC (6 << 4) 768 #define BLEND_FACTOR_DST_COLOR_NEG_K1 (7 << 4) 769 #define BLEND_FACTOR_SRC_COLOR_ZERO (0 << 0) 770 #define BLEND_FACTOR_SRC_COLOR_ONE (1 << 0) 771 #define BLEND_FACTOR_SRC_COLOR_K1 (2 << 0) 772 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_DST (3 << 0) 773 #define BLEND_FACTOR_SRC_COLOR_NEG_K1_TIMES_DST (4 << 0) 774 #define BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC (5 << 0) 775 776 #define DC_WIN_BLEND_NOMATCH_SELECT 0x718 777 778 #define DC_WIN_PRECOMP_WGRP_PARAMS 0x724 779 #define SWAP_UV (1 << 0) 780 781 #define DC_WIN_WINDOW_SET_CONTROL 0x730 782 #define CONTROL_CSC_ENABLE (1 << 5) 783 784 #define DC_WINBUF_CROPPED_POINT 0x806 785 #define OFFSET_Y(x) (((x) & 0xffff) << 16) 786 #define OFFSET_X(x) (((x) & 0xffff) << 0) 787 788 #endif /* TEGRA_DC_H */ 789