1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/clk/tegra.h> 12 #include <linux/debugfs.h> 13 14 #include "dc.h" 15 #include "drm.h" 16 #include "gem.h" 17 18 struct tegra_plane { 19 struct drm_plane base; 20 unsigned int index; 21 }; 22 23 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane) 24 { 25 return container_of(plane, struct tegra_plane, base); 26 } 27 28 static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc, 29 struct drm_framebuffer *fb, int crtc_x, 30 int crtc_y, unsigned int crtc_w, 31 unsigned int crtc_h, uint32_t src_x, 32 uint32_t src_y, uint32_t src_w, uint32_t src_h) 33 { 34 struct tegra_plane *p = to_tegra_plane(plane); 35 struct tegra_dc *dc = to_tegra_dc(crtc); 36 struct tegra_dc_window window; 37 unsigned int i; 38 39 memset(&window, 0, sizeof(window)); 40 window.src.x = src_x >> 16; 41 window.src.y = src_y >> 16; 42 window.src.w = src_w >> 16; 43 window.src.h = src_h >> 16; 44 window.dst.x = crtc_x; 45 window.dst.y = crtc_y; 46 window.dst.w = crtc_w; 47 window.dst.h = crtc_h; 48 window.format = tegra_dc_format(fb->pixel_format); 49 window.bits_per_pixel = fb->bits_per_pixel; 50 window.bottom_up = tegra_fb_is_bottom_up(fb); 51 window.tiled = tegra_fb_is_tiled(fb); 52 53 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) { 54 struct tegra_bo *bo = tegra_fb_get_plane(fb, i); 55 56 window.base[i] = bo->paddr + fb->offsets[i]; 57 58 /* 59 * Tegra doesn't support different strides for U and V planes 60 * so we display a warning if the user tries to display a 61 * framebuffer with such a configuration. 62 */ 63 if (i >= 2) { 64 if (fb->pitches[i] != window.stride[1]) 65 DRM_ERROR("unsupported UV-plane configuration\n"); 66 } else { 67 window.stride[i] = fb->pitches[i]; 68 } 69 } 70 71 return tegra_dc_setup_window(dc, p->index, &window); 72 } 73 74 static int tegra_plane_disable(struct drm_plane *plane) 75 { 76 struct tegra_dc *dc = to_tegra_dc(plane->crtc); 77 struct tegra_plane *p = to_tegra_plane(plane); 78 unsigned long value; 79 80 if (!plane->crtc) 81 return 0; 82 83 value = WINDOW_A_SELECT << p->index; 84 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); 85 86 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); 87 value &= ~WIN_ENABLE; 88 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 89 90 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL); 91 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL); 92 93 return 0; 94 } 95 96 static void tegra_plane_destroy(struct drm_plane *plane) 97 { 98 struct tegra_plane *p = to_tegra_plane(plane); 99 100 tegra_plane_disable(plane); 101 drm_plane_cleanup(plane); 102 kfree(p); 103 } 104 105 static const struct drm_plane_funcs tegra_plane_funcs = { 106 .update_plane = tegra_plane_update, 107 .disable_plane = tegra_plane_disable, 108 .destroy = tegra_plane_destroy, 109 }; 110 111 static const uint32_t plane_formats[] = { 112 DRM_FORMAT_XBGR8888, 113 DRM_FORMAT_XRGB8888, 114 DRM_FORMAT_RGB565, 115 DRM_FORMAT_UYVY, 116 DRM_FORMAT_YUV420, 117 DRM_FORMAT_YUV422, 118 }; 119 120 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc) 121 { 122 unsigned int i; 123 int err = 0; 124 125 for (i = 0; i < 2; i++) { 126 struct tegra_plane *plane; 127 128 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 129 if (!plane) 130 return -ENOMEM; 131 132 plane->index = 1 + i; 133 134 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe, 135 &tegra_plane_funcs, plane_formats, 136 ARRAY_SIZE(plane_formats), false); 137 if (err < 0) { 138 kfree(plane); 139 return err; 140 } 141 } 142 143 return 0; 144 } 145 146 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y, 147 struct drm_framebuffer *fb) 148 { 149 unsigned int format = tegra_dc_format(fb->pixel_format); 150 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0); 151 unsigned int h_offset = 0, v_offset = 0; 152 unsigned long value; 153 154 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER); 155 156 value = fb->offsets[0] + y * fb->pitches[0] + 157 x * fb->bits_per_pixel / 8; 158 159 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR); 160 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE); 161 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH); 162 163 if (tegra_fb_is_tiled(fb)) { 164 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 165 DC_WIN_BUFFER_ADDR_MODE_TILE; 166 } else { 167 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 168 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 169 } 170 171 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); 172 173 /* make sure bottom-up buffers are properly displayed */ 174 if (tegra_fb_is_bottom_up(fb)) { 175 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); 176 value |= INVERT_V; 177 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 178 179 v_offset += fb->height - 1; 180 } else { 181 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS); 182 value &= ~INVERT_V; 183 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 184 } 185 186 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); 187 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); 188 189 value = GENERAL_UPDATE | WIN_A_UPDATE; 190 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 191 192 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 193 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 194 195 return 0; 196 } 197 198 void tegra_dc_enable_vblank(struct tegra_dc *dc) 199 { 200 unsigned long value, flags; 201 202 spin_lock_irqsave(&dc->lock, flags); 203 204 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 205 value |= VBLANK_INT; 206 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 207 208 spin_unlock_irqrestore(&dc->lock, flags); 209 } 210 211 void tegra_dc_disable_vblank(struct tegra_dc *dc) 212 { 213 unsigned long value, flags; 214 215 spin_lock_irqsave(&dc->lock, flags); 216 217 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 218 value &= ~VBLANK_INT; 219 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 220 221 spin_unlock_irqrestore(&dc->lock, flags); 222 } 223 224 static void tegra_dc_finish_page_flip(struct tegra_dc *dc) 225 { 226 struct drm_device *drm = dc->base.dev; 227 struct drm_crtc *crtc = &dc->base; 228 unsigned long flags, base; 229 struct tegra_bo *bo; 230 231 if (!dc->event) 232 return; 233 234 bo = tegra_fb_get_plane(crtc->fb, 0); 235 236 /* check if new start address has been latched */ 237 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 238 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR); 239 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 240 241 if (base == bo->paddr + crtc->fb->offsets[0]) { 242 spin_lock_irqsave(&drm->event_lock, flags); 243 drm_send_vblank_event(drm, dc->pipe, dc->event); 244 drm_vblank_put(drm, dc->pipe); 245 dc->event = NULL; 246 spin_unlock_irqrestore(&drm->event_lock, flags); 247 } 248 } 249 250 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file) 251 { 252 struct tegra_dc *dc = to_tegra_dc(crtc); 253 struct drm_device *drm = crtc->dev; 254 unsigned long flags; 255 256 spin_lock_irqsave(&drm->event_lock, flags); 257 258 if (dc->event && dc->event->base.file_priv == file) { 259 dc->event->base.destroy(&dc->event->base); 260 drm_vblank_put(drm, dc->pipe); 261 dc->event = NULL; 262 } 263 264 spin_unlock_irqrestore(&drm->event_lock, flags); 265 } 266 267 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb, 268 struct drm_pending_vblank_event *event, uint32_t page_flip_flags) 269 { 270 struct tegra_dc *dc = to_tegra_dc(crtc); 271 struct drm_device *drm = crtc->dev; 272 273 if (dc->event) 274 return -EBUSY; 275 276 if (event) { 277 event->pipe = dc->pipe; 278 dc->event = event; 279 drm_vblank_get(drm, dc->pipe); 280 } 281 282 tegra_dc_set_base(dc, 0, 0, fb); 283 crtc->fb = fb; 284 285 return 0; 286 } 287 288 static void drm_crtc_clear(struct drm_crtc *crtc) 289 { 290 memset(crtc, 0, sizeof(*crtc)); 291 } 292 293 static void tegra_dc_destroy(struct drm_crtc *crtc) 294 { 295 drm_crtc_cleanup(crtc); 296 drm_crtc_clear(crtc); 297 } 298 299 static const struct drm_crtc_funcs tegra_crtc_funcs = { 300 .page_flip = tegra_dc_page_flip, 301 .set_config = drm_crtc_helper_set_config, 302 .destroy = tegra_dc_destroy, 303 }; 304 305 static void tegra_crtc_disable(struct drm_crtc *crtc) 306 { 307 struct tegra_dc *dc = to_tegra_dc(crtc); 308 struct drm_device *drm = crtc->dev; 309 struct drm_plane *plane; 310 311 list_for_each_entry(plane, &drm->mode_config.plane_list, head) { 312 if (plane->crtc == crtc) { 313 tegra_plane_disable(plane); 314 plane->crtc = NULL; 315 316 if (plane->fb) { 317 drm_framebuffer_unreference(plane->fb); 318 plane->fb = NULL; 319 } 320 } 321 } 322 323 drm_vblank_off(drm, dc->pipe); 324 } 325 326 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc, 327 const struct drm_display_mode *mode, 328 struct drm_display_mode *adjusted) 329 { 330 return true; 331 } 332 333 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 334 unsigned int bpp) 335 { 336 fixed20_12 outf = dfixed_init(out); 337 fixed20_12 inf = dfixed_init(in); 338 u32 dda_inc; 339 int max; 340 341 if (v) 342 max = 15; 343 else { 344 switch (bpp) { 345 case 2: 346 max = 8; 347 break; 348 349 default: 350 WARN_ON_ONCE(1); 351 /* fallthrough */ 352 case 4: 353 max = 4; 354 break; 355 } 356 } 357 358 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 359 inf.full -= dfixed_const(1); 360 361 dda_inc = dfixed_div(inf, outf); 362 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 363 364 return dda_inc; 365 } 366 367 static inline u32 compute_initial_dda(unsigned int in) 368 { 369 fixed20_12 inf = dfixed_init(in); 370 return dfixed_frac(inf); 371 } 372 373 static int tegra_dc_set_timings(struct tegra_dc *dc, 374 struct drm_display_mode *mode) 375 { 376 /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */ 377 unsigned int h_ref_to_sync = 0; 378 unsigned int v_ref_to_sync = 0; 379 unsigned long value; 380 381 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 382 383 value = (v_ref_to_sync << 16) | h_ref_to_sync; 384 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 385 386 value = ((mode->vsync_end - mode->vsync_start) << 16) | 387 ((mode->hsync_end - mode->hsync_start) << 0); 388 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 389 390 value = ((mode->vtotal - mode->vsync_end) << 16) | 391 ((mode->htotal - mode->hsync_end) << 0); 392 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 393 394 value = ((mode->vsync_start - mode->vdisplay) << 16) | 395 ((mode->hsync_start - mode->hdisplay) << 0); 396 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 397 398 value = (mode->vdisplay << 16) | mode->hdisplay; 399 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 400 401 return 0; 402 } 403 404 static int tegra_crtc_setup_clk(struct drm_crtc *crtc, 405 struct drm_display_mode *mode, 406 unsigned long *div) 407 { 408 unsigned long pclk = mode->clock * 1000, rate; 409 struct tegra_dc *dc = to_tegra_dc(crtc); 410 struct tegra_output *output = NULL; 411 struct drm_encoder *encoder; 412 long err; 413 414 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head) 415 if (encoder->crtc == crtc) { 416 output = encoder_to_output(encoder); 417 break; 418 } 419 420 if (!output) 421 return -ENODEV; 422 423 /* 424 * This assumes that the display controller will divide its parent 425 * clock by 2 to generate the pixel clock. 426 */ 427 err = tegra_output_setup_clock(output, dc->clk, pclk * 2); 428 if (err < 0) { 429 dev_err(dc->dev, "failed to setup clock: %ld\n", err); 430 return err; 431 } 432 433 rate = clk_get_rate(dc->clk); 434 *div = (rate * 2 / pclk) - 2; 435 436 DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div); 437 438 return 0; 439 } 440 441 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar) 442 { 443 switch (format) { 444 case WIN_COLOR_DEPTH_YCbCr422: 445 case WIN_COLOR_DEPTH_YUV422: 446 if (planar) 447 *planar = false; 448 449 return true; 450 451 case WIN_COLOR_DEPTH_YCbCr420P: 452 case WIN_COLOR_DEPTH_YUV420P: 453 case WIN_COLOR_DEPTH_YCbCr422P: 454 case WIN_COLOR_DEPTH_YUV422P: 455 case WIN_COLOR_DEPTH_YCbCr422R: 456 case WIN_COLOR_DEPTH_YUV422R: 457 case WIN_COLOR_DEPTH_YCbCr422RA: 458 case WIN_COLOR_DEPTH_YUV422RA: 459 if (planar) 460 *planar = true; 461 462 return true; 463 } 464 465 return false; 466 } 467 468 int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index, 469 const struct tegra_dc_window *window) 470 { 471 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 472 unsigned long value; 473 bool yuv, planar; 474 475 /* 476 * For YUV planar modes, the number of bytes per pixel takes into 477 * account only the luma component and therefore is 1. 478 */ 479 yuv = tegra_dc_format_is_yuv(window->format, &planar); 480 if (!yuv) 481 bpp = window->bits_per_pixel / 8; 482 else 483 bpp = planar ? 1 : 2; 484 485 value = WINDOW_A_SELECT << index; 486 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER); 487 488 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH); 489 tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP); 490 491 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 492 tegra_dc_writel(dc, value, DC_WIN_POSITION); 493 494 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 495 tegra_dc_writel(dc, value, DC_WIN_SIZE); 496 497 h_offset = window->src.x * bpp; 498 v_offset = window->src.y; 499 h_size = window->src.w * bpp; 500 v_size = window->src.h; 501 502 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 503 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE); 504 505 /* 506 * For DDA computations the number of bytes per pixel for YUV planar 507 * modes needs to take into account all Y, U and V components. 508 */ 509 if (yuv && planar) 510 bpp = 2; 511 512 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 513 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 514 515 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 516 tegra_dc_writel(dc, value, DC_WIN_DDA_INC); 517 518 h_dda = compute_initial_dda(window->src.x); 519 v_dda = compute_initial_dda(window->src.y); 520 521 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA); 522 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA); 523 524 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE); 525 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE); 526 527 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR); 528 529 if (yuv && planar) { 530 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U); 531 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V); 532 value = window->stride[1] << 16 | window->stride[0]; 533 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE); 534 } else { 535 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE); 536 } 537 538 if (window->bottom_up) 539 v_offset += window->src.h - 1; 540 541 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET); 542 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET); 543 544 if (window->tiled) { 545 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 546 DC_WIN_BUFFER_ADDR_MODE_TILE; 547 } else { 548 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 549 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 550 } 551 552 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE); 553 554 value = WIN_ENABLE; 555 556 if (yuv) { 557 /* setup default colorspace conversion coefficients */ 558 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF); 559 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB); 560 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR); 561 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR); 562 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG); 563 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG); 564 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB); 565 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB); 566 567 value |= CSC_ENABLE; 568 } else if (window->bits_per_pixel < 24) { 569 value |= COLOR_EXPAND; 570 } 571 572 if (window->bottom_up) 573 value |= INVERT_V; 574 575 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS); 576 577 /* 578 * Disable blending and assume Window A is the bottom-most window, 579 * Window C is the top-most window and Window B is in the middle. 580 */ 581 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY); 582 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN); 583 584 switch (index) { 585 case 0: 586 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X); 587 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); 588 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); 589 break; 590 591 case 1: 592 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); 593 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y); 594 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY); 595 break; 596 597 case 2: 598 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X); 599 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y); 600 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY); 601 break; 602 } 603 604 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL); 605 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL); 606 607 return 0; 608 } 609 610 unsigned int tegra_dc_format(uint32_t format) 611 { 612 switch (format) { 613 case DRM_FORMAT_XBGR8888: 614 return WIN_COLOR_DEPTH_R8G8B8A8; 615 616 case DRM_FORMAT_XRGB8888: 617 return WIN_COLOR_DEPTH_B8G8R8A8; 618 619 case DRM_FORMAT_RGB565: 620 return WIN_COLOR_DEPTH_B5G6R5; 621 622 case DRM_FORMAT_UYVY: 623 return WIN_COLOR_DEPTH_YCbCr422; 624 625 case DRM_FORMAT_YUV420: 626 return WIN_COLOR_DEPTH_YCbCr420P; 627 628 case DRM_FORMAT_YUV422: 629 return WIN_COLOR_DEPTH_YCbCr422P; 630 631 default: 632 break; 633 } 634 635 WARN(1, "unsupported pixel format %u, using default\n", format); 636 return WIN_COLOR_DEPTH_B8G8R8A8; 637 } 638 639 static int tegra_crtc_mode_set(struct drm_crtc *crtc, 640 struct drm_display_mode *mode, 641 struct drm_display_mode *adjusted, 642 int x, int y, struct drm_framebuffer *old_fb) 643 { 644 struct tegra_bo *bo = tegra_fb_get_plane(crtc->fb, 0); 645 struct tegra_dc *dc = to_tegra_dc(crtc); 646 struct tegra_dc_window window; 647 unsigned long div, value; 648 int err; 649 650 drm_vblank_pre_modeset(crtc->dev, dc->pipe); 651 652 err = tegra_crtc_setup_clk(crtc, mode, &div); 653 if (err) { 654 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err); 655 return err; 656 } 657 658 /* program display mode */ 659 tegra_dc_set_timings(dc, mode); 660 661 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL; 662 tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS); 663 664 value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1)); 665 value &= ~LVS_OUTPUT_POLARITY_LOW; 666 value &= ~LHS_OUTPUT_POLARITY_LOW; 667 tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1)); 668 669 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB | 670 DISP_ORDER_RED_BLUE; 671 tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL); 672 673 tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS); 674 675 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1; 676 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 677 678 /* setup window parameters */ 679 memset(&window, 0, sizeof(window)); 680 window.src.x = 0; 681 window.src.y = 0; 682 window.src.w = mode->hdisplay; 683 window.src.h = mode->vdisplay; 684 window.dst.x = 0; 685 window.dst.y = 0; 686 window.dst.w = mode->hdisplay; 687 window.dst.h = mode->vdisplay; 688 window.format = tegra_dc_format(crtc->fb->pixel_format); 689 window.bits_per_pixel = crtc->fb->bits_per_pixel; 690 window.stride[0] = crtc->fb->pitches[0]; 691 window.base[0] = bo->paddr; 692 693 err = tegra_dc_setup_window(dc, 0, &window); 694 if (err < 0) 695 dev_err(dc->dev, "failed to enable root plane\n"); 696 697 return 0; 698 } 699 700 static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, 701 struct drm_framebuffer *old_fb) 702 { 703 struct tegra_dc *dc = to_tegra_dc(crtc); 704 705 return tegra_dc_set_base(dc, x, y, crtc->fb); 706 } 707 708 static void tegra_crtc_prepare(struct drm_crtc *crtc) 709 { 710 struct tegra_dc *dc = to_tegra_dc(crtc); 711 unsigned int syncpt; 712 unsigned long value; 713 714 /* hardware initialization */ 715 tegra_periph_reset_deassert(dc->clk); 716 usleep_range(10000, 20000); 717 718 if (dc->pipe) 719 syncpt = SYNCPT_VBLANK1; 720 else 721 syncpt = SYNCPT_VBLANK0; 722 723 /* initialize display controller */ 724 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 725 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC); 726 727 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT; 728 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 729 730 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 731 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 732 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 733 734 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 735 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 736 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 737 738 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 739 value |= DISP_CTRL_MODE_C_DISPLAY; 740 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 741 742 /* initialize timer */ 743 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 744 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 745 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 746 747 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 748 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 749 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 750 751 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 752 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 753 754 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT; 755 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 756 } 757 758 static void tegra_crtc_commit(struct drm_crtc *crtc) 759 { 760 struct tegra_dc *dc = to_tegra_dc(crtc); 761 unsigned long value; 762 763 value = GENERAL_UPDATE | WIN_A_UPDATE; 764 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 765 766 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ; 767 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 768 769 drm_vblank_post_modeset(crtc->dev, dc->pipe); 770 } 771 772 static void tegra_crtc_load_lut(struct drm_crtc *crtc) 773 { 774 } 775 776 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 777 .disable = tegra_crtc_disable, 778 .mode_fixup = tegra_crtc_mode_fixup, 779 .mode_set = tegra_crtc_mode_set, 780 .mode_set_base = tegra_crtc_mode_set_base, 781 .prepare = tegra_crtc_prepare, 782 .commit = tegra_crtc_commit, 783 .load_lut = tegra_crtc_load_lut, 784 }; 785 786 static irqreturn_t tegra_dc_irq(int irq, void *data) 787 { 788 struct tegra_dc *dc = data; 789 unsigned long status; 790 791 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 792 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 793 794 if (status & FRAME_END_INT) { 795 /* 796 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 797 */ 798 } 799 800 if (status & VBLANK_INT) { 801 /* 802 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 803 */ 804 drm_handle_vblank(dc->base.dev, dc->pipe); 805 tegra_dc_finish_page_flip(dc); 806 } 807 808 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 809 /* 810 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 811 */ 812 } 813 814 return IRQ_HANDLED; 815 } 816 817 static int tegra_dc_show_regs(struct seq_file *s, void *data) 818 { 819 struct drm_info_node *node = s->private; 820 struct tegra_dc *dc = node->info_ent->data; 821 822 #define DUMP_REG(name) \ 823 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \ 824 tegra_dc_readl(dc, name)) 825 826 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT); 827 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 828 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR); 829 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT); 830 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL); 831 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR); 832 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT); 833 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL); 834 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR); 835 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT); 836 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL); 837 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR); 838 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC); 839 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0); 840 DUMP_REG(DC_CMD_DISPLAY_COMMAND); 841 DUMP_REG(DC_CMD_SIGNAL_RAISE); 842 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL); 843 DUMP_REG(DC_CMD_INT_STATUS); 844 DUMP_REG(DC_CMD_INT_MASK); 845 DUMP_REG(DC_CMD_INT_ENABLE); 846 DUMP_REG(DC_CMD_INT_TYPE); 847 DUMP_REG(DC_CMD_INT_POLARITY); 848 DUMP_REG(DC_CMD_SIGNAL_RAISE1); 849 DUMP_REG(DC_CMD_SIGNAL_RAISE2); 850 DUMP_REG(DC_CMD_SIGNAL_RAISE3); 851 DUMP_REG(DC_CMD_STATE_ACCESS); 852 DUMP_REG(DC_CMD_STATE_CONTROL); 853 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER); 854 DUMP_REG(DC_CMD_REG_ACT_CONTROL); 855 DUMP_REG(DC_COM_CRC_CONTROL); 856 DUMP_REG(DC_COM_CRC_CHECKSUM); 857 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0)); 858 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1)); 859 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2)); 860 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3)); 861 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0)); 862 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1)); 863 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2)); 864 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3)); 865 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0)); 866 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1)); 867 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2)); 868 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3)); 869 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0)); 870 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1)); 871 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2)); 872 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3)); 873 DUMP_REG(DC_COM_PIN_INPUT_DATA(0)); 874 DUMP_REG(DC_COM_PIN_INPUT_DATA(1)); 875 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0)); 876 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1)); 877 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2)); 878 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3)); 879 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4)); 880 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5)); 881 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6)); 882 DUMP_REG(DC_COM_PIN_MISC_CONTROL); 883 DUMP_REG(DC_COM_PIN_PM0_CONTROL); 884 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE); 885 DUMP_REG(DC_COM_PIN_PM1_CONTROL); 886 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE); 887 DUMP_REG(DC_COM_SPI_CONTROL); 888 DUMP_REG(DC_COM_SPI_START_BYTE); 889 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB); 890 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD); 891 DUMP_REG(DC_COM_HSPI_CS_DC); 892 DUMP_REG(DC_COM_SCRATCH_REGISTER_A); 893 DUMP_REG(DC_COM_SCRATCH_REGISTER_B); 894 DUMP_REG(DC_COM_GPIO_CTRL); 895 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER); 896 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED); 897 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0); 898 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1); 899 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS); 900 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY); 901 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 902 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS); 903 DUMP_REG(DC_DISP_REF_TO_SYNC); 904 DUMP_REG(DC_DISP_SYNC_WIDTH); 905 DUMP_REG(DC_DISP_BACK_PORCH); 906 DUMP_REG(DC_DISP_ACTIVE); 907 DUMP_REG(DC_DISP_FRONT_PORCH); 908 DUMP_REG(DC_DISP_H_PULSE0_CONTROL); 909 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A); 910 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B); 911 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C); 912 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D); 913 DUMP_REG(DC_DISP_H_PULSE1_CONTROL); 914 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A); 915 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B); 916 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C); 917 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D); 918 DUMP_REG(DC_DISP_H_PULSE2_CONTROL); 919 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A); 920 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B); 921 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C); 922 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D); 923 DUMP_REG(DC_DISP_V_PULSE0_CONTROL); 924 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A); 925 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B); 926 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C); 927 DUMP_REG(DC_DISP_V_PULSE1_CONTROL); 928 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A); 929 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B); 930 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C); 931 DUMP_REG(DC_DISP_V_PULSE2_CONTROL); 932 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A); 933 DUMP_REG(DC_DISP_V_PULSE3_CONTROL); 934 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A); 935 DUMP_REG(DC_DISP_M0_CONTROL); 936 DUMP_REG(DC_DISP_M1_CONTROL); 937 DUMP_REG(DC_DISP_DI_CONTROL); 938 DUMP_REG(DC_DISP_PP_CONTROL); 939 DUMP_REG(DC_DISP_PP_SELECT_A); 940 DUMP_REG(DC_DISP_PP_SELECT_B); 941 DUMP_REG(DC_DISP_PP_SELECT_C); 942 DUMP_REG(DC_DISP_PP_SELECT_D); 943 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL); 944 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL); 945 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL); 946 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS); 947 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS); 948 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS); 949 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS); 950 DUMP_REG(DC_DISP_BORDER_COLOR); 951 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER); 952 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER); 953 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER); 954 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER); 955 DUMP_REG(DC_DISP_CURSOR_FOREGROUND); 956 DUMP_REG(DC_DISP_CURSOR_BACKGROUND); 957 DUMP_REG(DC_DISP_CURSOR_START_ADDR); 958 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS); 959 DUMP_REG(DC_DISP_CURSOR_POSITION); 960 DUMP_REG(DC_DISP_CURSOR_POSITION_NS); 961 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL); 962 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A); 963 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B); 964 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C); 965 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D); 966 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL); 967 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST); 968 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST); 969 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST); 970 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST); 971 DUMP_REG(DC_DISP_DAC_CRT_CTRL); 972 DUMP_REG(DC_DISP_DISP_MISC_CONTROL); 973 DUMP_REG(DC_DISP_SD_CONTROL); 974 DUMP_REG(DC_DISP_SD_CSC_COEFF); 975 DUMP_REG(DC_DISP_SD_LUT(0)); 976 DUMP_REG(DC_DISP_SD_LUT(1)); 977 DUMP_REG(DC_DISP_SD_LUT(2)); 978 DUMP_REG(DC_DISP_SD_LUT(3)); 979 DUMP_REG(DC_DISP_SD_LUT(4)); 980 DUMP_REG(DC_DISP_SD_LUT(5)); 981 DUMP_REG(DC_DISP_SD_LUT(6)); 982 DUMP_REG(DC_DISP_SD_LUT(7)); 983 DUMP_REG(DC_DISP_SD_LUT(8)); 984 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL); 985 DUMP_REG(DC_DISP_DC_PIXEL_COUNT); 986 DUMP_REG(DC_DISP_SD_HISTOGRAM(0)); 987 DUMP_REG(DC_DISP_SD_HISTOGRAM(1)); 988 DUMP_REG(DC_DISP_SD_HISTOGRAM(2)); 989 DUMP_REG(DC_DISP_SD_HISTOGRAM(3)); 990 DUMP_REG(DC_DISP_SD_HISTOGRAM(4)); 991 DUMP_REG(DC_DISP_SD_HISTOGRAM(5)); 992 DUMP_REG(DC_DISP_SD_HISTOGRAM(6)); 993 DUMP_REG(DC_DISP_SD_HISTOGRAM(7)); 994 DUMP_REG(DC_DISP_SD_BL_TF(0)); 995 DUMP_REG(DC_DISP_SD_BL_TF(1)); 996 DUMP_REG(DC_DISP_SD_BL_TF(2)); 997 DUMP_REG(DC_DISP_SD_BL_TF(3)); 998 DUMP_REG(DC_DISP_SD_BL_CONTROL); 999 DUMP_REG(DC_DISP_SD_HW_K_VALUES); 1000 DUMP_REG(DC_DISP_SD_MAN_K_VALUES); 1001 DUMP_REG(DC_WIN_WIN_OPTIONS); 1002 DUMP_REG(DC_WIN_BYTE_SWAP); 1003 DUMP_REG(DC_WIN_BUFFER_CONTROL); 1004 DUMP_REG(DC_WIN_COLOR_DEPTH); 1005 DUMP_REG(DC_WIN_POSITION); 1006 DUMP_REG(DC_WIN_SIZE); 1007 DUMP_REG(DC_WIN_PRESCALED_SIZE); 1008 DUMP_REG(DC_WIN_H_INITIAL_DDA); 1009 DUMP_REG(DC_WIN_V_INITIAL_DDA); 1010 DUMP_REG(DC_WIN_DDA_INC); 1011 DUMP_REG(DC_WIN_LINE_STRIDE); 1012 DUMP_REG(DC_WIN_BUF_STRIDE); 1013 DUMP_REG(DC_WIN_UV_BUF_STRIDE); 1014 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE); 1015 DUMP_REG(DC_WIN_DV_CONTROL); 1016 DUMP_REG(DC_WIN_BLEND_NOKEY); 1017 DUMP_REG(DC_WIN_BLEND_1WIN); 1018 DUMP_REG(DC_WIN_BLEND_2WIN_X); 1019 DUMP_REG(DC_WIN_BLEND_2WIN_Y); 1020 DUMP_REG(DC_WIN_BLEND_3WIN_XY); 1021 DUMP_REG(DC_WIN_HP_FETCH_CONTROL); 1022 DUMP_REG(DC_WINBUF_START_ADDR); 1023 DUMP_REG(DC_WINBUF_START_ADDR_NS); 1024 DUMP_REG(DC_WINBUF_START_ADDR_U); 1025 DUMP_REG(DC_WINBUF_START_ADDR_U_NS); 1026 DUMP_REG(DC_WINBUF_START_ADDR_V); 1027 DUMP_REG(DC_WINBUF_START_ADDR_V_NS); 1028 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET); 1029 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS); 1030 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET); 1031 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS); 1032 DUMP_REG(DC_WINBUF_UFLOW_STATUS); 1033 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS); 1034 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS); 1035 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS); 1036 1037 #undef DUMP_REG 1038 1039 return 0; 1040 } 1041 1042 static struct drm_info_list debugfs_files[] = { 1043 { "regs", tegra_dc_show_regs, 0, NULL }, 1044 }; 1045 1046 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor) 1047 { 1048 unsigned int i; 1049 char *name; 1050 int err; 1051 1052 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe); 1053 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root); 1054 kfree(name); 1055 1056 if (!dc->debugfs) 1057 return -ENOMEM; 1058 1059 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1060 GFP_KERNEL); 1061 if (!dc->debugfs_files) { 1062 err = -ENOMEM; 1063 goto remove; 1064 } 1065 1066 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++) 1067 dc->debugfs_files[i].data = dc; 1068 1069 err = drm_debugfs_create_files(dc->debugfs_files, 1070 ARRAY_SIZE(debugfs_files), 1071 dc->debugfs, minor); 1072 if (err < 0) 1073 goto free; 1074 1075 dc->minor = minor; 1076 1077 return 0; 1078 1079 free: 1080 kfree(dc->debugfs_files); 1081 dc->debugfs_files = NULL; 1082 remove: 1083 debugfs_remove(dc->debugfs); 1084 dc->debugfs = NULL; 1085 1086 return err; 1087 } 1088 1089 static int tegra_dc_debugfs_exit(struct tegra_dc *dc) 1090 { 1091 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files), 1092 dc->minor); 1093 dc->minor = NULL; 1094 1095 kfree(dc->debugfs_files); 1096 dc->debugfs_files = NULL; 1097 1098 debugfs_remove(dc->debugfs); 1099 dc->debugfs = NULL; 1100 1101 return 0; 1102 } 1103 1104 static int tegra_dc_init(struct host1x_client *client) 1105 { 1106 struct tegra_drm *tegra = dev_get_drvdata(client->parent); 1107 struct tegra_dc *dc = host1x_client_to_dc(client); 1108 int err; 1109 1110 dc->pipe = tegra->drm->mode_config.num_crtc; 1111 1112 drm_crtc_init(tegra->drm, &dc->base, &tegra_crtc_funcs); 1113 drm_mode_crtc_set_gamma_size(&dc->base, 256); 1114 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 1115 1116 err = tegra_dc_rgb_init(tegra->drm, dc); 1117 if (err < 0 && err != -ENODEV) { 1118 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 1119 return err; 1120 } 1121 1122 err = tegra_dc_add_planes(tegra->drm, dc); 1123 if (err < 0) 1124 return err; 1125 1126 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1127 err = tegra_dc_debugfs_init(dc, tegra->drm->primary); 1128 if (err < 0) 1129 dev_err(dc->dev, "debugfs setup failed: %d\n", err); 1130 } 1131 1132 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 1133 dev_name(dc->dev), dc); 1134 if (err < 0) { 1135 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 1136 err); 1137 return err; 1138 } 1139 1140 return 0; 1141 } 1142 1143 static int tegra_dc_exit(struct host1x_client *client) 1144 { 1145 struct tegra_dc *dc = host1x_client_to_dc(client); 1146 int err; 1147 1148 devm_free_irq(dc->dev, dc->irq, dc); 1149 1150 if (IS_ENABLED(CONFIG_DEBUG_FS)) { 1151 err = tegra_dc_debugfs_exit(dc); 1152 if (err < 0) 1153 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err); 1154 } 1155 1156 err = tegra_dc_rgb_exit(dc); 1157 if (err) { 1158 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 1159 return err; 1160 } 1161 1162 return 0; 1163 } 1164 1165 static const struct host1x_client_ops dc_client_ops = { 1166 .init = tegra_dc_init, 1167 .exit = tegra_dc_exit, 1168 }; 1169 1170 static int tegra_dc_probe(struct platform_device *pdev) 1171 { 1172 struct resource *regs; 1173 struct tegra_dc *dc; 1174 int err; 1175 1176 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 1177 if (!dc) 1178 return -ENOMEM; 1179 1180 spin_lock_init(&dc->lock); 1181 INIT_LIST_HEAD(&dc->list); 1182 dc->dev = &pdev->dev; 1183 1184 dc->clk = devm_clk_get(&pdev->dev, NULL); 1185 if (IS_ERR(dc->clk)) { 1186 dev_err(&pdev->dev, "failed to get clock\n"); 1187 return PTR_ERR(dc->clk); 1188 } 1189 1190 err = clk_prepare_enable(dc->clk); 1191 if (err < 0) 1192 return err; 1193 1194 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1195 dc->regs = devm_ioremap_resource(&pdev->dev, regs); 1196 if (IS_ERR(dc->regs)) 1197 return PTR_ERR(dc->regs); 1198 1199 dc->irq = platform_get_irq(pdev, 0); 1200 if (dc->irq < 0) { 1201 dev_err(&pdev->dev, "failed to get IRQ\n"); 1202 return -ENXIO; 1203 } 1204 1205 INIT_LIST_HEAD(&dc->client.list); 1206 dc->client.ops = &dc_client_ops; 1207 dc->client.dev = &pdev->dev; 1208 1209 err = tegra_dc_rgb_probe(dc); 1210 if (err < 0 && err != -ENODEV) { 1211 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); 1212 return err; 1213 } 1214 1215 err = host1x_client_register(&dc->client); 1216 if (err < 0) { 1217 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 1218 err); 1219 return err; 1220 } 1221 1222 platform_set_drvdata(pdev, dc); 1223 1224 return 0; 1225 } 1226 1227 static int tegra_dc_remove(struct platform_device *pdev) 1228 { 1229 struct tegra_dc *dc = platform_get_drvdata(pdev); 1230 int err; 1231 1232 err = host1x_client_unregister(&dc->client); 1233 if (err < 0) { 1234 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 1235 err); 1236 return err; 1237 } 1238 1239 err = tegra_dc_rgb_remove(dc); 1240 if (err < 0) { 1241 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 1242 return err; 1243 } 1244 1245 clk_disable_unprepare(dc->clk); 1246 1247 return 0; 1248 } 1249 1250 static struct of_device_id tegra_dc_of_match[] = { 1251 { .compatible = "nvidia,tegra30-dc", }, 1252 { .compatible = "nvidia,tegra20-dc", }, 1253 { }, 1254 }; 1255 1256 struct platform_driver tegra_dc_driver = { 1257 .driver = { 1258 .name = "tegra-dc", 1259 .owner = THIS_MODULE, 1260 .of_match_table = tegra_dc_of_match, 1261 }, 1262 .probe = tegra_dc_probe, 1263 .remove = tegra_dc_remove, 1264 }; 1265