1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/iommu.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 17 #include <soc/tegra/pmc.h> 18 19 #include "dc.h" 20 #include "drm.h" 21 #include "gem.h" 22 #include "hub.h" 23 #include "plane.h" 24 25 #include <drm/drm_atomic.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_plane_helper.h> 28 29 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 30 struct drm_crtc_state *state); 31 32 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 33 { 34 stats->frames = 0; 35 stats->vblank = 0; 36 stats->underflow = 0; 37 stats->overflow = 0; 38 } 39 40 /* Reads the active copy of a register. */ 41 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 42 { 43 u32 value; 44 45 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 46 value = tegra_dc_readl(dc, offset); 47 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 48 49 return value; 50 } 51 52 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 53 unsigned int offset) 54 { 55 if (offset >= 0x500 && offset <= 0x638) { 56 offset = 0x000 + (offset - 0x500); 57 return plane->offset + offset; 58 } 59 60 if (offset >= 0x700 && offset <= 0x719) { 61 offset = 0x180 + (offset - 0x700); 62 return plane->offset + offset; 63 } 64 65 if (offset >= 0x800 && offset <= 0x839) { 66 offset = 0x1c0 + (offset - 0x800); 67 return plane->offset + offset; 68 } 69 70 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 71 72 return plane->offset + offset; 73 } 74 75 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 76 unsigned int offset) 77 { 78 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 79 } 80 81 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 82 unsigned int offset) 83 { 84 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 85 } 86 87 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 88 { 89 struct device_node *np = dc->dev->of_node; 90 struct of_phandle_iterator it; 91 int err; 92 93 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 94 if (it.node == dev->of_node) 95 return true; 96 97 return false; 98 } 99 100 /* 101 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 102 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 103 * Latching happens mmediately if the display controller is in STOP mode or 104 * on the next frame boundary otherwise. 105 * 106 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 107 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 108 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 109 * into the ACTIVE copy, either immediately if the display controller is in 110 * STOP mode, or at the next frame boundary otherwise. 111 */ 112 void tegra_dc_commit(struct tegra_dc *dc) 113 { 114 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 115 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 116 } 117 118 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 119 unsigned int bpp) 120 { 121 fixed20_12 outf = dfixed_init(out); 122 fixed20_12 inf = dfixed_init(in); 123 u32 dda_inc; 124 int max; 125 126 if (v) 127 max = 15; 128 else { 129 switch (bpp) { 130 case 2: 131 max = 8; 132 break; 133 134 default: 135 WARN_ON_ONCE(1); 136 /* fallthrough */ 137 case 4: 138 max = 4; 139 break; 140 } 141 } 142 143 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 144 inf.full -= dfixed_const(1); 145 146 dda_inc = dfixed_div(inf, outf); 147 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 148 149 return dda_inc; 150 } 151 152 static inline u32 compute_initial_dda(unsigned int in) 153 { 154 fixed20_12 inf = dfixed_init(in); 155 return dfixed_frac(inf); 156 } 157 158 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 159 { 160 u32 background[3] = { 161 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 162 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 164 }; 165 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 166 BLEND_COLOR_KEY_NONE; 167 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 168 struct tegra_plane_state *state; 169 u32 blending[2]; 170 unsigned int i; 171 172 /* disable blending for non-overlapping case */ 173 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 174 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 175 176 state = to_tegra_plane_state(plane->base.state); 177 178 if (state->opaque) { 179 /* 180 * Since custom fix-weight blending isn't utilized and weight 181 * of top window is set to max, we can enforce dependent 182 * blending which in this case results in transparent bottom 183 * window if top window is opaque and if top window enables 184 * alpha blending, then bottom window is getting alpha value 185 * of 1 minus the sum of alpha components of the overlapping 186 * plane. 187 */ 188 background[0] |= BLEND_CONTROL_DEPENDENT; 189 background[1] |= BLEND_CONTROL_DEPENDENT; 190 191 /* 192 * The region where three windows overlap is the intersection 193 * of the two regions where two windows overlap. It contributes 194 * to the area if all of the windows on top of it have an alpha 195 * component. 196 */ 197 switch (state->base.normalized_zpos) { 198 case 0: 199 if (state->blending[0].alpha && 200 state->blending[1].alpha) 201 background[2] |= BLEND_CONTROL_DEPENDENT; 202 break; 203 204 case 1: 205 background[2] |= BLEND_CONTROL_DEPENDENT; 206 break; 207 } 208 } else { 209 /* 210 * Enable alpha blending if pixel format has an alpha 211 * component. 212 */ 213 foreground |= BLEND_CONTROL_ALPHA; 214 215 /* 216 * If any of the windows on top of this window is opaque, it 217 * will completely conceal this window within that area. If 218 * top window has an alpha component, it is blended over the 219 * bottom window. 220 */ 221 for (i = 0; i < 2; i++) { 222 if (state->blending[i].alpha && 223 state->blending[i].top) 224 background[i] |= BLEND_CONTROL_DEPENDENT; 225 } 226 227 switch (state->base.normalized_zpos) { 228 case 0: 229 if (state->blending[0].alpha && 230 state->blending[1].alpha) 231 background[2] |= BLEND_CONTROL_DEPENDENT; 232 break; 233 234 case 1: 235 /* 236 * When both middle and topmost windows have an alpha, 237 * these windows a mixed together and then the result 238 * is blended over the bottom window. 239 */ 240 if (state->blending[0].alpha && 241 state->blending[0].top) 242 background[2] |= BLEND_CONTROL_ALPHA; 243 244 if (state->blending[1].alpha && 245 state->blending[1].top) 246 background[2] |= BLEND_CONTROL_ALPHA; 247 break; 248 } 249 } 250 251 switch (state->base.normalized_zpos) { 252 case 0: 253 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 254 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 255 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 256 break; 257 258 case 1: 259 /* 260 * If window B / C is topmost, then X / Y registers are 261 * matching the order of blending[...] state indices, 262 * otherwise a swap is required. 263 */ 264 if (!state->blending[0].top && state->blending[1].top) { 265 blending[0] = foreground; 266 blending[1] = background[1]; 267 } else { 268 blending[0] = background[0]; 269 blending[1] = foreground; 270 } 271 272 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X); 273 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y); 274 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 275 break; 276 277 case 2: 278 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 279 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 281 break; 282 } 283 } 284 285 static void tegra_plane_setup_blending(struct tegra_plane *plane, 286 const struct tegra_dc_window *window) 287 { 288 u32 value; 289 290 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 291 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 292 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 293 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 294 295 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 296 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 297 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 298 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 299 300 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 301 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 302 } 303 304 static bool 305 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, 306 const struct tegra_dc_window *window) 307 { 308 struct tegra_dc *dc = plane->dc; 309 310 if (window->src.w == window->dst.w) 311 return false; 312 313 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 314 return false; 315 316 return true; 317 } 318 319 static bool 320 tegra_plane_use_vertical_filtering(struct tegra_plane *plane, 321 const struct tegra_dc_window *window) 322 { 323 struct tegra_dc *dc = plane->dc; 324 325 if (window->src.h == window->dst.h) 326 return false; 327 328 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 329 return false; 330 331 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) 332 return false; 333 334 return true; 335 } 336 337 static void tegra_dc_setup_window(struct tegra_plane *plane, 338 const struct tegra_dc_window *window) 339 { 340 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 341 struct tegra_dc *dc = plane->dc; 342 bool yuv, planar; 343 u32 value; 344 345 /* 346 * For YUV planar modes, the number of bytes per pixel takes into 347 * account only the luma component and therefore is 1. 348 */ 349 yuv = tegra_plane_format_is_yuv(window->format, &planar); 350 if (!yuv) 351 bpp = window->bits_per_pixel / 8; 352 else 353 bpp = planar ? 1 : 2; 354 355 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 356 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 357 358 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 359 tegra_plane_writel(plane, value, DC_WIN_POSITION); 360 361 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 362 tegra_plane_writel(plane, value, DC_WIN_SIZE); 363 364 h_offset = window->src.x * bpp; 365 v_offset = window->src.y; 366 h_size = window->src.w * bpp; 367 v_size = window->src.h; 368 369 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 370 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 371 372 /* 373 * For DDA computations the number of bytes per pixel for YUV planar 374 * modes needs to take into account all Y, U and V components. 375 */ 376 if (yuv && planar) 377 bpp = 2; 378 379 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 380 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 381 382 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 383 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 384 385 h_dda = compute_initial_dda(window->src.x); 386 v_dda = compute_initial_dda(window->src.y); 387 388 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 389 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 390 391 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 392 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 393 394 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 395 396 if (yuv && planar) { 397 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 398 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 399 value = window->stride[1] << 16 | window->stride[0]; 400 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 401 } else { 402 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 403 } 404 405 if (window->bottom_up) 406 v_offset += window->src.h - 1; 407 408 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 409 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 410 411 if (dc->soc->supports_block_linear) { 412 unsigned long height = window->tiling.value; 413 414 switch (window->tiling.mode) { 415 case TEGRA_BO_TILING_MODE_PITCH: 416 value = DC_WINBUF_SURFACE_KIND_PITCH; 417 break; 418 419 case TEGRA_BO_TILING_MODE_TILED: 420 value = DC_WINBUF_SURFACE_KIND_TILED; 421 break; 422 423 case TEGRA_BO_TILING_MODE_BLOCK: 424 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 425 DC_WINBUF_SURFACE_KIND_BLOCK; 426 break; 427 } 428 429 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 430 } else { 431 switch (window->tiling.mode) { 432 case TEGRA_BO_TILING_MODE_PITCH: 433 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 434 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 435 break; 436 437 case TEGRA_BO_TILING_MODE_TILED: 438 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 439 DC_WIN_BUFFER_ADDR_MODE_TILE; 440 break; 441 442 case TEGRA_BO_TILING_MODE_BLOCK: 443 /* 444 * No need to handle this here because ->atomic_check 445 * will already have filtered it out. 446 */ 447 break; 448 } 449 450 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 451 } 452 453 value = WIN_ENABLE; 454 455 if (yuv) { 456 /* setup default colorspace conversion coefficients */ 457 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 458 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 459 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 460 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 461 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 462 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 463 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 464 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 465 466 value |= CSC_ENABLE; 467 } else if (window->bits_per_pixel < 24) { 468 value |= COLOR_EXPAND; 469 } 470 471 if (window->bottom_up) 472 value |= V_DIRECTION; 473 474 if (tegra_plane_use_horizontal_filtering(plane, window)) { 475 /* 476 * Enable horizontal 6-tap filter and set filtering 477 * coefficients to the default values defined in TRM. 478 */ 479 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0)); 480 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1)); 481 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2)); 482 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3)); 483 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4)); 484 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5)); 485 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6)); 486 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7)); 487 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8)); 488 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9)); 489 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10)); 490 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11)); 491 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12)); 492 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13)); 493 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14)); 494 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15)); 495 496 value |= H_FILTER; 497 } 498 499 if (tegra_plane_use_vertical_filtering(plane, window)) { 500 unsigned int i, k; 501 502 /* 503 * Enable vertical 2-tap filter and set filtering 504 * coefficients to the default values defined in TRM. 505 */ 506 for (i = 0, k = 128; i < 16; i++, k -= 8) 507 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); 508 509 value |= V_FILTER; 510 } 511 512 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 513 514 if (dc->soc->has_legacy_blending) 515 tegra_plane_setup_blending_legacy(plane); 516 else 517 tegra_plane_setup_blending(plane, window); 518 } 519 520 static const u32 tegra20_primary_formats[] = { 521 DRM_FORMAT_ARGB4444, 522 DRM_FORMAT_ARGB1555, 523 DRM_FORMAT_RGB565, 524 DRM_FORMAT_RGBA5551, 525 DRM_FORMAT_ABGR8888, 526 DRM_FORMAT_ARGB8888, 527 /* non-native formats */ 528 DRM_FORMAT_XRGB1555, 529 DRM_FORMAT_RGBX5551, 530 DRM_FORMAT_XBGR8888, 531 DRM_FORMAT_XRGB8888, 532 }; 533 534 static const u64 tegra20_modifiers[] = { 535 DRM_FORMAT_MOD_LINEAR, 536 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 537 DRM_FORMAT_MOD_INVALID 538 }; 539 540 static const u32 tegra114_primary_formats[] = { 541 DRM_FORMAT_ARGB4444, 542 DRM_FORMAT_ARGB1555, 543 DRM_FORMAT_RGB565, 544 DRM_FORMAT_RGBA5551, 545 DRM_FORMAT_ABGR8888, 546 DRM_FORMAT_ARGB8888, 547 /* new on Tegra114 */ 548 DRM_FORMAT_ABGR4444, 549 DRM_FORMAT_ABGR1555, 550 DRM_FORMAT_BGRA5551, 551 DRM_FORMAT_XRGB1555, 552 DRM_FORMAT_RGBX5551, 553 DRM_FORMAT_XBGR1555, 554 DRM_FORMAT_BGRX5551, 555 DRM_FORMAT_BGR565, 556 DRM_FORMAT_BGRA8888, 557 DRM_FORMAT_RGBA8888, 558 DRM_FORMAT_XRGB8888, 559 DRM_FORMAT_XBGR8888, 560 }; 561 562 static const u32 tegra124_primary_formats[] = { 563 DRM_FORMAT_ARGB4444, 564 DRM_FORMAT_ARGB1555, 565 DRM_FORMAT_RGB565, 566 DRM_FORMAT_RGBA5551, 567 DRM_FORMAT_ABGR8888, 568 DRM_FORMAT_ARGB8888, 569 /* new on Tegra114 */ 570 DRM_FORMAT_ABGR4444, 571 DRM_FORMAT_ABGR1555, 572 DRM_FORMAT_BGRA5551, 573 DRM_FORMAT_XRGB1555, 574 DRM_FORMAT_RGBX5551, 575 DRM_FORMAT_XBGR1555, 576 DRM_FORMAT_BGRX5551, 577 DRM_FORMAT_BGR565, 578 DRM_FORMAT_BGRA8888, 579 DRM_FORMAT_RGBA8888, 580 DRM_FORMAT_XRGB8888, 581 DRM_FORMAT_XBGR8888, 582 /* new on Tegra124 */ 583 DRM_FORMAT_RGBX8888, 584 DRM_FORMAT_BGRX8888, 585 }; 586 587 static const u64 tegra124_modifiers[] = { 588 DRM_FORMAT_MOD_LINEAR, 589 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 590 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 591 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 592 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 593 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 594 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 595 DRM_FORMAT_MOD_INVALID 596 }; 597 598 static int tegra_plane_atomic_check(struct drm_plane *plane, 599 struct drm_plane_state *state) 600 { 601 struct tegra_plane_state *plane_state = to_tegra_plane_state(state); 602 unsigned int rotation = DRM_MODE_ROTATE_0 | DRM_MODE_REFLECT_Y; 603 struct tegra_bo_tiling *tiling = &plane_state->tiling; 604 struct tegra_plane *tegra = to_tegra_plane(plane); 605 struct tegra_dc *dc = to_tegra_dc(state->crtc); 606 int err; 607 608 /* no need for further checks if the plane is being disabled */ 609 if (!state->crtc) 610 return 0; 611 612 err = tegra_plane_format(state->fb->format->format, 613 &plane_state->format, 614 &plane_state->swap); 615 if (err < 0) 616 return err; 617 618 /* 619 * Tegra20 and Tegra30 are special cases here because they support 620 * only variants of specific formats with an alpha component, but not 621 * the corresponding opaque formats. However, the opaque formats can 622 * be emulated by disabling alpha blending for the plane. 623 */ 624 if (dc->soc->has_legacy_blending) { 625 err = tegra_plane_setup_legacy_state(tegra, plane_state); 626 if (err < 0) 627 return err; 628 } 629 630 err = tegra_fb_get_tiling(state->fb, tiling); 631 if (err < 0) 632 return err; 633 634 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 635 !dc->soc->supports_block_linear) { 636 DRM_ERROR("hardware doesn't support block linear mode\n"); 637 return -EINVAL; 638 } 639 640 rotation = drm_rotation_simplify(state->rotation, rotation); 641 642 if (rotation & DRM_MODE_REFLECT_Y) 643 plane_state->bottom_up = true; 644 else 645 plane_state->bottom_up = false; 646 647 /* 648 * Tegra doesn't support different strides for U and V planes so we 649 * error out if the user tries to display a framebuffer with such a 650 * configuration. 651 */ 652 if (state->fb->format->num_planes > 2) { 653 if (state->fb->pitches[2] != state->fb->pitches[1]) { 654 DRM_ERROR("unsupported UV-plane configuration\n"); 655 return -EINVAL; 656 } 657 } 658 659 err = tegra_plane_state_add(tegra, state); 660 if (err < 0) 661 return err; 662 663 return 0; 664 } 665 666 static void tegra_plane_atomic_disable(struct drm_plane *plane, 667 struct drm_plane_state *old_state) 668 { 669 struct tegra_plane *p = to_tegra_plane(plane); 670 u32 value; 671 672 /* rien ne va plus */ 673 if (!old_state || !old_state->crtc) 674 return; 675 676 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 677 value &= ~WIN_ENABLE; 678 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 679 } 680 681 static void tegra_plane_atomic_update(struct drm_plane *plane, 682 struct drm_plane_state *old_state) 683 { 684 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); 685 struct drm_framebuffer *fb = plane->state->fb; 686 struct tegra_plane *p = to_tegra_plane(plane); 687 struct tegra_dc_window window; 688 unsigned int i; 689 690 /* rien ne va plus */ 691 if (!plane->state->crtc || !plane->state->fb) 692 return; 693 694 if (!plane->state->visible) 695 return tegra_plane_atomic_disable(plane, old_state); 696 697 memset(&window, 0, sizeof(window)); 698 window.src.x = plane->state->src.x1 >> 16; 699 window.src.y = plane->state->src.y1 >> 16; 700 window.src.w = drm_rect_width(&plane->state->src) >> 16; 701 window.src.h = drm_rect_height(&plane->state->src) >> 16; 702 window.dst.x = plane->state->dst.x1; 703 window.dst.y = plane->state->dst.y1; 704 window.dst.w = drm_rect_width(&plane->state->dst); 705 window.dst.h = drm_rect_height(&plane->state->dst); 706 window.bits_per_pixel = fb->format->cpp[0] * 8; 707 window.bottom_up = tegra_fb_is_bottom_up(fb) || state->bottom_up; 708 709 /* copy from state */ 710 window.zpos = plane->state->normalized_zpos; 711 window.tiling = state->tiling; 712 window.format = state->format; 713 window.swap = state->swap; 714 715 for (i = 0; i < fb->format->num_planes; i++) { 716 struct tegra_bo *bo = tegra_fb_get_plane(fb, i); 717 718 window.base[i] = bo->paddr + fb->offsets[i]; 719 720 /* 721 * Tegra uses a shared stride for UV planes. Framebuffers are 722 * already checked for this in the tegra_plane_atomic_check() 723 * function, so it's safe to ignore the V-plane pitch here. 724 */ 725 if (i < 2) 726 window.stride[i] = fb->pitches[i]; 727 } 728 729 tegra_dc_setup_window(p, &window); 730 } 731 732 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 733 .atomic_check = tegra_plane_atomic_check, 734 .atomic_disable = tegra_plane_atomic_disable, 735 .atomic_update = tegra_plane_atomic_update, 736 }; 737 738 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 739 { 740 /* 741 * Ideally this would use drm_crtc_mask(), but that would require the 742 * CRTC to already be in the mode_config's list of CRTCs. However, it 743 * will only be added to that list in the drm_crtc_init_with_planes() 744 * (in tegra_dc_init()), which in turn requires registration of these 745 * planes. So we have ourselves a nice little chicken and egg problem 746 * here. 747 * 748 * We work around this by manually creating the mask from the number 749 * of CRTCs that have been registered, and should therefore always be 750 * the same as drm_crtc_index() after registration. 751 */ 752 return 1 << drm->mode_config.num_crtc; 753 } 754 755 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 756 struct tegra_dc *dc) 757 { 758 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 759 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 760 struct tegra_plane *plane; 761 unsigned int num_formats; 762 const u64 *modifiers; 763 const u32 *formats; 764 int err; 765 766 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 767 if (!plane) 768 return ERR_PTR(-ENOMEM); 769 770 /* Always use window A as primary window */ 771 plane->offset = 0xa00; 772 plane->index = 0; 773 plane->dc = dc; 774 775 num_formats = dc->soc->num_primary_formats; 776 formats = dc->soc->primary_formats; 777 modifiers = dc->soc->modifiers; 778 779 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 780 &tegra_plane_funcs, formats, 781 num_formats, modifiers, type, NULL); 782 if (err < 0) { 783 kfree(plane); 784 return ERR_PTR(err); 785 } 786 787 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 788 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 789 790 err = drm_plane_create_rotation_property(&plane->base, 791 DRM_MODE_ROTATE_0, 792 DRM_MODE_ROTATE_0 | 793 DRM_MODE_REFLECT_Y); 794 if (err < 0) 795 dev_err(dc->dev, "failed to create rotation property: %d\n", 796 err); 797 798 return &plane->base; 799 } 800 801 static const u32 tegra_cursor_plane_formats[] = { 802 DRM_FORMAT_RGBA8888, 803 }; 804 805 static int tegra_cursor_atomic_check(struct drm_plane *plane, 806 struct drm_plane_state *state) 807 { 808 struct tegra_plane *tegra = to_tegra_plane(plane); 809 int err; 810 811 /* no need for further checks if the plane is being disabled */ 812 if (!state->crtc) 813 return 0; 814 815 /* scaling not supported for cursor */ 816 if ((state->src_w >> 16 != state->crtc_w) || 817 (state->src_h >> 16 != state->crtc_h)) 818 return -EINVAL; 819 820 /* only square cursors supported */ 821 if (state->src_w != state->src_h) 822 return -EINVAL; 823 824 if (state->crtc_w != 32 && state->crtc_w != 64 && 825 state->crtc_w != 128 && state->crtc_w != 256) 826 return -EINVAL; 827 828 err = tegra_plane_state_add(tegra, state); 829 if (err < 0) 830 return err; 831 832 return 0; 833 } 834 835 static void tegra_cursor_atomic_update(struct drm_plane *plane, 836 struct drm_plane_state *old_state) 837 { 838 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); 839 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); 840 struct drm_plane_state *state = plane->state; 841 u32 value = CURSOR_CLIP_DISPLAY; 842 843 /* rien ne va plus */ 844 if (!plane->state->crtc || !plane->state->fb) 845 return; 846 847 switch (state->crtc_w) { 848 case 32: 849 value |= CURSOR_SIZE_32x32; 850 break; 851 852 case 64: 853 value |= CURSOR_SIZE_64x64; 854 break; 855 856 case 128: 857 value |= CURSOR_SIZE_128x128; 858 break; 859 860 case 256: 861 value |= CURSOR_SIZE_256x256; 862 break; 863 864 default: 865 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, 866 state->crtc_h); 867 return; 868 } 869 870 value |= (bo->paddr >> 10) & 0x3fffff; 871 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 872 873 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 874 value = (bo->paddr >> 32) & 0x3; 875 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 876 #endif 877 878 /* enable cursor and set blend mode */ 879 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 880 value |= CURSOR_ENABLE; 881 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 882 883 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 884 value &= ~CURSOR_DST_BLEND_MASK; 885 value &= ~CURSOR_SRC_BLEND_MASK; 886 value |= CURSOR_MODE_NORMAL; 887 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 888 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 889 value |= CURSOR_ALPHA; 890 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 891 892 /* position the cursor */ 893 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); 894 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 895 } 896 897 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 898 struct drm_plane_state *old_state) 899 { 900 struct tegra_dc *dc; 901 u32 value; 902 903 /* rien ne va plus */ 904 if (!old_state || !old_state->crtc) 905 return; 906 907 dc = to_tegra_dc(old_state->crtc); 908 909 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 910 value &= ~CURSOR_ENABLE; 911 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 912 } 913 914 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 915 .atomic_check = tegra_cursor_atomic_check, 916 .atomic_update = tegra_cursor_atomic_update, 917 .atomic_disable = tegra_cursor_atomic_disable, 918 }; 919 920 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 921 struct tegra_dc *dc) 922 { 923 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 924 struct tegra_plane *plane; 925 unsigned int num_formats; 926 const u32 *formats; 927 int err; 928 929 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 930 if (!plane) 931 return ERR_PTR(-ENOMEM); 932 933 /* 934 * This index is kind of fake. The cursor isn't a regular plane, but 935 * its update and activation request bits in DC_CMD_STATE_CONTROL do 936 * use the same programming. Setting this fake index here allows the 937 * code in tegra_add_plane_state() to do the right thing without the 938 * need to special-casing the cursor plane. 939 */ 940 plane->index = 6; 941 plane->dc = dc; 942 943 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 944 formats = tegra_cursor_plane_formats; 945 946 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 947 &tegra_plane_funcs, formats, 948 num_formats, NULL, 949 DRM_PLANE_TYPE_CURSOR, NULL); 950 if (err < 0) { 951 kfree(plane); 952 return ERR_PTR(err); 953 } 954 955 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 956 957 return &plane->base; 958 } 959 960 static const u32 tegra20_overlay_formats[] = { 961 DRM_FORMAT_ARGB4444, 962 DRM_FORMAT_ARGB1555, 963 DRM_FORMAT_RGB565, 964 DRM_FORMAT_RGBA5551, 965 DRM_FORMAT_ABGR8888, 966 DRM_FORMAT_ARGB8888, 967 /* non-native formats */ 968 DRM_FORMAT_XRGB1555, 969 DRM_FORMAT_RGBX5551, 970 DRM_FORMAT_XBGR8888, 971 DRM_FORMAT_XRGB8888, 972 /* planar formats */ 973 DRM_FORMAT_UYVY, 974 DRM_FORMAT_YUYV, 975 DRM_FORMAT_YUV420, 976 DRM_FORMAT_YUV422, 977 }; 978 979 static const u32 tegra114_overlay_formats[] = { 980 DRM_FORMAT_ARGB4444, 981 DRM_FORMAT_ARGB1555, 982 DRM_FORMAT_RGB565, 983 DRM_FORMAT_RGBA5551, 984 DRM_FORMAT_ABGR8888, 985 DRM_FORMAT_ARGB8888, 986 /* new on Tegra114 */ 987 DRM_FORMAT_ABGR4444, 988 DRM_FORMAT_ABGR1555, 989 DRM_FORMAT_BGRA5551, 990 DRM_FORMAT_XRGB1555, 991 DRM_FORMAT_RGBX5551, 992 DRM_FORMAT_XBGR1555, 993 DRM_FORMAT_BGRX5551, 994 DRM_FORMAT_BGR565, 995 DRM_FORMAT_BGRA8888, 996 DRM_FORMAT_RGBA8888, 997 DRM_FORMAT_XRGB8888, 998 DRM_FORMAT_XBGR8888, 999 /* planar formats */ 1000 DRM_FORMAT_UYVY, 1001 DRM_FORMAT_YUYV, 1002 DRM_FORMAT_YUV420, 1003 DRM_FORMAT_YUV422, 1004 }; 1005 1006 static const u32 tegra124_overlay_formats[] = { 1007 DRM_FORMAT_ARGB4444, 1008 DRM_FORMAT_ARGB1555, 1009 DRM_FORMAT_RGB565, 1010 DRM_FORMAT_RGBA5551, 1011 DRM_FORMAT_ABGR8888, 1012 DRM_FORMAT_ARGB8888, 1013 /* new on Tegra114 */ 1014 DRM_FORMAT_ABGR4444, 1015 DRM_FORMAT_ABGR1555, 1016 DRM_FORMAT_BGRA5551, 1017 DRM_FORMAT_XRGB1555, 1018 DRM_FORMAT_RGBX5551, 1019 DRM_FORMAT_XBGR1555, 1020 DRM_FORMAT_BGRX5551, 1021 DRM_FORMAT_BGR565, 1022 DRM_FORMAT_BGRA8888, 1023 DRM_FORMAT_RGBA8888, 1024 DRM_FORMAT_XRGB8888, 1025 DRM_FORMAT_XBGR8888, 1026 /* new on Tegra124 */ 1027 DRM_FORMAT_RGBX8888, 1028 DRM_FORMAT_BGRX8888, 1029 /* planar formats */ 1030 DRM_FORMAT_UYVY, 1031 DRM_FORMAT_YUYV, 1032 DRM_FORMAT_YUV420, 1033 DRM_FORMAT_YUV422, 1034 }; 1035 1036 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 1037 struct tegra_dc *dc, 1038 unsigned int index, 1039 bool cursor) 1040 { 1041 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1042 struct tegra_plane *plane; 1043 unsigned int num_formats; 1044 enum drm_plane_type type; 1045 const u32 *formats; 1046 int err; 1047 1048 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1049 if (!plane) 1050 return ERR_PTR(-ENOMEM); 1051 1052 plane->offset = 0xa00 + 0x200 * index; 1053 plane->index = index; 1054 plane->dc = dc; 1055 1056 num_formats = dc->soc->num_overlay_formats; 1057 formats = dc->soc->overlay_formats; 1058 1059 if (!cursor) 1060 type = DRM_PLANE_TYPE_OVERLAY; 1061 else 1062 type = DRM_PLANE_TYPE_CURSOR; 1063 1064 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1065 &tegra_plane_funcs, formats, 1066 num_formats, NULL, type, NULL); 1067 if (err < 0) { 1068 kfree(plane); 1069 return ERR_PTR(err); 1070 } 1071 1072 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 1073 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 1074 1075 err = drm_plane_create_rotation_property(&plane->base, 1076 DRM_MODE_ROTATE_0, 1077 DRM_MODE_ROTATE_0 | 1078 DRM_MODE_REFLECT_Y); 1079 if (err < 0) 1080 dev_err(dc->dev, "failed to create rotation property: %d\n", 1081 err); 1082 1083 return &plane->base; 1084 } 1085 1086 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 1087 struct tegra_dc *dc) 1088 { 1089 struct drm_plane *plane, *primary = NULL; 1090 unsigned int i, j; 1091 1092 for (i = 0; i < dc->soc->num_wgrps; i++) { 1093 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1094 1095 if (wgrp->dc == dc->pipe) { 1096 for (j = 0; j < wgrp->num_windows; j++) { 1097 unsigned int index = wgrp->windows[j]; 1098 1099 plane = tegra_shared_plane_create(drm, dc, 1100 wgrp->index, 1101 index); 1102 if (IS_ERR(plane)) 1103 return plane; 1104 1105 /* 1106 * Choose the first shared plane owned by this 1107 * head as the primary plane. 1108 */ 1109 if (!primary) { 1110 plane->type = DRM_PLANE_TYPE_PRIMARY; 1111 primary = plane; 1112 } 1113 } 1114 } 1115 } 1116 1117 return primary; 1118 } 1119 1120 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 1121 struct tegra_dc *dc) 1122 { 1123 struct drm_plane *planes[2], *primary; 1124 unsigned int planes_num; 1125 unsigned int i; 1126 int err; 1127 1128 primary = tegra_primary_plane_create(drm, dc); 1129 if (IS_ERR(primary)) 1130 return primary; 1131 1132 if (dc->soc->supports_cursor) 1133 planes_num = 2; 1134 else 1135 planes_num = 1; 1136 1137 for (i = 0; i < planes_num; i++) { 1138 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 1139 false); 1140 if (IS_ERR(planes[i])) { 1141 err = PTR_ERR(planes[i]); 1142 1143 while (i--) 1144 tegra_plane_funcs.destroy(planes[i]); 1145 1146 tegra_plane_funcs.destroy(primary); 1147 return ERR_PTR(err); 1148 } 1149 } 1150 1151 return primary; 1152 } 1153 1154 static void tegra_dc_destroy(struct drm_crtc *crtc) 1155 { 1156 drm_crtc_cleanup(crtc); 1157 } 1158 1159 static void tegra_crtc_reset(struct drm_crtc *crtc) 1160 { 1161 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 1162 1163 if (crtc->state) 1164 tegra_crtc_atomic_destroy_state(crtc, crtc->state); 1165 1166 __drm_atomic_helper_crtc_reset(crtc, &state->base); 1167 drm_crtc_vblank_reset(crtc); 1168 } 1169 1170 static struct drm_crtc_state * 1171 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1172 { 1173 struct tegra_dc_state *state = to_dc_state(crtc->state); 1174 struct tegra_dc_state *copy; 1175 1176 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 1177 if (!copy) 1178 return NULL; 1179 1180 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1181 copy->clk = state->clk; 1182 copy->pclk = state->pclk; 1183 copy->div = state->div; 1184 copy->planes = state->planes; 1185 1186 return ©->base; 1187 } 1188 1189 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1190 struct drm_crtc_state *state) 1191 { 1192 __drm_atomic_helper_crtc_destroy_state(state); 1193 kfree(state); 1194 } 1195 1196 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1197 1198 static const struct debugfs_reg32 tegra_dc_regs[] = { 1199 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1200 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1201 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1202 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1203 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1204 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1205 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1206 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1207 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1208 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1209 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1210 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1211 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1212 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1213 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1214 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1215 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1216 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1217 DEBUGFS_REG32(DC_CMD_INT_MASK), 1218 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1219 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1220 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1221 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1222 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1223 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1224 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1225 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1226 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1227 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1228 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1229 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1230 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1231 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1232 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1233 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1234 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1235 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1236 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1237 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1238 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1239 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1240 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1241 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1242 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1243 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1244 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1245 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1246 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1247 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1248 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1249 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1250 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1251 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1252 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1253 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1254 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1255 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1256 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1257 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1258 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1259 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1260 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1261 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1262 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1263 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1264 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1265 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1266 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1267 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1268 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1269 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1270 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1271 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1272 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1273 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1274 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1275 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1276 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1277 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1278 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1279 DEBUGFS_REG32(DC_DISP_ACTIVE), 1280 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1281 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1282 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1283 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1284 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1285 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1286 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1287 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1288 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1289 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1290 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1291 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1292 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1293 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1294 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1295 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1296 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1297 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1298 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1299 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1300 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1301 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1302 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1303 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1304 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1305 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1306 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1307 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1308 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1309 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1310 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1311 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1312 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1313 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1314 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1315 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1316 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1317 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1318 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1319 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1320 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1321 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1322 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1323 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1324 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1325 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1326 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1327 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1328 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1329 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1330 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1331 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1332 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1333 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1334 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1335 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1336 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1337 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1338 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1339 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1340 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1341 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1342 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1343 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1344 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1345 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1346 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1347 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1348 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1349 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1350 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1351 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1352 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1353 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1354 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1355 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1356 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1357 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1358 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1359 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1360 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1361 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1362 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1363 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1364 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1365 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1366 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1367 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1368 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1369 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1370 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1371 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1372 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1373 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1374 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1375 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1376 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1377 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1378 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1379 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1380 DEBUGFS_REG32(DC_WIN_POSITION), 1381 DEBUGFS_REG32(DC_WIN_SIZE), 1382 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1383 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1384 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1385 DEBUGFS_REG32(DC_WIN_DDA_INC), 1386 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1387 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1388 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1389 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1390 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1391 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1392 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1393 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1394 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1395 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1396 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1397 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1398 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1399 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1400 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1401 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1402 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1403 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1404 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1405 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1406 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1407 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1408 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1409 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1410 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1411 }; 1412 1413 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1414 { 1415 struct drm_info_node *node = s->private; 1416 struct tegra_dc *dc = node->info_ent->data; 1417 unsigned int i; 1418 int err = 0; 1419 1420 drm_modeset_lock(&dc->base.mutex, NULL); 1421 1422 if (!dc->base.state->active) { 1423 err = -EBUSY; 1424 goto unlock; 1425 } 1426 1427 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1428 unsigned int offset = tegra_dc_regs[i].offset; 1429 1430 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1431 offset, tegra_dc_readl(dc, offset)); 1432 } 1433 1434 unlock: 1435 drm_modeset_unlock(&dc->base.mutex); 1436 return err; 1437 } 1438 1439 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1440 { 1441 struct drm_info_node *node = s->private; 1442 struct tegra_dc *dc = node->info_ent->data; 1443 int err = 0; 1444 u32 value; 1445 1446 drm_modeset_lock(&dc->base.mutex, NULL); 1447 1448 if (!dc->base.state->active) { 1449 err = -EBUSY; 1450 goto unlock; 1451 } 1452 1453 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1454 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1455 tegra_dc_commit(dc); 1456 1457 drm_crtc_wait_one_vblank(&dc->base); 1458 drm_crtc_wait_one_vblank(&dc->base); 1459 1460 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1461 seq_printf(s, "%08x\n", value); 1462 1463 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1464 1465 unlock: 1466 drm_modeset_unlock(&dc->base.mutex); 1467 return err; 1468 } 1469 1470 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1471 { 1472 struct drm_info_node *node = s->private; 1473 struct tegra_dc *dc = node->info_ent->data; 1474 1475 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1476 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1477 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1478 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1479 1480 return 0; 1481 } 1482 1483 static struct drm_info_list debugfs_files[] = { 1484 { "regs", tegra_dc_show_regs, 0, NULL }, 1485 { "crc", tegra_dc_show_crc, 0, NULL }, 1486 { "stats", tegra_dc_show_stats, 0, NULL }, 1487 }; 1488 1489 static int tegra_dc_late_register(struct drm_crtc *crtc) 1490 { 1491 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1492 struct drm_minor *minor = crtc->dev->primary; 1493 struct dentry *root; 1494 struct tegra_dc *dc = to_tegra_dc(crtc); 1495 int err; 1496 1497 #ifdef CONFIG_DEBUG_FS 1498 root = crtc->debugfs_entry; 1499 #else 1500 root = NULL; 1501 #endif 1502 1503 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1504 GFP_KERNEL); 1505 if (!dc->debugfs_files) 1506 return -ENOMEM; 1507 1508 for (i = 0; i < count; i++) 1509 dc->debugfs_files[i].data = dc; 1510 1511 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1512 if (err < 0) 1513 goto free; 1514 1515 return 0; 1516 1517 free: 1518 kfree(dc->debugfs_files); 1519 dc->debugfs_files = NULL; 1520 1521 return err; 1522 } 1523 1524 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1525 { 1526 unsigned int count = ARRAY_SIZE(debugfs_files); 1527 struct drm_minor *minor = crtc->dev->primary; 1528 struct tegra_dc *dc = to_tegra_dc(crtc); 1529 1530 drm_debugfs_remove_files(dc->debugfs_files, count, minor); 1531 kfree(dc->debugfs_files); 1532 dc->debugfs_files = NULL; 1533 } 1534 1535 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1536 { 1537 struct tegra_dc *dc = to_tegra_dc(crtc); 1538 1539 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1540 if (dc->syncpt && !dc->soc->has_nvdisplay) 1541 return host1x_syncpt_read(dc->syncpt); 1542 1543 /* fallback to software emulated VBLANK counter */ 1544 return (u32)drm_crtc_vblank_count(&dc->base); 1545 } 1546 1547 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1548 { 1549 struct tegra_dc *dc = to_tegra_dc(crtc); 1550 u32 value; 1551 1552 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1553 value |= VBLANK_INT; 1554 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1555 1556 return 0; 1557 } 1558 1559 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1560 { 1561 struct tegra_dc *dc = to_tegra_dc(crtc); 1562 u32 value; 1563 1564 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1565 value &= ~VBLANK_INT; 1566 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1567 } 1568 1569 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1570 .page_flip = drm_atomic_helper_page_flip, 1571 .set_config = drm_atomic_helper_set_config, 1572 .destroy = tegra_dc_destroy, 1573 .reset = tegra_crtc_reset, 1574 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1575 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1576 .late_register = tegra_dc_late_register, 1577 .early_unregister = tegra_dc_early_unregister, 1578 .get_vblank_counter = tegra_dc_get_vblank_counter, 1579 .enable_vblank = tegra_dc_enable_vblank, 1580 .disable_vblank = tegra_dc_disable_vblank, 1581 }; 1582 1583 static int tegra_dc_set_timings(struct tegra_dc *dc, 1584 struct drm_display_mode *mode) 1585 { 1586 unsigned int h_ref_to_sync = 1; 1587 unsigned int v_ref_to_sync = 1; 1588 unsigned long value; 1589 1590 if (!dc->soc->has_nvdisplay) { 1591 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1592 1593 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1594 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1595 } 1596 1597 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1598 ((mode->hsync_end - mode->hsync_start) << 0); 1599 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1600 1601 value = ((mode->vtotal - mode->vsync_end) << 16) | 1602 ((mode->htotal - mode->hsync_end) << 0); 1603 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1604 1605 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1606 ((mode->hsync_start - mode->hdisplay) << 0); 1607 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1608 1609 value = (mode->vdisplay << 16) | mode->hdisplay; 1610 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1611 1612 return 0; 1613 } 1614 1615 /** 1616 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1617 * state 1618 * @dc: display controller 1619 * @crtc_state: CRTC atomic state 1620 * @clk: parent clock for display controller 1621 * @pclk: pixel clock 1622 * @div: shift clock divider 1623 * 1624 * Returns: 1625 * 0 on success or a negative error-code on failure. 1626 */ 1627 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1628 struct drm_crtc_state *crtc_state, 1629 struct clk *clk, unsigned long pclk, 1630 unsigned int div) 1631 { 1632 struct tegra_dc_state *state = to_dc_state(crtc_state); 1633 1634 if (!clk_has_parent(dc->clk, clk)) 1635 return -EINVAL; 1636 1637 state->clk = clk; 1638 state->pclk = pclk; 1639 state->div = div; 1640 1641 return 0; 1642 } 1643 1644 static void tegra_dc_commit_state(struct tegra_dc *dc, 1645 struct tegra_dc_state *state) 1646 { 1647 u32 value; 1648 int err; 1649 1650 err = clk_set_parent(dc->clk, state->clk); 1651 if (err < 0) 1652 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 1653 1654 /* 1655 * Outputs may not want to change the parent clock rate. This is only 1656 * relevant to Tegra20 where only a single display PLL is available. 1657 * Since that PLL would typically be used for HDMI, an internal LVDS 1658 * panel would need to be driven by some other clock such as PLL_P 1659 * which is shared with other peripherals. Changing the clock rate 1660 * should therefore be avoided. 1661 */ 1662 if (state->pclk > 0) { 1663 err = clk_set_rate(state->clk, state->pclk); 1664 if (err < 0) 1665 dev_err(dc->dev, 1666 "failed to set clock rate to %lu Hz\n", 1667 state->pclk); 1668 } 1669 1670 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 1671 state->div); 1672 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1673 1674 if (!dc->soc->has_nvdisplay) { 1675 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; 1676 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 1677 } 1678 1679 err = clk_set_rate(dc->clk, state->pclk); 1680 if (err < 0) 1681 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 1682 dc->clk, state->pclk, err); 1683 } 1684 1685 static void tegra_dc_stop(struct tegra_dc *dc) 1686 { 1687 u32 value; 1688 1689 /* stop the display controller */ 1690 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1691 value &= ~DISP_CTRL_MODE_MASK; 1692 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1693 1694 tegra_dc_commit(dc); 1695 } 1696 1697 static bool tegra_dc_idle(struct tegra_dc *dc) 1698 { 1699 u32 value; 1700 1701 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 1702 1703 return (value & DISP_CTRL_MODE_MASK) == 0; 1704 } 1705 1706 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 1707 { 1708 timeout = jiffies + msecs_to_jiffies(timeout); 1709 1710 while (time_before(jiffies, timeout)) { 1711 if (tegra_dc_idle(dc)) 1712 return 0; 1713 1714 usleep_range(1000, 2000); 1715 } 1716 1717 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 1718 return -ETIMEDOUT; 1719 } 1720 1721 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 1722 struct drm_crtc_state *old_state) 1723 { 1724 struct tegra_dc *dc = to_tegra_dc(crtc); 1725 u32 value; 1726 1727 if (!tegra_dc_idle(dc)) { 1728 tegra_dc_stop(dc); 1729 1730 /* 1731 * Ignore the return value, there isn't anything useful to do 1732 * in case this fails. 1733 */ 1734 tegra_dc_wait_idle(dc, 100); 1735 } 1736 1737 /* 1738 * This should really be part of the RGB encoder driver, but clearing 1739 * these bits has the side-effect of stopping the display controller. 1740 * When that happens no VBLANK interrupts will be raised. At the same 1741 * time the encoder is disabled before the display controller, so the 1742 * above code is always going to timeout waiting for the controller 1743 * to go idle. 1744 * 1745 * Given the close coupling between the RGB encoder and the display 1746 * controller doing it here is still kind of okay. None of the other 1747 * encoder drivers require these bits to be cleared. 1748 * 1749 * XXX: Perhaps given that the display controller is switched off at 1750 * this point anyway maybe clearing these bits isn't even useful for 1751 * the RGB encoder? 1752 */ 1753 if (dc->rgb) { 1754 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1755 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1756 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 1757 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1758 } 1759 1760 tegra_dc_stats_reset(&dc->stats); 1761 drm_crtc_vblank_off(crtc); 1762 1763 spin_lock_irq(&crtc->dev->event_lock); 1764 1765 if (crtc->state->event) { 1766 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1767 crtc->state->event = NULL; 1768 } 1769 1770 spin_unlock_irq(&crtc->dev->event_lock); 1771 1772 pm_runtime_put_sync(dc->dev); 1773 } 1774 1775 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 1776 struct drm_crtc_state *old_state) 1777 { 1778 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1779 struct tegra_dc_state *state = to_dc_state(crtc->state); 1780 struct tegra_dc *dc = to_tegra_dc(crtc); 1781 u32 value; 1782 1783 pm_runtime_get_sync(dc->dev); 1784 1785 /* initialize display controller */ 1786 if (dc->syncpt) { 1787 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 1788 1789 if (dc->soc->has_nvdisplay) 1790 enable = 1 << 31; 1791 else 1792 enable = 1 << 8; 1793 1794 value = SYNCPT_CNTRL_NO_STALL; 1795 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1796 1797 value = enable | syncpt; 1798 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 1799 } 1800 1801 if (dc->soc->has_nvdisplay) { 1802 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 1803 DSC_OBUF_UF_INT; 1804 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1805 1806 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 1807 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 1808 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 1809 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 1810 VBLANK_INT | FRAME_END_INT; 1811 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1812 1813 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 1814 FRAME_END_INT; 1815 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1816 1817 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 1818 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1819 1820 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 1821 } else { 1822 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1823 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1824 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1825 1826 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1827 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1828 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1829 1830 /* initialize timer */ 1831 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1832 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1833 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1834 1835 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1836 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1837 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1838 1839 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1840 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1841 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1842 1843 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1844 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1845 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1846 } 1847 1848 if (dc->soc->supports_background_color) 1849 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 1850 else 1851 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1852 1853 /* apply PLL and pixel clock changes */ 1854 tegra_dc_commit_state(dc, state); 1855 1856 /* program display mode */ 1857 tegra_dc_set_timings(dc, mode); 1858 1859 /* interlacing isn't supported yet, so disable it */ 1860 if (dc->soc->supports_interlacing) { 1861 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 1862 value &= ~INTERLACE_ENABLE; 1863 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 1864 } 1865 1866 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1867 value &= ~DISP_CTRL_MODE_MASK; 1868 value |= DISP_CTRL_MODE_C_DISPLAY; 1869 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1870 1871 if (!dc->soc->has_nvdisplay) { 1872 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1873 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1874 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 1875 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1876 } 1877 1878 /* enable underflow reporting and display red for missing pixels */ 1879 if (dc->soc->has_nvdisplay) { 1880 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 1881 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 1882 } 1883 1884 tegra_dc_commit(dc); 1885 1886 drm_crtc_vblank_on(crtc); 1887 } 1888 1889 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 1890 struct drm_crtc_state *old_crtc_state) 1891 { 1892 unsigned long flags; 1893 1894 if (crtc->state->event) { 1895 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1896 1897 if (drm_crtc_vblank_get(crtc) != 0) 1898 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1899 else 1900 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 1901 1902 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1903 1904 crtc->state->event = NULL; 1905 } 1906 } 1907 1908 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 1909 struct drm_crtc_state *old_crtc_state) 1910 { 1911 struct tegra_dc_state *state = to_dc_state(crtc->state); 1912 struct tegra_dc *dc = to_tegra_dc(crtc); 1913 u32 value; 1914 1915 value = state->planes << 8 | GENERAL_UPDATE; 1916 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1917 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1918 1919 value = state->planes | GENERAL_ACT_REQ; 1920 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1921 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1922 } 1923 1924 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 1925 .atomic_begin = tegra_crtc_atomic_begin, 1926 .atomic_flush = tegra_crtc_atomic_flush, 1927 .atomic_enable = tegra_crtc_atomic_enable, 1928 .atomic_disable = tegra_crtc_atomic_disable, 1929 }; 1930 1931 static irqreturn_t tegra_dc_irq(int irq, void *data) 1932 { 1933 struct tegra_dc *dc = data; 1934 unsigned long status; 1935 1936 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 1937 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 1938 1939 if (status & FRAME_END_INT) { 1940 /* 1941 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 1942 */ 1943 dc->stats.frames++; 1944 } 1945 1946 if (status & VBLANK_INT) { 1947 /* 1948 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 1949 */ 1950 drm_crtc_handle_vblank(&dc->base); 1951 dc->stats.vblank++; 1952 } 1953 1954 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 1955 /* 1956 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 1957 */ 1958 dc->stats.underflow++; 1959 } 1960 1961 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 1962 /* 1963 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 1964 */ 1965 dc->stats.overflow++; 1966 } 1967 1968 if (status & HEAD_UF_INT) { 1969 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 1970 dc->stats.underflow++; 1971 } 1972 1973 return IRQ_HANDLED; 1974 } 1975 1976 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) 1977 { 1978 unsigned int i; 1979 1980 if (!dc->soc->wgrps) 1981 return true; 1982 1983 for (i = 0; i < dc->soc->num_wgrps; i++) { 1984 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1985 1986 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) 1987 return true; 1988 } 1989 1990 return false; 1991 } 1992 1993 static int tegra_dc_init(struct host1x_client *client) 1994 { 1995 struct drm_device *drm = dev_get_drvdata(client->parent); 1996 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 1997 struct tegra_dc *dc = host1x_client_to_dc(client); 1998 struct tegra_drm *tegra = drm->dev_private; 1999 struct drm_plane *primary = NULL; 2000 struct drm_plane *cursor = NULL; 2001 int err; 2002 2003 /* 2004 * XXX do not register DCs with no window groups because we cannot 2005 * assign a primary plane to them, which in turn will cause KMS to 2006 * crash. 2007 */ 2008 if (!tegra_dc_has_window_groups(dc)) 2009 return 0; 2010 2011 dc->syncpt = host1x_syncpt_request(client, flags); 2012 if (!dc->syncpt) 2013 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 2014 2015 dc->group = host1x_client_iommu_attach(client, true); 2016 if (IS_ERR(dc->group)) { 2017 err = PTR_ERR(dc->group); 2018 dev_err(client->dev, "failed to attach to domain: %d\n", err); 2019 return err; 2020 } 2021 2022 if (dc->soc->wgrps) 2023 primary = tegra_dc_add_shared_planes(drm, dc); 2024 else 2025 primary = tegra_dc_add_planes(drm, dc); 2026 2027 if (IS_ERR(primary)) { 2028 err = PTR_ERR(primary); 2029 goto cleanup; 2030 } 2031 2032 if (dc->soc->supports_cursor) { 2033 cursor = tegra_dc_cursor_plane_create(drm, dc); 2034 if (IS_ERR(cursor)) { 2035 err = PTR_ERR(cursor); 2036 goto cleanup; 2037 } 2038 } else { 2039 /* dedicate one overlay to mouse cursor */ 2040 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 2041 if (IS_ERR(cursor)) { 2042 err = PTR_ERR(cursor); 2043 goto cleanup; 2044 } 2045 } 2046 2047 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 2048 &tegra_crtc_funcs, NULL); 2049 if (err < 0) 2050 goto cleanup; 2051 2052 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 2053 2054 /* 2055 * Keep track of the minimum pitch alignment across all display 2056 * controllers. 2057 */ 2058 if (dc->soc->pitch_align > tegra->pitch_align) 2059 tegra->pitch_align = dc->soc->pitch_align; 2060 2061 err = tegra_dc_rgb_init(drm, dc); 2062 if (err < 0 && err != -ENODEV) { 2063 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 2064 goto cleanup; 2065 } 2066 2067 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 2068 dev_name(dc->dev), dc); 2069 if (err < 0) { 2070 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 2071 err); 2072 goto cleanup; 2073 } 2074 2075 return 0; 2076 2077 cleanup: 2078 if (!IS_ERR_OR_NULL(cursor)) 2079 drm_plane_cleanup(cursor); 2080 2081 if (!IS_ERR(primary)) 2082 drm_plane_cleanup(primary); 2083 2084 host1x_client_iommu_detach(client, dc->group); 2085 host1x_syncpt_free(dc->syncpt); 2086 2087 return err; 2088 } 2089 2090 static int tegra_dc_exit(struct host1x_client *client) 2091 { 2092 struct tegra_dc *dc = host1x_client_to_dc(client); 2093 int err; 2094 2095 if (!tegra_dc_has_window_groups(dc)) 2096 return 0; 2097 2098 devm_free_irq(dc->dev, dc->irq, dc); 2099 2100 err = tegra_dc_rgb_exit(dc); 2101 if (err) { 2102 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 2103 return err; 2104 } 2105 2106 host1x_client_iommu_detach(client, dc->group); 2107 host1x_syncpt_free(dc->syncpt); 2108 2109 return 0; 2110 } 2111 2112 static const struct host1x_client_ops dc_client_ops = { 2113 .init = tegra_dc_init, 2114 .exit = tegra_dc_exit, 2115 }; 2116 2117 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 2118 .supports_background_color = false, 2119 .supports_interlacing = false, 2120 .supports_cursor = false, 2121 .supports_block_linear = false, 2122 .has_legacy_blending = true, 2123 .pitch_align = 8, 2124 .has_powergate = false, 2125 .coupled_pm = true, 2126 .has_nvdisplay = false, 2127 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2128 .primary_formats = tegra20_primary_formats, 2129 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2130 .overlay_formats = tegra20_overlay_formats, 2131 .modifiers = tegra20_modifiers, 2132 .has_win_a_without_filters = true, 2133 .has_win_c_without_vert_filter = true, 2134 }; 2135 2136 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 2137 .supports_background_color = false, 2138 .supports_interlacing = false, 2139 .supports_cursor = false, 2140 .supports_block_linear = false, 2141 .has_legacy_blending = true, 2142 .pitch_align = 8, 2143 .has_powergate = false, 2144 .coupled_pm = false, 2145 .has_nvdisplay = false, 2146 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2147 .primary_formats = tegra20_primary_formats, 2148 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2149 .overlay_formats = tegra20_overlay_formats, 2150 .modifiers = tegra20_modifiers, 2151 .has_win_a_without_filters = false, 2152 .has_win_c_without_vert_filter = false, 2153 }; 2154 2155 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2156 .supports_background_color = false, 2157 .supports_interlacing = false, 2158 .supports_cursor = false, 2159 .supports_block_linear = false, 2160 .has_legacy_blending = true, 2161 .pitch_align = 64, 2162 .has_powergate = true, 2163 .coupled_pm = false, 2164 .has_nvdisplay = false, 2165 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2166 .primary_formats = tegra114_primary_formats, 2167 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2168 .overlay_formats = tegra114_overlay_formats, 2169 .modifiers = tegra20_modifiers, 2170 .has_win_a_without_filters = false, 2171 .has_win_c_without_vert_filter = false, 2172 }; 2173 2174 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 2175 .supports_background_color = true, 2176 .supports_interlacing = true, 2177 .supports_cursor = true, 2178 .supports_block_linear = true, 2179 .has_legacy_blending = false, 2180 .pitch_align = 64, 2181 .has_powergate = true, 2182 .coupled_pm = false, 2183 .has_nvdisplay = false, 2184 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 2185 .primary_formats = tegra124_primary_formats, 2186 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 2187 .overlay_formats = tegra124_overlay_formats, 2188 .modifiers = tegra124_modifiers, 2189 .has_win_a_without_filters = false, 2190 .has_win_c_without_vert_filter = false, 2191 }; 2192 2193 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2194 .supports_background_color = true, 2195 .supports_interlacing = true, 2196 .supports_cursor = true, 2197 .supports_block_linear = true, 2198 .has_legacy_blending = false, 2199 .pitch_align = 64, 2200 .has_powergate = true, 2201 .coupled_pm = false, 2202 .has_nvdisplay = false, 2203 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2204 .primary_formats = tegra114_primary_formats, 2205 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2206 .overlay_formats = tegra114_overlay_formats, 2207 .modifiers = tegra124_modifiers, 2208 .has_win_a_without_filters = false, 2209 .has_win_c_without_vert_filter = false, 2210 }; 2211 2212 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 2213 { 2214 .index = 0, 2215 .dc = 0, 2216 .windows = (const unsigned int[]) { 0 }, 2217 .num_windows = 1, 2218 }, { 2219 .index = 1, 2220 .dc = 1, 2221 .windows = (const unsigned int[]) { 1 }, 2222 .num_windows = 1, 2223 }, { 2224 .index = 2, 2225 .dc = 1, 2226 .windows = (const unsigned int[]) { 2 }, 2227 .num_windows = 1, 2228 }, { 2229 .index = 3, 2230 .dc = 2, 2231 .windows = (const unsigned int[]) { 3 }, 2232 .num_windows = 1, 2233 }, { 2234 .index = 4, 2235 .dc = 2, 2236 .windows = (const unsigned int[]) { 4 }, 2237 .num_windows = 1, 2238 }, { 2239 .index = 5, 2240 .dc = 2, 2241 .windows = (const unsigned int[]) { 5 }, 2242 .num_windows = 1, 2243 }, 2244 }; 2245 2246 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 2247 .supports_background_color = true, 2248 .supports_interlacing = true, 2249 .supports_cursor = true, 2250 .supports_block_linear = true, 2251 .has_legacy_blending = false, 2252 .pitch_align = 64, 2253 .has_powergate = false, 2254 .coupled_pm = false, 2255 .has_nvdisplay = true, 2256 .wgrps = tegra186_dc_wgrps, 2257 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2258 }; 2259 2260 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { 2261 { 2262 .index = 0, 2263 .dc = 0, 2264 .windows = (const unsigned int[]) { 0 }, 2265 .num_windows = 1, 2266 }, { 2267 .index = 1, 2268 .dc = 1, 2269 .windows = (const unsigned int[]) { 1 }, 2270 .num_windows = 1, 2271 }, { 2272 .index = 2, 2273 .dc = 1, 2274 .windows = (const unsigned int[]) { 2 }, 2275 .num_windows = 1, 2276 }, { 2277 .index = 3, 2278 .dc = 2, 2279 .windows = (const unsigned int[]) { 3 }, 2280 .num_windows = 1, 2281 }, { 2282 .index = 4, 2283 .dc = 2, 2284 .windows = (const unsigned int[]) { 4 }, 2285 .num_windows = 1, 2286 }, { 2287 .index = 5, 2288 .dc = 2, 2289 .windows = (const unsigned int[]) { 5 }, 2290 .num_windows = 1, 2291 }, 2292 }; 2293 2294 static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 2295 .supports_background_color = true, 2296 .supports_interlacing = true, 2297 .supports_cursor = true, 2298 .supports_block_linear = true, 2299 .has_legacy_blending = false, 2300 .pitch_align = 64, 2301 .has_powergate = false, 2302 .coupled_pm = false, 2303 .has_nvdisplay = true, 2304 .wgrps = tegra194_dc_wgrps, 2305 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), 2306 }; 2307 2308 static const struct of_device_id tegra_dc_of_match[] = { 2309 { 2310 .compatible = "nvidia,tegra194-dc", 2311 .data = &tegra194_dc_soc_info, 2312 }, { 2313 .compatible = "nvidia,tegra186-dc", 2314 .data = &tegra186_dc_soc_info, 2315 }, { 2316 .compatible = "nvidia,tegra210-dc", 2317 .data = &tegra210_dc_soc_info, 2318 }, { 2319 .compatible = "nvidia,tegra124-dc", 2320 .data = &tegra124_dc_soc_info, 2321 }, { 2322 .compatible = "nvidia,tegra114-dc", 2323 .data = &tegra114_dc_soc_info, 2324 }, { 2325 .compatible = "nvidia,tegra30-dc", 2326 .data = &tegra30_dc_soc_info, 2327 }, { 2328 .compatible = "nvidia,tegra20-dc", 2329 .data = &tegra20_dc_soc_info, 2330 }, { 2331 /* sentinel */ 2332 } 2333 }; 2334 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 2335 2336 static int tegra_dc_parse_dt(struct tegra_dc *dc) 2337 { 2338 struct device_node *np; 2339 u32 value = 0; 2340 int err; 2341 2342 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 2343 if (err < 0) { 2344 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 2345 2346 /* 2347 * If the nvidia,head property isn't present, try to find the 2348 * correct head number by looking up the position of this 2349 * display controller's node within the device tree. Assuming 2350 * that the nodes are ordered properly in the DTS file and 2351 * that the translation into a flattened device tree blob 2352 * preserves that ordering this will actually yield the right 2353 * head number. 2354 * 2355 * If those assumptions don't hold, this will still work for 2356 * cases where only a single display controller is used. 2357 */ 2358 for_each_matching_node(np, tegra_dc_of_match) { 2359 if (np == dc->dev->of_node) { 2360 of_node_put(np); 2361 break; 2362 } 2363 2364 value++; 2365 } 2366 } 2367 2368 dc->pipe = value; 2369 2370 return 0; 2371 } 2372 2373 static int tegra_dc_match_by_pipe(struct device *dev, void *data) 2374 { 2375 struct tegra_dc *dc = dev_get_drvdata(dev); 2376 unsigned int pipe = (unsigned long)data; 2377 2378 return dc->pipe == pipe; 2379 } 2380 2381 static int tegra_dc_couple(struct tegra_dc *dc) 2382 { 2383 /* 2384 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 2385 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 2386 * POWER_CONTROL registers during CRTC enabling. 2387 */ 2388 if (dc->soc->coupled_pm && dc->pipe == 1) { 2389 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE_CONSUMER; 2390 struct device_link *link; 2391 struct device *partner; 2392 2393 partner = driver_find_device(dc->dev->driver, NULL, NULL, 2394 tegra_dc_match_by_pipe); 2395 if (!partner) 2396 return -EPROBE_DEFER; 2397 2398 link = device_link_add(dc->dev, partner, flags); 2399 if (!link) { 2400 dev_err(dc->dev, "failed to link controllers\n"); 2401 return -EINVAL; 2402 } 2403 2404 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner)); 2405 } 2406 2407 return 0; 2408 } 2409 2410 static int tegra_dc_probe(struct platform_device *pdev) 2411 { 2412 struct resource *regs; 2413 struct tegra_dc *dc; 2414 int err; 2415 2416 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 2417 if (!dc) 2418 return -ENOMEM; 2419 2420 dc->soc = of_device_get_match_data(&pdev->dev); 2421 2422 INIT_LIST_HEAD(&dc->list); 2423 dc->dev = &pdev->dev; 2424 2425 err = tegra_dc_parse_dt(dc); 2426 if (err < 0) 2427 return err; 2428 2429 err = tegra_dc_couple(dc); 2430 if (err < 0) 2431 return err; 2432 2433 dc->clk = devm_clk_get(&pdev->dev, NULL); 2434 if (IS_ERR(dc->clk)) { 2435 dev_err(&pdev->dev, "failed to get clock\n"); 2436 return PTR_ERR(dc->clk); 2437 } 2438 2439 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 2440 if (IS_ERR(dc->rst)) { 2441 dev_err(&pdev->dev, "failed to get reset\n"); 2442 return PTR_ERR(dc->rst); 2443 } 2444 2445 /* assert reset and disable clock */ 2446 err = clk_prepare_enable(dc->clk); 2447 if (err < 0) 2448 return err; 2449 2450 usleep_range(2000, 4000); 2451 2452 err = reset_control_assert(dc->rst); 2453 if (err < 0) 2454 return err; 2455 2456 usleep_range(2000, 4000); 2457 2458 clk_disable_unprepare(dc->clk); 2459 2460 if (dc->soc->has_powergate) { 2461 if (dc->pipe == 0) 2462 dc->powergate = TEGRA_POWERGATE_DIS; 2463 else 2464 dc->powergate = TEGRA_POWERGATE_DISB; 2465 2466 tegra_powergate_power_off(dc->powergate); 2467 } 2468 2469 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2470 dc->regs = devm_ioremap_resource(&pdev->dev, regs); 2471 if (IS_ERR(dc->regs)) 2472 return PTR_ERR(dc->regs); 2473 2474 dc->irq = platform_get_irq(pdev, 0); 2475 if (dc->irq < 0) { 2476 dev_err(&pdev->dev, "failed to get IRQ\n"); 2477 return -ENXIO; 2478 } 2479 2480 err = tegra_dc_rgb_probe(dc); 2481 if (err < 0 && err != -ENODEV) { 2482 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); 2483 return err; 2484 } 2485 2486 platform_set_drvdata(pdev, dc); 2487 pm_runtime_enable(&pdev->dev); 2488 2489 INIT_LIST_HEAD(&dc->client.list); 2490 dc->client.ops = &dc_client_ops; 2491 dc->client.dev = &pdev->dev; 2492 2493 err = host1x_client_register(&dc->client); 2494 if (err < 0) { 2495 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 2496 err); 2497 return err; 2498 } 2499 2500 return 0; 2501 } 2502 2503 static int tegra_dc_remove(struct platform_device *pdev) 2504 { 2505 struct tegra_dc *dc = platform_get_drvdata(pdev); 2506 int err; 2507 2508 err = host1x_client_unregister(&dc->client); 2509 if (err < 0) { 2510 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 2511 err); 2512 return err; 2513 } 2514 2515 err = tegra_dc_rgb_remove(dc); 2516 if (err < 0) { 2517 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 2518 return err; 2519 } 2520 2521 pm_runtime_disable(&pdev->dev); 2522 2523 return 0; 2524 } 2525 2526 #ifdef CONFIG_PM 2527 static int tegra_dc_suspend(struct device *dev) 2528 { 2529 struct tegra_dc *dc = dev_get_drvdata(dev); 2530 int err; 2531 2532 err = reset_control_assert(dc->rst); 2533 if (err < 0) { 2534 dev_err(dev, "failed to assert reset: %d\n", err); 2535 return err; 2536 } 2537 2538 if (dc->soc->has_powergate) 2539 tegra_powergate_power_off(dc->powergate); 2540 2541 clk_disable_unprepare(dc->clk); 2542 2543 return 0; 2544 } 2545 2546 static int tegra_dc_resume(struct device *dev) 2547 { 2548 struct tegra_dc *dc = dev_get_drvdata(dev); 2549 int err; 2550 2551 if (dc->soc->has_powergate) { 2552 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, 2553 dc->rst); 2554 if (err < 0) { 2555 dev_err(dev, "failed to power partition: %d\n", err); 2556 return err; 2557 } 2558 } else { 2559 err = clk_prepare_enable(dc->clk); 2560 if (err < 0) { 2561 dev_err(dev, "failed to enable clock: %d\n", err); 2562 return err; 2563 } 2564 2565 err = reset_control_deassert(dc->rst); 2566 if (err < 0) { 2567 dev_err(dev, "failed to deassert reset: %d\n", err); 2568 return err; 2569 } 2570 } 2571 2572 return 0; 2573 } 2574 #endif 2575 2576 static const struct dev_pm_ops tegra_dc_pm_ops = { 2577 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL) 2578 }; 2579 2580 struct platform_driver tegra_dc_driver = { 2581 .driver = { 2582 .name = "tegra-dc", 2583 .of_match_table = tegra_dc_of_match, 2584 .pm = &tegra_dc_pm_ops, 2585 }, 2586 .probe = tegra_dc_probe, 2587 .remove = tegra_dc_remove, 2588 }; 2589