1 /* 2 * Copyright (C) 2012 Avionic Design GmbH 3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 */ 9 10 #include <linux/clk.h> 11 #include <linux/debugfs.h> 12 #include <linux/iommu.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/reset.h> 16 17 #include <soc/tegra/pmc.h> 18 19 #include "dc.h" 20 #include "drm.h" 21 #include "gem.h" 22 #include "hub.h" 23 #include "plane.h" 24 25 #include <drm/drm_atomic.h> 26 #include <drm/drm_atomic_helper.h> 27 #include <drm/drm_plane_helper.h> 28 29 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 30 { 31 stats->frames = 0; 32 stats->vblank = 0; 33 stats->underflow = 0; 34 stats->overflow = 0; 35 } 36 37 /* Reads the active copy of a register. */ 38 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 39 { 40 u32 value; 41 42 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 43 value = tegra_dc_readl(dc, offset); 44 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 45 46 return value; 47 } 48 49 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 50 unsigned int offset) 51 { 52 if (offset >= 0x500 && offset <= 0x638) { 53 offset = 0x000 + (offset - 0x500); 54 return plane->offset + offset; 55 } 56 57 if (offset >= 0x700 && offset <= 0x719) { 58 offset = 0x180 + (offset - 0x700); 59 return plane->offset + offset; 60 } 61 62 if (offset >= 0x800 && offset <= 0x839) { 63 offset = 0x1c0 + (offset - 0x800); 64 return plane->offset + offset; 65 } 66 67 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 68 69 return plane->offset + offset; 70 } 71 72 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 73 unsigned int offset) 74 { 75 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 76 } 77 78 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 79 unsigned int offset) 80 { 81 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 82 } 83 84 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 85 { 86 struct device_node *np = dc->dev->of_node; 87 struct of_phandle_iterator it; 88 int err; 89 90 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 91 if (it.node == dev->of_node) 92 return true; 93 94 return false; 95 } 96 97 /* 98 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 99 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 100 * Latching happens mmediately if the display controller is in STOP mode or 101 * on the next frame boundary otherwise. 102 * 103 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 104 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 105 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 106 * into the ACTIVE copy, either immediately if the display controller is in 107 * STOP mode, or at the next frame boundary otherwise. 108 */ 109 void tegra_dc_commit(struct tegra_dc *dc) 110 { 111 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 112 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 113 } 114 115 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 116 unsigned int bpp) 117 { 118 fixed20_12 outf = dfixed_init(out); 119 fixed20_12 inf = dfixed_init(in); 120 u32 dda_inc; 121 int max; 122 123 if (v) 124 max = 15; 125 else { 126 switch (bpp) { 127 case 2: 128 max = 8; 129 break; 130 131 default: 132 WARN_ON_ONCE(1); 133 /* fallthrough */ 134 case 4: 135 max = 4; 136 break; 137 } 138 } 139 140 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 141 inf.full -= dfixed_const(1); 142 143 dda_inc = dfixed_div(inf, outf); 144 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 145 146 return dda_inc; 147 } 148 149 static inline u32 compute_initial_dda(unsigned int in) 150 { 151 fixed20_12 inf = dfixed_init(in); 152 return dfixed_frac(inf); 153 } 154 155 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 156 { 157 u32 background[3] = { 158 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 159 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 160 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 161 }; 162 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 163 BLEND_COLOR_KEY_NONE; 164 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 165 struct tegra_plane_state *state; 166 unsigned int i; 167 168 state = to_tegra_plane_state(plane->base.state); 169 170 /* alpha contribution is 1 minus sum of overlapping windows */ 171 for (i = 0; i < 3; i++) { 172 if (state->dependent[i]) 173 background[i] |= BLEND_CONTROL_DEPENDENT; 174 } 175 176 /* enable alpha blending if pixel format has an alpha component */ 177 if (!state->opaque) 178 foreground |= BLEND_CONTROL_ALPHA; 179 180 /* 181 * Disable blending and assume Window A is the bottom-most window, 182 * Window C is the top-most window and Window B is in the middle. 183 */ 184 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 185 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 186 187 switch (plane->index) { 188 case 0: 189 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 190 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 191 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 192 break; 193 194 case 1: 195 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 196 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 197 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 198 break; 199 200 case 2: 201 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 202 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 203 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 204 break; 205 } 206 } 207 208 static void tegra_plane_setup_blending(struct tegra_plane *plane, 209 const struct tegra_dc_window *window) 210 { 211 u32 value; 212 213 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 214 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 215 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 216 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 217 218 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 219 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 220 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 221 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 222 223 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 224 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 225 } 226 227 static void tegra_dc_setup_window(struct tegra_plane *plane, 228 const struct tegra_dc_window *window) 229 { 230 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 231 struct tegra_dc *dc = plane->dc; 232 bool yuv, planar; 233 u32 value; 234 235 /* 236 * For YUV planar modes, the number of bytes per pixel takes into 237 * account only the luma component and therefore is 1. 238 */ 239 yuv = tegra_plane_format_is_yuv(window->format, &planar); 240 if (!yuv) 241 bpp = window->bits_per_pixel / 8; 242 else 243 bpp = planar ? 1 : 2; 244 245 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 246 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 247 248 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 249 tegra_plane_writel(plane, value, DC_WIN_POSITION); 250 251 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 252 tegra_plane_writel(plane, value, DC_WIN_SIZE); 253 254 h_offset = window->src.x * bpp; 255 v_offset = window->src.y; 256 h_size = window->src.w * bpp; 257 v_size = window->src.h; 258 259 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 260 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 261 262 /* 263 * For DDA computations the number of bytes per pixel for YUV planar 264 * modes needs to take into account all Y, U and V components. 265 */ 266 if (yuv && planar) 267 bpp = 2; 268 269 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 270 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 271 272 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 273 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 274 275 h_dda = compute_initial_dda(window->src.x); 276 v_dda = compute_initial_dda(window->src.y); 277 278 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 279 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 280 281 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 282 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 283 284 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 285 286 if (yuv && planar) { 287 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 288 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 289 value = window->stride[1] << 16 | window->stride[0]; 290 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 291 } else { 292 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 293 } 294 295 if (window->bottom_up) 296 v_offset += window->src.h - 1; 297 298 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 299 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 300 301 if (dc->soc->supports_block_linear) { 302 unsigned long height = window->tiling.value; 303 304 switch (window->tiling.mode) { 305 case TEGRA_BO_TILING_MODE_PITCH: 306 value = DC_WINBUF_SURFACE_KIND_PITCH; 307 break; 308 309 case TEGRA_BO_TILING_MODE_TILED: 310 value = DC_WINBUF_SURFACE_KIND_TILED; 311 break; 312 313 case TEGRA_BO_TILING_MODE_BLOCK: 314 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 315 DC_WINBUF_SURFACE_KIND_BLOCK; 316 break; 317 } 318 319 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 320 } else { 321 switch (window->tiling.mode) { 322 case TEGRA_BO_TILING_MODE_PITCH: 323 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 324 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 325 break; 326 327 case TEGRA_BO_TILING_MODE_TILED: 328 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 329 DC_WIN_BUFFER_ADDR_MODE_TILE; 330 break; 331 332 case TEGRA_BO_TILING_MODE_BLOCK: 333 /* 334 * No need to handle this here because ->atomic_check 335 * will already have filtered it out. 336 */ 337 break; 338 } 339 340 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 341 } 342 343 value = WIN_ENABLE; 344 345 if (yuv) { 346 /* setup default colorspace conversion coefficients */ 347 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 348 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 349 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 350 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 351 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 352 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 353 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 354 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 355 356 value |= CSC_ENABLE; 357 } else if (window->bits_per_pixel < 24) { 358 value |= COLOR_EXPAND; 359 } 360 361 if (window->bottom_up) 362 value |= V_DIRECTION; 363 364 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 365 366 if (dc->soc->supports_blending) 367 tegra_plane_setup_blending(plane, window); 368 else 369 tegra_plane_setup_blending_legacy(plane); 370 } 371 372 static const u32 tegra20_primary_formats[] = { 373 DRM_FORMAT_ARGB4444, 374 DRM_FORMAT_ARGB1555, 375 DRM_FORMAT_RGB565, 376 DRM_FORMAT_RGBA5551, 377 DRM_FORMAT_ABGR8888, 378 DRM_FORMAT_ARGB8888, 379 /* non-native formats */ 380 DRM_FORMAT_XRGB1555, 381 DRM_FORMAT_RGBX5551, 382 DRM_FORMAT_XBGR8888, 383 DRM_FORMAT_XRGB8888, 384 }; 385 386 static const u64 tegra20_modifiers[] = { 387 DRM_FORMAT_MOD_LINEAR, 388 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 389 DRM_FORMAT_MOD_INVALID 390 }; 391 392 static const u32 tegra114_primary_formats[] = { 393 DRM_FORMAT_ARGB4444, 394 DRM_FORMAT_ARGB1555, 395 DRM_FORMAT_RGB565, 396 DRM_FORMAT_RGBA5551, 397 DRM_FORMAT_ABGR8888, 398 DRM_FORMAT_ARGB8888, 399 /* new on Tegra114 */ 400 DRM_FORMAT_ABGR4444, 401 DRM_FORMAT_ABGR1555, 402 DRM_FORMAT_BGRA5551, 403 DRM_FORMAT_XRGB1555, 404 DRM_FORMAT_RGBX5551, 405 DRM_FORMAT_XBGR1555, 406 DRM_FORMAT_BGRX5551, 407 DRM_FORMAT_BGR565, 408 DRM_FORMAT_BGRA8888, 409 DRM_FORMAT_RGBA8888, 410 DRM_FORMAT_XRGB8888, 411 DRM_FORMAT_XBGR8888, 412 }; 413 414 static const u32 tegra124_primary_formats[] = { 415 DRM_FORMAT_ARGB4444, 416 DRM_FORMAT_ARGB1555, 417 DRM_FORMAT_RGB565, 418 DRM_FORMAT_RGBA5551, 419 DRM_FORMAT_ABGR8888, 420 DRM_FORMAT_ARGB8888, 421 /* new on Tegra114 */ 422 DRM_FORMAT_ABGR4444, 423 DRM_FORMAT_ABGR1555, 424 DRM_FORMAT_BGRA5551, 425 DRM_FORMAT_XRGB1555, 426 DRM_FORMAT_RGBX5551, 427 DRM_FORMAT_XBGR1555, 428 DRM_FORMAT_BGRX5551, 429 DRM_FORMAT_BGR565, 430 DRM_FORMAT_BGRA8888, 431 DRM_FORMAT_RGBA8888, 432 DRM_FORMAT_XRGB8888, 433 DRM_FORMAT_XBGR8888, 434 /* new on Tegra124 */ 435 DRM_FORMAT_RGBX8888, 436 DRM_FORMAT_BGRX8888, 437 }; 438 439 static const u64 tegra124_modifiers[] = { 440 DRM_FORMAT_MOD_LINEAR, 441 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 442 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 443 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 444 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 445 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 446 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 447 DRM_FORMAT_MOD_INVALID 448 }; 449 450 static int tegra_plane_atomic_check(struct drm_plane *plane, 451 struct drm_plane_state *state) 452 { 453 struct tegra_plane_state *plane_state = to_tegra_plane_state(state); 454 struct tegra_bo_tiling *tiling = &plane_state->tiling; 455 struct tegra_plane *tegra = to_tegra_plane(plane); 456 struct tegra_dc *dc = to_tegra_dc(state->crtc); 457 unsigned int format; 458 int err; 459 460 /* no need for further checks if the plane is being disabled */ 461 if (!state->crtc) 462 return 0; 463 464 err = tegra_plane_format(state->fb->format->format, &format, 465 &plane_state->swap); 466 if (err < 0) 467 return err; 468 469 /* 470 * Tegra20 and Tegra30 are special cases here because they support 471 * only variants of specific formats with an alpha component, but not 472 * the corresponding opaque formats. However, the opaque formats can 473 * be emulated by disabling alpha blending for the plane. 474 */ 475 if (!dc->soc->supports_blending) { 476 if (!tegra_plane_format_has_alpha(format)) { 477 err = tegra_plane_format_get_alpha(format, &format); 478 if (err < 0) 479 return err; 480 481 plane_state->opaque = true; 482 } else { 483 plane_state->opaque = false; 484 } 485 486 tegra_plane_check_dependent(tegra, plane_state); 487 } 488 489 plane_state->format = format; 490 491 err = tegra_fb_get_tiling(state->fb, tiling); 492 if (err < 0) 493 return err; 494 495 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 496 !dc->soc->supports_block_linear) { 497 DRM_ERROR("hardware doesn't support block linear mode\n"); 498 return -EINVAL; 499 } 500 501 /* 502 * Tegra doesn't support different strides for U and V planes so we 503 * error out if the user tries to display a framebuffer with such a 504 * configuration. 505 */ 506 if (state->fb->format->num_planes > 2) { 507 if (state->fb->pitches[2] != state->fb->pitches[1]) { 508 DRM_ERROR("unsupported UV-plane configuration\n"); 509 return -EINVAL; 510 } 511 } 512 513 err = tegra_plane_state_add(tegra, state); 514 if (err < 0) 515 return err; 516 517 return 0; 518 } 519 520 static void tegra_plane_atomic_disable(struct drm_plane *plane, 521 struct drm_plane_state *old_state) 522 { 523 struct tegra_plane *p = to_tegra_plane(plane); 524 u32 value; 525 526 /* rien ne va plus */ 527 if (!old_state || !old_state->crtc) 528 return; 529 530 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 531 value &= ~WIN_ENABLE; 532 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 533 } 534 535 static void tegra_plane_atomic_update(struct drm_plane *plane, 536 struct drm_plane_state *old_state) 537 { 538 struct tegra_plane_state *state = to_tegra_plane_state(plane->state); 539 struct drm_framebuffer *fb = plane->state->fb; 540 struct tegra_plane *p = to_tegra_plane(plane); 541 struct tegra_dc_window window; 542 unsigned int i; 543 544 /* rien ne va plus */ 545 if (!plane->state->crtc || !plane->state->fb) 546 return; 547 548 if (!plane->state->visible) 549 return tegra_plane_atomic_disable(plane, old_state); 550 551 memset(&window, 0, sizeof(window)); 552 window.src.x = plane->state->src.x1 >> 16; 553 window.src.y = plane->state->src.y1 >> 16; 554 window.src.w = drm_rect_width(&plane->state->src) >> 16; 555 window.src.h = drm_rect_height(&plane->state->src) >> 16; 556 window.dst.x = plane->state->dst.x1; 557 window.dst.y = plane->state->dst.y1; 558 window.dst.w = drm_rect_width(&plane->state->dst); 559 window.dst.h = drm_rect_height(&plane->state->dst); 560 window.bits_per_pixel = fb->format->cpp[0] * 8; 561 window.bottom_up = tegra_fb_is_bottom_up(fb); 562 563 /* copy from state */ 564 window.zpos = plane->state->normalized_zpos; 565 window.tiling = state->tiling; 566 window.format = state->format; 567 window.swap = state->swap; 568 569 for (i = 0; i < fb->format->num_planes; i++) { 570 struct tegra_bo *bo = tegra_fb_get_plane(fb, i); 571 572 window.base[i] = bo->paddr + fb->offsets[i]; 573 574 /* 575 * Tegra uses a shared stride for UV planes. Framebuffers are 576 * already checked for this in the tegra_plane_atomic_check() 577 * function, so it's safe to ignore the V-plane pitch here. 578 */ 579 if (i < 2) 580 window.stride[i] = fb->pitches[i]; 581 } 582 583 tegra_dc_setup_window(p, &window); 584 } 585 586 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 587 .atomic_check = tegra_plane_atomic_check, 588 .atomic_disable = tegra_plane_atomic_disable, 589 .atomic_update = tegra_plane_atomic_update, 590 }; 591 592 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 593 { 594 /* 595 * Ideally this would use drm_crtc_mask(), but that would require the 596 * CRTC to already be in the mode_config's list of CRTCs. However, it 597 * will only be added to that list in the drm_crtc_init_with_planes() 598 * (in tegra_dc_init()), which in turn requires registration of these 599 * planes. So we have ourselves a nice little chicken and egg problem 600 * here. 601 * 602 * We work around this by manually creating the mask from the number 603 * of CRTCs that have been registered, and should therefore always be 604 * the same as drm_crtc_index() after registration. 605 */ 606 return 1 << drm->mode_config.num_crtc; 607 } 608 609 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 610 struct tegra_dc *dc) 611 { 612 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 613 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 614 struct tegra_plane *plane; 615 unsigned int num_formats; 616 const u64 *modifiers; 617 const u32 *formats; 618 int err; 619 620 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 621 if (!plane) 622 return ERR_PTR(-ENOMEM); 623 624 /* Always use window A as primary window */ 625 plane->offset = 0xa00; 626 plane->index = 0; 627 plane->dc = dc; 628 629 num_formats = dc->soc->num_primary_formats; 630 formats = dc->soc->primary_formats; 631 modifiers = dc->soc->modifiers; 632 633 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 634 &tegra_plane_funcs, formats, 635 num_formats, modifiers, type, NULL); 636 if (err < 0) { 637 kfree(plane); 638 return ERR_PTR(err); 639 } 640 641 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 642 643 if (dc->soc->supports_blending) 644 drm_plane_create_zpos_property(&plane->base, 0, 0, 255); 645 646 return &plane->base; 647 } 648 649 static const u32 tegra_cursor_plane_formats[] = { 650 DRM_FORMAT_RGBA8888, 651 }; 652 653 static int tegra_cursor_atomic_check(struct drm_plane *plane, 654 struct drm_plane_state *state) 655 { 656 struct tegra_plane *tegra = to_tegra_plane(plane); 657 int err; 658 659 /* no need for further checks if the plane is being disabled */ 660 if (!state->crtc) 661 return 0; 662 663 /* scaling not supported for cursor */ 664 if ((state->src_w >> 16 != state->crtc_w) || 665 (state->src_h >> 16 != state->crtc_h)) 666 return -EINVAL; 667 668 /* only square cursors supported */ 669 if (state->src_w != state->src_h) 670 return -EINVAL; 671 672 if (state->crtc_w != 32 && state->crtc_w != 64 && 673 state->crtc_w != 128 && state->crtc_w != 256) 674 return -EINVAL; 675 676 err = tegra_plane_state_add(tegra, state); 677 if (err < 0) 678 return err; 679 680 return 0; 681 } 682 683 static void tegra_cursor_atomic_update(struct drm_plane *plane, 684 struct drm_plane_state *old_state) 685 { 686 struct tegra_bo *bo = tegra_fb_get_plane(plane->state->fb, 0); 687 struct tegra_dc *dc = to_tegra_dc(plane->state->crtc); 688 struct drm_plane_state *state = plane->state; 689 u32 value = CURSOR_CLIP_DISPLAY; 690 691 /* rien ne va plus */ 692 if (!plane->state->crtc || !plane->state->fb) 693 return; 694 695 switch (state->crtc_w) { 696 case 32: 697 value |= CURSOR_SIZE_32x32; 698 break; 699 700 case 64: 701 value |= CURSOR_SIZE_64x64; 702 break; 703 704 case 128: 705 value |= CURSOR_SIZE_128x128; 706 break; 707 708 case 256: 709 value |= CURSOR_SIZE_256x256; 710 break; 711 712 default: 713 WARN(1, "cursor size %ux%u not supported\n", state->crtc_w, 714 state->crtc_h); 715 return; 716 } 717 718 value |= (bo->paddr >> 10) & 0x3fffff; 719 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 720 721 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 722 value = (bo->paddr >> 32) & 0x3; 723 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 724 #endif 725 726 /* enable cursor and set blend mode */ 727 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 728 value |= CURSOR_ENABLE; 729 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 730 731 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 732 value &= ~CURSOR_DST_BLEND_MASK; 733 value &= ~CURSOR_SRC_BLEND_MASK; 734 value |= CURSOR_MODE_NORMAL; 735 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 736 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 737 value |= CURSOR_ALPHA; 738 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 739 740 /* position the cursor */ 741 value = (state->crtc_y & 0x3fff) << 16 | (state->crtc_x & 0x3fff); 742 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 743 } 744 745 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 746 struct drm_plane_state *old_state) 747 { 748 struct tegra_dc *dc; 749 u32 value; 750 751 /* rien ne va plus */ 752 if (!old_state || !old_state->crtc) 753 return; 754 755 dc = to_tegra_dc(old_state->crtc); 756 757 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 758 value &= ~CURSOR_ENABLE; 759 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 760 } 761 762 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 763 .atomic_check = tegra_cursor_atomic_check, 764 .atomic_update = tegra_cursor_atomic_update, 765 .atomic_disable = tegra_cursor_atomic_disable, 766 }; 767 768 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 769 struct tegra_dc *dc) 770 { 771 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 772 struct tegra_plane *plane; 773 unsigned int num_formats; 774 const u32 *formats; 775 int err; 776 777 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 778 if (!plane) 779 return ERR_PTR(-ENOMEM); 780 781 /* 782 * This index is kind of fake. The cursor isn't a regular plane, but 783 * its update and activation request bits in DC_CMD_STATE_CONTROL do 784 * use the same programming. Setting this fake index here allows the 785 * code in tegra_add_plane_state() to do the right thing without the 786 * need to special-casing the cursor plane. 787 */ 788 plane->index = 6; 789 plane->dc = dc; 790 791 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 792 formats = tegra_cursor_plane_formats; 793 794 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 795 &tegra_plane_funcs, formats, 796 num_formats, NULL, 797 DRM_PLANE_TYPE_CURSOR, NULL); 798 if (err < 0) { 799 kfree(plane); 800 return ERR_PTR(err); 801 } 802 803 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 804 805 return &plane->base; 806 } 807 808 static const u32 tegra20_overlay_formats[] = { 809 DRM_FORMAT_ARGB4444, 810 DRM_FORMAT_ARGB1555, 811 DRM_FORMAT_RGB565, 812 DRM_FORMAT_RGBA5551, 813 DRM_FORMAT_ABGR8888, 814 DRM_FORMAT_ARGB8888, 815 /* non-native formats */ 816 DRM_FORMAT_XRGB1555, 817 DRM_FORMAT_RGBX5551, 818 DRM_FORMAT_XBGR8888, 819 DRM_FORMAT_XRGB8888, 820 /* planar formats */ 821 DRM_FORMAT_UYVY, 822 DRM_FORMAT_YUYV, 823 DRM_FORMAT_YUV420, 824 DRM_FORMAT_YUV422, 825 }; 826 827 static const u32 tegra114_overlay_formats[] = { 828 DRM_FORMAT_ARGB4444, 829 DRM_FORMAT_ARGB1555, 830 DRM_FORMAT_RGB565, 831 DRM_FORMAT_RGBA5551, 832 DRM_FORMAT_ABGR8888, 833 DRM_FORMAT_ARGB8888, 834 /* new on Tegra114 */ 835 DRM_FORMAT_ABGR4444, 836 DRM_FORMAT_ABGR1555, 837 DRM_FORMAT_BGRA5551, 838 DRM_FORMAT_XRGB1555, 839 DRM_FORMAT_RGBX5551, 840 DRM_FORMAT_XBGR1555, 841 DRM_FORMAT_BGRX5551, 842 DRM_FORMAT_BGR565, 843 DRM_FORMAT_BGRA8888, 844 DRM_FORMAT_RGBA8888, 845 DRM_FORMAT_XRGB8888, 846 DRM_FORMAT_XBGR8888, 847 /* planar formats */ 848 DRM_FORMAT_UYVY, 849 DRM_FORMAT_YUYV, 850 DRM_FORMAT_YUV420, 851 DRM_FORMAT_YUV422, 852 }; 853 854 static const u32 tegra124_overlay_formats[] = { 855 DRM_FORMAT_ARGB4444, 856 DRM_FORMAT_ARGB1555, 857 DRM_FORMAT_RGB565, 858 DRM_FORMAT_RGBA5551, 859 DRM_FORMAT_ABGR8888, 860 DRM_FORMAT_ARGB8888, 861 /* new on Tegra114 */ 862 DRM_FORMAT_ABGR4444, 863 DRM_FORMAT_ABGR1555, 864 DRM_FORMAT_BGRA5551, 865 DRM_FORMAT_XRGB1555, 866 DRM_FORMAT_RGBX5551, 867 DRM_FORMAT_XBGR1555, 868 DRM_FORMAT_BGRX5551, 869 DRM_FORMAT_BGR565, 870 DRM_FORMAT_BGRA8888, 871 DRM_FORMAT_RGBA8888, 872 DRM_FORMAT_XRGB8888, 873 DRM_FORMAT_XBGR8888, 874 /* new on Tegra124 */ 875 DRM_FORMAT_RGBX8888, 876 DRM_FORMAT_BGRX8888, 877 /* planar formats */ 878 DRM_FORMAT_UYVY, 879 DRM_FORMAT_YUYV, 880 DRM_FORMAT_YUV420, 881 DRM_FORMAT_YUV422, 882 }; 883 884 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 885 struct tegra_dc *dc, 886 unsigned int index, 887 bool cursor) 888 { 889 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 890 struct tegra_plane *plane; 891 unsigned int num_formats; 892 enum drm_plane_type type; 893 const u32 *formats; 894 int err; 895 896 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 897 if (!plane) 898 return ERR_PTR(-ENOMEM); 899 900 plane->offset = 0xa00 + 0x200 * index; 901 plane->index = index; 902 plane->dc = dc; 903 904 num_formats = dc->soc->num_overlay_formats; 905 formats = dc->soc->overlay_formats; 906 907 if (!cursor) 908 type = DRM_PLANE_TYPE_OVERLAY; 909 else 910 type = DRM_PLANE_TYPE_CURSOR; 911 912 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 913 &tegra_plane_funcs, formats, 914 num_formats, NULL, type, NULL); 915 if (err < 0) { 916 kfree(plane); 917 return ERR_PTR(err); 918 } 919 920 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 921 922 if (dc->soc->supports_blending) 923 drm_plane_create_zpos_property(&plane->base, 0, 0, 255); 924 925 return &plane->base; 926 } 927 928 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 929 struct tegra_dc *dc) 930 { 931 struct drm_plane *plane, *primary = NULL; 932 unsigned int i, j; 933 934 for (i = 0; i < dc->soc->num_wgrps; i++) { 935 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 936 937 if (wgrp->dc == dc->pipe) { 938 for (j = 0; j < wgrp->num_windows; j++) { 939 unsigned int index = wgrp->windows[j]; 940 941 plane = tegra_shared_plane_create(drm, dc, 942 wgrp->index, 943 index); 944 if (IS_ERR(plane)) 945 return plane; 946 947 /* 948 * Choose the first shared plane owned by this 949 * head as the primary plane. 950 */ 951 if (!primary) { 952 plane->type = DRM_PLANE_TYPE_PRIMARY; 953 primary = plane; 954 } 955 } 956 } 957 } 958 959 return primary; 960 } 961 962 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 963 struct tegra_dc *dc) 964 { 965 struct drm_plane *planes[2], *primary; 966 unsigned int planes_num; 967 unsigned int i; 968 int err; 969 970 primary = tegra_primary_plane_create(drm, dc); 971 if (IS_ERR(primary)) 972 return primary; 973 974 if (dc->soc->supports_cursor) 975 planes_num = 2; 976 else 977 planes_num = 1; 978 979 for (i = 0; i < planes_num; i++) { 980 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 981 false); 982 if (IS_ERR(planes[i])) { 983 err = PTR_ERR(planes[i]); 984 985 while (i--) 986 tegra_plane_funcs.destroy(planes[i]); 987 988 tegra_plane_funcs.destroy(primary); 989 return ERR_PTR(err); 990 } 991 } 992 993 return primary; 994 } 995 996 static void tegra_dc_destroy(struct drm_crtc *crtc) 997 { 998 drm_crtc_cleanup(crtc); 999 } 1000 1001 static void tegra_crtc_reset(struct drm_crtc *crtc) 1002 { 1003 struct tegra_dc_state *state; 1004 1005 if (crtc->state) 1006 __drm_atomic_helper_crtc_destroy_state(crtc->state); 1007 1008 kfree(crtc->state); 1009 crtc->state = NULL; 1010 1011 state = kzalloc(sizeof(*state), GFP_KERNEL); 1012 if (state) { 1013 crtc->state = &state->base; 1014 crtc->state->crtc = crtc; 1015 } 1016 1017 drm_crtc_vblank_reset(crtc); 1018 } 1019 1020 static struct drm_crtc_state * 1021 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1022 { 1023 struct tegra_dc_state *state = to_dc_state(crtc->state); 1024 struct tegra_dc_state *copy; 1025 1026 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 1027 if (!copy) 1028 return NULL; 1029 1030 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1031 copy->clk = state->clk; 1032 copy->pclk = state->pclk; 1033 copy->div = state->div; 1034 copy->planes = state->planes; 1035 1036 return ©->base; 1037 } 1038 1039 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1040 struct drm_crtc_state *state) 1041 { 1042 __drm_atomic_helper_crtc_destroy_state(state); 1043 kfree(state); 1044 } 1045 1046 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1047 1048 static const struct debugfs_reg32 tegra_dc_regs[] = { 1049 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1050 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1051 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1052 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1053 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1054 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1055 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1056 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1057 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1058 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1059 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1060 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1061 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1062 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1063 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1064 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1065 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1066 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1067 DEBUGFS_REG32(DC_CMD_INT_MASK), 1068 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1069 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1070 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1071 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1072 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1073 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1074 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1075 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1076 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1077 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1078 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1079 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1080 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1081 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1082 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1083 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1084 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1085 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1086 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1087 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1088 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1089 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1090 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1091 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1092 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1093 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1094 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1095 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1096 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1097 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1098 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1099 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1100 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1101 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1102 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1103 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1104 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1105 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1106 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1107 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1108 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1109 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1110 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1111 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1112 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1113 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1114 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1115 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1116 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1117 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1118 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1119 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1120 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1121 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1122 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1123 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1124 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1125 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1126 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1127 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1128 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1129 DEBUGFS_REG32(DC_DISP_ACTIVE), 1130 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1131 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1132 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1133 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1134 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1135 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1136 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1137 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1138 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1139 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1140 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1141 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1142 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1143 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1144 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1145 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1146 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1147 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1148 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1149 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1150 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1151 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1152 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1153 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1154 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1155 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1156 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1157 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1158 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1159 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1160 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1161 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1162 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1163 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1164 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1165 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1166 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1167 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1168 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1169 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1170 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1171 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1172 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1173 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1174 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1175 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1176 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1177 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1178 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1179 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1180 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1181 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1182 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1183 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1184 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1185 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1186 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1187 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1188 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1189 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1190 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1191 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1192 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1193 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1194 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1195 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1196 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1197 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1198 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1199 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1200 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1201 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1202 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1203 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1204 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1205 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1206 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1207 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1208 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1209 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1210 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1211 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1212 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1213 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1214 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1215 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1216 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1217 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1218 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1219 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1220 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1221 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1222 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1223 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1224 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1225 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1226 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1227 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1228 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1229 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1230 DEBUGFS_REG32(DC_WIN_POSITION), 1231 DEBUGFS_REG32(DC_WIN_SIZE), 1232 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1233 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1234 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1235 DEBUGFS_REG32(DC_WIN_DDA_INC), 1236 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1237 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1238 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1239 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1240 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1241 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1242 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1243 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1244 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1245 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1246 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1247 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1248 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1249 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1250 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1251 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1252 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1253 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1254 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1255 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1256 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1257 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1258 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1259 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1260 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1261 }; 1262 1263 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1264 { 1265 struct drm_info_node *node = s->private; 1266 struct tegra_dc *dc = node->info_ent->data; 1267 unsigned int i; 1268 int err = 0; 1269 1270 drm_modeset_lock(&dc->base.mutex, NULL); 1271 1272 if (!dc->base.state->active) { 1273 err = -EBUSY; 1274 goto unlock; 1275 } 1276 1277 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1278 unsigned int offset = tegra_dc_regs[i].offset; 1279 1280 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1281 offset, tegra_dc_readl(dc, offset)); 1282 } 1283 1284 unlock: 1285 drm_modeset_unlock(&dc->base.mutex); 1286 return err; 1287 } 1288 1289 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1290 { 1291 struct drm_info_node *node = s->private; 1292 struct tegra_dc *dc = node->info_ent->data; 1293 int err = 0; 1294 u32 value; 1295 1296 drm_modeset_lock(&dc->base.mutex, NULL); 1297 1298 if (!dc->base.state->active) { 1299 err = -EBUSY; 1300 goto unlock; 1301 } 1302 1303 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1304 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1305 tegra_dc_commit(dc); 1306 1307 drm_crtc_wait_one_vblank(&dc->base); 1308 drm_crtc_wait_one_vblank(&dc->base); 1309 1310 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1311 seq_printf(s, "%08x\n", value); 1312 1313 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1314 1315 unlock: 1316 drm_modeset_unlock(&dc->base.mutex); 1317 return err; 1318 } 1319 1320 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1321 { 1322 struct drm_info_node *node = s->private; 1323 struct tegra_dc *dc = node->info_ent->data; 1324 1325 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1326 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1327 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1328 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1329 1330 return 0; 1331 } 1332 1333 static struct drm_info_list debugfs_files[] = { 1334 { "regs", tegra_dc_show_regs, 0, NULL }, 1335 { "crc", tegra_dc_show_crc, 0, NULL }, 1336 { "stats", tegra_dc_show_stats, 0, NULL }, 1337 }; 1338 1339 static int tegra_dc_late_register(struct drm_crtc *crtc) 1340 { 1341 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1342 struct drm_minor *minor = crtc->dev->primary; 1343 struct dentry *root; 1344 struct tegra_dc *dc = to_tegra_dc(crtc); 1345 int err; 1346 1347 #ifdef CONFIG_DEBUG_FS 1348 root = crtc->debugfs_entry; 1349 #else 1350 root = NULL; 1351 #endif 1352 1353 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1354 GFP_KERNEL); 1355 if (!dc->debugfs_files) 1356 return -ENOMEM; 1357 1358 for (i = 0; i < count; i++) 1359 dc->debugfs_files[i].data = dc; 1360 1361 err = drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1362 if (err < 0) 1363 goto free; 1364 1365 return 0; 1366 1367 free: 1368 kfree(dc->debugfs_files); 1369 dc->debugfs_files = NULL; 1370 1371 return err; 1372 } 1373 1374 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1375 { 1376 unsigned int count = ARRAY_SIZE(debugfs_files); 1377 struct drm_minor *minor = crtc->dev->primary; 1378 struct tegra_dc *dc = to_tegra_dc(crtc); 1379 1380 drm_debugfs_remove_files(dc->debugfs_files, count, minor); 1381 kfree(dc->debugfs_files); 1382 dc->debugfs_files = NULL; 1383 } 1384 1385 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1386 { 1387 struct tegra_dc *dc = to_tegra_dc(crtc); 1388 1389 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1390 if (dc->syncpt && !dc->soc->has_nvdisplay) 1391 return host1x_syncpt_read(dc->syncpt); 1392 1393 /* fallback to software emulated VBLANK counter */ 1394 return (u32)drm_crtc_vblank_count(&dc->base); 1395 } 1396 1397 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1398 { 1399 struct tegra_dc *dc = to_tegra_dc(crtc); 1400 u32 value; 1401 1402 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1403 value |= VBLANK_INT; 1404 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1405 1406 return 0; 1407 } 1408 1409 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1410 { 1411 struct tegra_dc *dc = to_tegra_dc(crtc); 1412 u32 value; 1413 1414 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1415 value &= ~VBLANK_INT; 1416 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1417 } 1418 1419 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1420 .page_flip = drm_atomic_helper_page_flip, 1421 .set_config = drm_atomic_helper_set_config, 1422 .destroy = tegra_dc_destroy, 1423 .reset = tegra_crtc_reset, 1424 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1425 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1426 .late_register = tegra_dc_late_register, 1427 .early_unregister = tegra_dc_early_unregister, 1428 .get_vblank_counter = tegra_dc_get_vblank_counter, 1429 .enable_vblank = tegra_dc_enable_vblank, 1430 .disable_vblank = tegra_dc_disable_vblank, 1431 }; 1432 1433 static int tegra_dc_set_timings(struct tegra_dc *dc, 1434 struct drm_display_mode *mode) 1435 { 1436 unsigned int h_ref_to_sync = 1; 1437 unsigned int v_ref_to_sync = 1; 1438 unsigned long value; 1439 1440 if (!dc->soc->has_nvdisplay) { 1441 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1442 1443 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1444 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1445 } 1446 1447 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1448 ((mode->hsync_end - mode->hsync_start) << 0); 1449 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1450 1451 value = ((mode->vtotal - mode->vsync_end) << 16) | 1452 ((mode->htotal - mode->hsync_end) << 0); 1453 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1454 1455 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1456 ((mode->hsync_start - mode->hdisplay) << 0); 1457 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1458 1459 value = (mode->vdisplay << 16) | mode->hdisplay; 1460 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1461 1462 return 0; 1463 } 1464 1465 /** 1466 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1467 * state 1468 * @dc: display controller 1469 * @crtc_state: CRTC atomic state 1470 * @clk: parent clock for display controller 1471 * @pclk: pixel clock 1472 * @div: shift clock divider 1473 * 1474 * Returns: 1475 * 0 on success or a negative error-code on failure. 1476 */ 1477 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1478 struct drm_crtc_state *crtc_state, 1479 struct clk *clk, unsigned long pclk, 1480 unsigned int div) 1481 { 1482 struct tegra_dc_state *state = to_dc_state(crtc_state); 1483 1484 if (!clk_has_parent(dc->clk, clk)) 1485 return -EINVAL; 1486 1487 state->clk = clk; 1488 state->pclk = pclk; 1489 state->div = div; 1490 1491 return 0; 1492 } 1493 1494 static void tegra_dc_commit_state(struct tegra_dc *dc, 1495 struct tegra_dc_state *state) 1496 { 1497 u32 value; 1498 int err; 1499 1500 err = clk_set_parent(dc->clk, state->clk); 1501 if (err < 0) 1502 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 1503 1504 /* 1505 * Outputs may not want to change the parent clock rate. This is only 1506 * relevant to Tegra20 where only a single display PLL is available. 1507 * Since that PLL would typically be used for HDMI, an internal LVDS 1508 * panel would need to be driven by some other clock such as PLL_P 1509 * which is shared with other peripherals. Changing the clock rate 1510 * should therefore be avoided. 1511 */ 1512 if (state->pclk > 0) { 1513 err = clk_set_rate(state->clk, state->pclk); 1514 if (err < 0) 1515 dev_err(dc->dev, 1516 "failed to set clock rate to %lu Hz\n", 1517 state->pclk); 1518 } 1519 1520 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 1521 state->div); 1522 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1523 1524 if (!dc->soc->has_nvdisplay) { 1525 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; 1526 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 1527 } 1528 1529 err = clk_set_rate(dc->clk, state->pclk); 1530 if (err < 0) 1531 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 1532 dc->clk, state->pclk, err); 1533 } 1534 1535 static void tegra_dc_stop(struct tegra_dc *dc) 1536 { 1537 u32 value; 1538 1539 /* stop the display controller */ 1540 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1541 value &= ~DISP_CTRL_MODE_MASK; 1542 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1543 1544 tegra_dc_commit(dc); 1545 } 1546 1547 static bool tegra_dc_idle(struct tegra_dc *dc) 1548 { 1549 u32 value; 1550 1551 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 1552 1553 return (value & DISP_CTRL_MODE_MASK) == 0; 1554 } 1555 1556 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 1557 { 1558 timeout = jiffies + msecs_to_jiffies(timeout); 1559 1560 while (time_before(jiffies, timeout)) { 1561 if (tegra_dc_idle(dc)) 1562 return 0; 1563 1564 usleep_range(1000, 2000); 1565 } 1566 1567 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 1568 return -ETIMEDOUT; 1569 } 1570 1571 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 1572 struct drm_crtc_state *old_state) 1573 { 1574 struct tegra_dc *dc = to_tegra_dc(crtc); 1575 u32 value; 1576 1577 if (!tegra_dc_idle(dc)) { 1578 tegra_dc_stop(dc); 1579 1580 /* 1581 * Ignore the return value, there isn't anything useful to do 1582 * in case this fails. 1583 */ 1584 tegra_dc_wait_idle(dc, 100); 1585 } 1586 1587 /* 1588 * This should really be part of the RGB encoder driver, but clearing 1589 * these bits has the side-effect of stopping the display controller. 1590 * When that happens no VBLANK interrupts will be raised. At the same 1591 * time the encoder is disabled before the display controller, so the 1592 * above code is always going to timeout waiting for the controller 1593 * to go idle. 1594 * 1595 * Given the close coupling between the RGB encoder and the display 1596 * controller doing it here is still kind of okay. None of the other 1597 * encoder drivers require these bits to be cleared. 1598 * 1599 * XXX: Perhaps given that the display controller is switched off at 1600 * this point anyway maybe clearing these bits isn't even useful for 1601 * the RGB encoder? 1602 */ 1603 if (dc->rgb) { 1604 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1605 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1606 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 1607 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1608 } 1609 1610 tegra_dc_stats_reset(&dc->stats); 1611 drm_crtc_vblank_off(crtc); 1612 1613 spin_lock_irq(&crtc->dev->event_lock); 1614 1615 if (crtc->state->event) { 1616 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1617 crtc->state->event = NULL; 1618 } 1619 1620 spin_unlock_irq(&crtc->dev->event_lock); 1621 1622 pm_runtime_put_sync(dc->dev); 1623 } 1624 1625 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 1626 struct drm_crtc_state *old_state) 1627 { 1628 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1629 struct tegra_dc_state *state = to_dc_state(crtc->state); 1630 struct tegra_dc *dc = to_tegra_dc(crtc); 1631 u32 value; 1632 1633 pm_runtime_get_sync(dc->dev); 1634 1635 /* initialize display controller */ 1636 if (dc->syncpt) { 1637 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 1638 1639 if (dc->soc->has_nvdisplay) 1640 enable = 1 << 31; 1641 else 1642 enable = 1 << 8; 1643 1644 value = SYNCPT_CNTRL_NO_STALL; 1645 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1646 1647 value = enable | syncpt; 1648 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 1649 } 1650 1651 if (dc->soc->has_nvdisplay) { 1652 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 1653 DSC_OBUF_UF_INT; 1654 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1655 1656 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 1657 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 1658 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 1659 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 1660 VBLANK_INT | FRAME_END_INT; 1661 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1662 1663 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 1664 FRAME_END_INT; 1665 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1666 1667 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 1668 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1669 1670 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 1671 } else { 1672 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1673 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1674 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1675 1676 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1677 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1678 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1679 1680 /* initialize timer */ 1681 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1682 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1683 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1684 1685 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1686 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1687 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1688 1689 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1690 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1691 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1692 1693 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1694 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1695 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1696 } 1697 1698 if (dc->soc->supports_background_color) 1699 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 1700 else 1701 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1702 1703 /* apply PLL and pixel clock changes */ 1704 tegra_dc_commit_state(dc, state); 1705 1706 /* program display mode */ 1707 tegra_dc_set_timings(dc, mode); 1708 1709 /* interlacing isn't supported yet, so disable it */ 1710 if (dc->soc->supports_interlacing) { 1711 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 1712 value &= ~INTERLACE_ENABLE; 1713 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 1714 } 1715 1716 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1717 value &= ~DISP_CTRL_MODE_MASK; 1718 value |= DISP_CTRL_MODE_C_DISPLAY; 1719 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1720 1721 if (!dc->soc->has_nvdisplay) { 1722 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1723 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1724 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 1725 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1726 } 1727 1728 /* enable underflow reporting and display red for missing pixels */ 1729 if (dc->soc->has_nvdisplay) { 1730 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 1731 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 1732 } 1733 1734 tegra_dc_commit(dc); 1735 1736 drm_crtc_vblank_on(crtc); 1737 } 1738 1739 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 1740 struct drm_crtc_state *old_crtc_state) 1741 { 1742 unsigned long flags; 1743 1744 if (crtc->state->event) { 1745 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1746 1747 if (drm_crtc_vblank_get(crtc) != 0) 1748 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1749 else 1750 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 1751 1752 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1753 1754 crtc->state->event = NULL; 1755 } 1756 } 1757 1758 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 1759 struct drm_crtc_state *old_crtc_state) 1760 { 1761 struct tegra_dc_state *state = to_dc_state(crtc->state); 1762 struct tegra_dc *dc = to_tegra_dc(crtc); 1763 u32 value; 1764 1765 value = state->planes << 8 | GENERAL_UPDATE; 1766 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1767 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1768 1769 value = state->planes | GENERAL_ACT_REQ; 1770 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1771 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1772 } 1773 1774 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 1775 .atomic_begin = tegra_crtc_atomic_begin, 1776 .atomic_flush = tegra_crtc_atomic_flush, 1777 .atomic_enable = tegra_crtc_atomic_enable, 1778 .atomic_disable = tegra_crtc_atomic_disable, 1779 }; 1780 1781 static irqreturn_t tegra_dc_irq(int irq, void *data) 1782 { 1783 struct tegra_dc *dc = data; 1784 unsigned long status; 1785 1786 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 1787 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 1788 1789 if (status & FRAME_END_INT) { 1790 /* 1791 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 1792 */ 1793 dc->stats.frames++; 1794 } 1795 1796 if (status & VBLANK_INT) { 1797 /* 1798 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 1799 */ 1800 drm_crtc_handle_vblank(&dc->base); 1801 dc->stats.vblank++; 1802 } 1803 1804 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 1805 /* 1806 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 1807 */ 1808 dc->stats.underflow++; 1809 } 1810 1811 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 1812 /* 1813 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 1814 */ 1815 dc->stats.overflow++; 1816 } 1817 1818 if (status & HEAD_UF_INT) { 1819 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 1820 dc->stats.underflow++; 1821 } 1822 1823 return IRQ_HANDLED; 1824 } 1825 1826 static int tegra_dc_init(struct host1x_client *client) 1827 { 1828 struct drm_device *drm = dev_get_drvdata(client->parent); 1829 struct iommu_group *group = iommu_group_get(client->dev); 1830 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 1831 struct tegra_dc *dc = host1x_client_to_dc(client); 1832 struct tegra_drm *tegra = drm->dev_private; 1833 struct drm_plane *primary = NULL; 1834 struct drm_plane *cursor = NULL; 1835 int err; 1836 1837 dc->syncpt = host1x_syncpt_request(client, flags); 1838 if (!dc->syncpt) 1839 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 1840 1841 if (group && tegra->domain) { 1842 if (group != tegra->group) { 1843 err = iommu_attach_group(tegra->domain, group); 1844 if (err < 0) { 1845 dev_err(dc->dev, 1846 "failed to attach to domain: %d\n", 1847 err); 1848 return err; 1849 } 1850 1851 tegra->group = group; 1852 } 1853 1854 dc->domain = tegra->domain; 1855 } 1856 1857 if (dc->soc->wgrps) 1858 primary = tegra_dc_add_shared_planes(drm, dc); 1859 else 1860 primary = tegra_dc_add_planes(drm, dc); 1861 1862 if (IS_ERR(primary)) { 1863 err = PTR_ERR(primary); 1864 goto cleanup; 1865 } 1866 1867 if (dc->soc->supports_cursor) { 1868 cursor = tegra_dc_cursor_plane_create(drm, dc); 1869 if (IS_ERR(cursor)) { 1870 err = PTR_ERR(cursor); 1871 goto cleanup; 1872 } 1873 } else { 1874 /* dedicate one overlay to mouse cursor */ 1875 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 1876 if (IS_ERR(cursor)) { 1877 err = PTR_ERR(cursor); 1878 goto cleanup; 1879 } 1880 } 1881 1882 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 1883 &tegra_crtc_funcs, NULL); 1884 if (err < 0) 1885 goto cleanup; 1886 1887 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 1888 1889 /* 1890 * Keep track of the minimum pitch alignment across all display 1891 * controllers. 1892 */ 1893 if (dc->soc->pitch_align > tegra->pitch_align) 1894 tegra->pitch_align = dc->soc->pitch_align; 1895 1896 err = tegra_dc_rgb_init(drm, dc); 1897 if (err < 0 && err != -ENODEV) { 1898 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 1899 goto cleanup; 1900 } 1901 1902 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 1903 dev_name(dc->dev), dc); 1904 if (err < 0) { 1905 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 1906 err); 1907 goto cleanup; 1908 } 1909 1910 return 0; 1911 1912 cleanup: 1913 if (!IS_ERR_OR_NULL(cursor)) 1914 drm_plane_cleanup(cursor); 1915 1916 if (!IS_ERR(primary)) 1917 drm_plane_cleanup(primary); 1918 1919 if (group && dc->domain) { 1920 if (group == tegra->group) { 1921 iommu_detach_group(dc->domain, group); 1922 tegra->group = NULL; 1923 } 1924 1925 dc->domain = NULL; 1926 } 1927 1928 return err; 1929 } 1930 1931 static int tegra_dc_exit(struct host1x_client *client) 1932 { 1933 struct drm_device *drm = dev_get_drvdata(client->parent); 1934 struct iommu_group *group = iommu_group_get(client->dev); 1935 struct tegra_dc *dc = host1x_client_to_dc(client); 1936 struct tegra_drm *tegra = drm->dev_private; 1937 int err; 1938 1939 devm_free_irq(dc->dev, dc->irq, dc); 1940 1941 err = tegra_dc_rgb_exit(dc); 1942 if (err) { 1943 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 1944 return err; 1945 } 1946 1947 if (group && dc->domain) { 1948 if (group == tegra->group) { 1949 iommu_detach_group(dc->domain, group); 1950 tegra->group = NULL; 1951 } 1952 1953 dc->domain = NULL; 1954 } 1955 1956 host1x_syncpt_free(dc->syncpt); 1957 1958 return 0; 1959 } 1960 1961 static const struct host1x_client_ops dc_client_ops = { 1962 .init = tegra_dc_init, 1963 .exit = tegra_dc_exit, 1964 }; 1965 1966 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 1967 .supports_background_color = false, 1968 .supports_interlacing = false, 1969 .supports_cursor = false, 1970 .supports_block_linear = false, 1971 .supports_blending = false, 1972 .pitch_align = 8, 1973 .has_powergate = false, 1974 .coupled_pm = true, 1975 .has_nvdisplay = false, 1976 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 1977 .primary_formats = tegra20_primary_formats, 1978 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 1979 .overlay_formats = tegra20_overlay_formats, 1980 .modifiers = tegra20_modifiers, 1981 }; 1982 1983 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 1984 .supports_background_color = false, 1985 .supports_interlacing = false, 1986 .supports_cursor = false, 1987 .supports_block_linear = false, 1988 .supports_blending = false, 1989 .pitch_align = 8, 1990 .has_powergate = false, 1991 .coupled_pm = false, 1992 .has_nvdisplay = false, 1993 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 1994 .primary_formats = tegra20_primary_formats, 1995 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 1996 .overlay_formats = tegra20_overlay_formats, 1997 .modifiers = tegra20_modifiers, 1998 }; 1999 2000 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2001 .supports_background_color = false, 2002 .supports_interlacing = false, 2003 .supports_cursor = false, 2004 .supports_block_linear = false, 2005 .supports_blending = false, 2006 .pitch_align = 64, 2007 .has_powergate = true, 2008 .coupled_pm = false, 2009 .has_nvdisplay = false, 2010 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2011 .primary_formats = tegra114_primary_formats, 2012 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2013 .overlay_formats = tegra114_overlay_formats, 2014 .modifiers = tegra20_modifiers, 2015 }; 2016 2017 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 2018 .supports_background_color = true, 2019 .supports_interlacing = true, 2020 .supports_cursor = true, 2021 .supports_block_linear = true, 2022 .supports_blending = true, 2023 .pitch_align = 64, 2024 .has_powergate = true, 2025 .coupled_pm = false, 2026 .has_nvdisplay = false, 2027 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 2028 .primary_formats = tegra124_primary_formats, 2029 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 2030 .overlay_formats = tegra124_overlay_formats, 2031 .modifiers = tegra124_modifiers, 2032 }; 2033 2034 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2035 .supports_background_color = true, 2036 .supports_interlacing = true, 2037 .supports_cursor = true, 2038 .supports_block_linear = true, 2039 .supports_blending = true, 2040 .pitch_align = 64, 2041 .has_powergate = true, 2042 .coupled_pm = false, 2043 .has_nvdisplay = false, 2044 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2045 .primary_formats = tegra114_primary_formats, 2046 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2047 .overlay_formats = tegra114_overlay_formats, 2048 .modifiers = tegra124_modifiers, 2049 }; 2050 2051 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 2052 { 2053 .index = 0, 2054 .dc = 0, 2055 .windows = (const unsigned int[]) { 0 }, 2056 .num_windows = 1, 2057 }, { 2058 .index = 1, 2059 .dc = 1, 2060 .windows = (const unsigned int[]) { 1 }, 2061 .num_windows = 1, 2062 }, { 2063 .index = 2, 2064 .dc = 1, 2065 .windows = (const unsigned int[]) { 2 }, 2066 .num_windows = 1, 2067 }, { 2068 .index = 3, 2069 .dc = 2, 2070 .windows = (const unsigned int[]) { 3 }, 2071 .num_windows = 1, 2072 }, { 2073 .index = 4, 2074 .dc = 2, 2075 .windows = (const unsigned int[]) { 4 }, 2076 .num_windows = 1, 2077 }, { 2078 .index = 5, 2079 .dc = 2, 2080 .windows = (const unsigned int[]) { 5 }, 2081 .num_windows = 1, 2082 }, 2083 }; 2084 2085 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 2086 .supports_background_color = true, 2087 .supports_interlacing = true, 2088 .supports_cursor = true, 2089 .supports_block_linear = true, 2090 .supports_blending = true, 2091 .pitch_align = 64, 2092 .has_powergate = false, 2093 .coupled_pm = false, 2094 .has_nvdisplay = true, 2095 .wgrps = tegra186_dc_wgrps, 2096 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2097 }; 2098 2099 static const struct of_device_id tegra_dc_of_match[] = { 2100 { 2101 .compatible = "nvidia,tegra186-dc", 2102 .data = &tegra186_dc_soc_info, 2103 }, { 2104 .compatible = "nvidia,tegra210-dc", 2105 .data = &tegra210_dc_soc_info, 2106 }, { 2107 .compatible = "nvidia,tegra124-dc", 2108 .data = &tegra124_dc_soc_info, 2109 }, { 2110 .compatible = "nvidia,tegra114-dc", 2111 .data = &tegra114_dc_soc_info, 2112 }, { 2113 .compatible = "nvidia,tegra30-dc", 2114 .data = &tegra30_dc_soc_info, 2115 }, { 2116 .compatible = "nvidia,tegra20-dc", 2117 .data = &tegra20_dc_soc_info, 2118 }, { 2119 /* sentinel */ 2120 } 2121 }; 2122 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 2123 2124 static int tegra_dc_parse_dt(struct tegra_dc *dc) 2125 { 2126 struct device_node *np; 2127 u32 value = 0; 2128 int err; 2129 2130 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 2131 if (err < 0) { 2132 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 2133 2134 /* 2135 * If the nvidia,head property isn't present, try to find the 2136 * correct head number by looking up the position of this 2137 * display controller's node within the device tree. Assuming 2138 * that the nodes are ordered properly in the DTS file and 2139 * that the translation into a flattened device tree blob 2140 * preserves that ordering this will actually yield the right 2141 * head number. 2142 * 2143 * If those assumptions don't hold, this will still work for 2144 * cases where only a single display controller is used. 2145 */ 2146 for_each_matching_node(np, tegra_dc_of_match) { 2147 if (np == dc->dev->of_node) { 2148 of_node_put(np); 2149 break; 2150 } 2151 2152 value++; 2153 } 2154 } 2155 2156 dc->pipe = value; 2157 2158 return 0; 2159 } 2160 2161 static int tegra_dc_match_by_pipe(struct device *dev, void *data) 2162 { 2163 struct tegra_dc *dc = dev_get_drvdata(dev); 2164 unsigned int pipe = (unsigned long)data; 2165 2166 return dc->pipe == pipe; 2167 } 2168 2169 static int tegra_dc_couple(struct tegra_dc *dc) 2170 { 2171 /* 2172 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 2173 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 2174 * POWER_CONTROL registers during CRTC enabling. 2175 */ 2176 if (dc->soc->coupled_pm && dc->pipe == 1) { 2177 u32 flags = DL_FLAG_PM_RUNTIME | DL_FLAG_AUTOREMOVE; 2178 struct device_link *link; 2179 struct device *partner; 2180 2181 partner = driver_find_device(dc->dev->driver, NULL, NULL, 2182 tegra_dc_match_by_pipe); 2183 if (!partner) 2184 return -EPROBE_DEFER; 2185 2186 link = device_link_add(dc->dev, partner, flags); 2187 if (!link) { 2188 dev_err(dc->dev, "failed to link controllers\n"); 2189 return -EINVAL; 2190 } 2191 2192 dev_dbg(dc->dev, "coupled to %s\n", dev_name(partner)); 2193 } 2194 2195 return 0; 2196 } 2197 2198 static int tegra_dc_probe(struct platform_device *pdev) 2199 { 2200 struct resource *regs; 2201 struct tegra_dc *dc; 2202 int err; 2203 2204 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 2205 if (!dc) 2206 return -ENOMEM; 2207 2208 dc->soc = of_device_get_match_data(&pdev->dev); 2209 2210 INIT_LIST_HEAD(&dc->list); 2211 dc->dev = &pdev->dev; 2212 2213 err = tegra_dc_parse_dt(dc); 2214 if (err < 0) 2215 return err; 2216 2217 err = tegra_dc_couple(dc); 2218 if (err < 0) 2219 return err; 2220 2221 dc->clk = devm_clk_get(&pdev->dev, NULL); 2222 if (IS_ERR(dc->clk)) { 2223 dev_err(&pdev->dev, "failed to get clock\n"); 2224 return PTR_ERR(dc->clk); 2225 } 2226 2227 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 2228 if (IS_ERR(dc->rst)) { 2229 dev_err(&pdev->dev, "failed to get reset\n"); 2230 return PTR_ERR(dc->rst); 2231 } 2232 2233 /* assert reset and disable clock */ 2234 err = clk_prepare_enable(dc->clk); 2235 if (err < 0) 2236 return err; 2237 2238 usleep_range(2000, 4000); 2239 2240 err = reset_control_assert(dc->rst); 2241 if (err < 0) 2242 return err; 2243 2244 usleep_range(2000, 4000); 2245 2246 clk_disable_unprepare(dc->clk); 2247 2248 if (dc->soc->has_powergate) { 2249 if (dc->pipe == 0) 2250 dc->powergate = TEGRA_POWERGATE_DIS; 2251 else 2252 dc->powergate = TEGRA_POWERGATE_DISB; 2253 2254 tegra_powergate_power_off(dc->powergate); 2255 } 2256 2257 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0); 2258 dc->regs = devm_ioremap_resource(&pdev->dev, regs); 2259 if (IS_ERR(dc->regs)) 2260 return PTR_ERR(dc->regs); 2261 2262 dc->irq = platform_get_irq(pdev, 0); 2263 if (dc->irq < 0) { 2264 dev_err(&pdev->dev, "failed to get IRQ\n"); 2265 return -ENXIO; 2266 } 2267 2268 err = tegra_dc_rgb_probe(dc); 2269 if (err < 0 && err != -ENODEV) { 2270 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err); 2271 return err; 2272 } 2273 2274 platform_set_drvdata(pdev, dc); 2275 pm_runtime_enable(&pdev->dev); 2276 2277 INIT_LIST_HEAD(&dc->client.list); 2278 dc->client.ops = &dc_client_ops; 2279 dc->client.dev = &pdev->dev; 2280 2281 err = host1x_client_register(&dc->client); 2282 if (err < 0) { 2283 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 2284 err); 2285 return err; 2286 } 2287 2288 return 0; 2289 } 2290 2291 static int tegra_dc_remove(struct platform_device *pdev) 2292 { 2293 struct tegra_dc *dc = platform_get_drvdata(pdev); 2294 int err; 2295 2296 err = host1x_client_unregister(&dc->client); 2297 if (err < 0) { 2298 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 2299 err); 2300 return err; 2301 } 2302 2303 err = tegra_dc_rgb_remove(dc); 2304 if (err < 0) { 2305 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 2306 return err; 2307 } 2308 2309 pm_runtime_disable(&pdev->dev); 2310 2311 return 0; 2312 } 2313 2314 #ifdef CONFIG_PM 2315 static int tegra_dc_suspend(struct device *dev) 2316 { 2317 struct tegra_dc *dc = dev_get_drvdata(dev); 2318 int err; 2319 2320 err = reset_control_assert(dc->rst); 2321 if (err < 0) { 2322 dev_err(dev, "failed to assert reset: %d\n", err); 2323 return err; 2324 } 2325 2326 if (dc->soc->has_powergate) 2327 tegra_powergate_power_off(dc->powergate); 2328 2329 clk_disable_unprepare(dc->clk); 2330 2331 return 0; 2332 } 2333 2334 static int tegra_dc_resume(struct device *dev) 2335 { 2336 struct tegra_dc *dc = dev_get_drvdata(dev); 2337 int err; 2338 2339 if (dc->soc->has_powergate) { 2340 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, 2341 dc->rst); 2342 if (err < 0) { 2343 dev_err(dev, "failed to power partition: %d\n", err); 2344 return err; 2345 } 2346 } else { 2347 err = clk_prepare_enable(dc->clk); 2348 if (err < 0) { 2349 dev_err(dev, "failed to enable clock: %d\n", err); 2350 return err; 2351 } 2352 2353 err = reset_control_deassert(dc->rst); 2354 if (err < 0) { 2355 dev_err(dev, "failed to deassert reset: %d\n", err); 2356 return err; 2357 } 2358 } 2359 2360 return 0; 2361 } 2362 #endif 2363 2364 static const struct dev_pm_ops tegra_dc_pm_ops = { 2365 SET_RUNTIME_PM_OPS(tegra_dc_suspend, tegra_dc_resume, NULL) 2366 }; 2367 2368 struct platform_driver tegra_dc_driver = { 2369 .driver = { 2370 .name = "tegra-dc", 2371 .of_match_table = tegra_dc_of_match, 2372 .pm = &tegra_dc_pm_ops, 2373 }, 2374 .probe = tegra_dc_probe, 2375 .remove = tegra_dc_remove, 2376 }; 2377