1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/iommu.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/reset.h> 15 16 #include <soc/tegra/pmc.h> 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_debugfs.h> 21 #include <drm/drm_fourcc.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drm_vblank.h> 24 25 #include "dc.h" 26 #include "drm.h" 27 #include "gem.h" 28 #include "hub.h" 29 #include "plane.h" 30 31 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 32 struct drm_crtc_state *state); 33 34 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 35 { 36 stats->frames = 0; 37 stats->vblank = 0; 38 stats->underflow = 0; 39 stats->overflow = 0; 40 } 41 42 /* Reads the active copy of a register. */ 43 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 44 { 45 u32 value; 46 47 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 48 value = tegra_dc_readl(dc, offset); 49 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 50 51 return value; 52 } 53 54 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 55 unsigned int offset) 56 { 57 if (offset >= 0x500 && offset <= 0x638) { 58 offset = 0x000 + (offset - 0x500); 59 return plane->offset + offset; 60 } 61 62 if (offset >= 0x700 && offset <= 0x719) { 63 offset = 0x180 + (offset - 0x700); 64 return plane->offset + offset; 65 } 66 67 if (offset >= 0x800 && offset <= 0x839) { 68 offset = 0x1c0 + (offset - 0x800); 69 return plane->offset + offset; 70 } 71 72 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 73 74 return plane->offset + offset; 75 } 76 77 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 78 unsigned int offset) 79 { 80 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 81 } 82 83 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 84 unsigned int offset) 85 { 86 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 87 } 88 89 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 90 { 91 struct device_node *np = dc->dev->of_node; 92 struct of_phandle_iterator it; 93 int err; 94 95 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 96 if (it.node == dev->of_node) 97 return true; 98 99 return false; 100 } 101 102 /* 103 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 104 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 105 * Latching happens mmediately if the display controller is in STOP mode or 106 * on the next frame boundary otherwise. 107 * 108 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 109 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 110 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 111 * into the ACTIVE copy, either immediately if the display controller is in 112 * STOP mode, or at the next frame boundary otherwise. 113 */ 114 void tegra_dc_commit(struct tegra_dc *dc) 115 { 116 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 117 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 118 } 119 120 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 121 unsigned int bpp) 122 { 123 fixed20_12 outf = dfixed_init(out); 124 fixed20_12 inf = dfixed_init(in); 125 u32 dda_inc; 126 int max; 127 128 if (v) 129 max = 15; 130 else { 131 switch (bpp) { 132 case 2: 133 max = 8; 134 break; 135 136 default: 137 WARN_ON_ONCE(1); 138 fallthrough; 139 case 4: 140 max = 4; 141 break; 142 } 143 } 144 145 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 146 inf.full -= dfixed_const(1); 147 148 dda_inc = dfixed_div(inf, outf); 149 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 150 151 return dda_inc; 152 } 153 154 static inline u32 compute_initial_dda(unsigned int in) 155 { 156 fixed20_12 inf = dfixed_init(in); 157 return dfixed_frac(inf); 158 } 159 160 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 161 { 162 u32 background[3] = { 163 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 164 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 165 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 166 }; 167 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 168 BLEND_COLOR_KEY_NONE; 169 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 170 struct tegra_plane_state *state; 171 u32 blending[2]; 172 unsigned int i; 173 174 /* disable blending for non-overlapping case */ 175 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 176 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 177 178 state = to_tegra_plane_state(plane->base.state); 179 180 if (state->opaque) { 181 /* 182 * Since custom fix-weight blending isn't utilized and weight 183 * of top window is set to max, we can enforce dependent 184 * blending which in this case results in transparent bottom 185 * window if top window is opaque and if top window enables 186 * alpha blending, then bottom window is getting alpha value 187 * of 1 minus the sum of alpha components of the overlapping 188 * plane. 189 */ 190 background[0] |= BLEND_CONTROL_DEPENDENT; 191 background[1] |= BLEND_CONTROL_DEPENDENT; 192 193 /* 194 * The region where three windows overlap is the intersection 195 * of the two regions where two windows overlap. It contributes 196 * to the area if all of the windows on top of it have an alpha 197 * component. 198 */ 199 switch (state->base.normalized_zpos) { 200 case 0: 201 if (state->blending[0].alpha && 202 state->blending[1].alpha) 203 background[2] |= BLEND_CONTROL_DEPENDENT; 204 break; 205 206 case 1: 207 background[2] |= BLEND_CONTROL_DEPENDENT; 208 break; 209 } 210 } else { 211 /* 212 * Enable alpha blending if pixel format has an alpha 213 * component. 214 */ 215 foreground |= BLEND_CONTROL_ALPHA; 216 217 /* 218 * If any of the windows on top of this window is opaque, it 219 * will completely conceal this window within that area. If 220 * top window has an alpha component, it is blended over the 221 * bottom window. 222 */ 223 for (i = 0; i < 2; i++) { 224 if (state->blending[i].alpha && 225 state->blending[i].top) 226 background[i] |= BLEND_CONTROL_DEPENDENT; 227 } 228 229 switch (state->base.normalized_zpos) { 230 case 0: 231 if (state->blending[0].alpha && 232 state->blending[1].alpha) 233 background[2] |= BLEND_CONTROL_DEPENDENT; 234 break; 235 236 case 1: 237 /* 238 * When both middle and topmost windows have an alpha, 239 * these windows a mixed together and then the result 240 * is blended over the bottom window. 241 */ 242 if (state->blending[0].alpha && 243 state->blending[0].top) 244 background[2] |= BLEND_CONTROL_ALPHA; 245 246 if (state->blending[1].alpha && 247 state->blending[1].top) 248 background[2] |= BLEND_CONTROL_ALPHA; 249 break; 250 } 251 } 252 253 switch (state->base.normalized_zpos) { 254 case 0: 255 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 256 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 257 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 258 break; 259 260 case 1: 261 /* 262 * If window B / C is topmost, then X / Y registers are 263 * matching the order of blending[...] state indices, 264 * otherwise a swap is required. 265 */ 266 if (!state->blending[0].top && state->blending[1].top) { 267 blending[0] = foreground; 268 blending[1] = background[1]; 269 } else { 270 blending[0] = background[0]; 271 blending[1] = foreground; 272 } 273 274 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X); 275 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y); 276 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 277 break; 278 279 case 2: 280 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 281 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 282 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 283 break; 284 } 285 } 286 287 static void tegra_plane_setup_blending(struct tegra_plane *plane, 288 const struct tegra_dc_window *window) 289 { 290 u32 value; 291 292 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 293 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 294 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 295 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 296 297 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 298 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 299 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 300 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 301 302 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 303 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 304 } 305 306 static bool 307 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, 308 const struct tegra_dc_window *window) 309 { 310 struct tegra_dc *dc = plane->dc; 311 312 if (window->src.w == window->dst.w) 313 return false; 314 315 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 316 return false; 317 318 return true; 319 } 320 321 static bool 322 tegra_plane_use_vertical_filtering(struct tegra_plane *plane, 323 const struct tegra_dc_window *window) 324 { 325 struct tegra_dc *dc = plane->dc; 326 327 if (window->src.h == window->dst.h) 328 return false; 329 330 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 331 return false; 332 333 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) 334 return false; 335 336 return true; 337 } 338 339 static void tegra_dc_setup_window(struct tegra_plane *plane, 340 const struct tegra_dc_window *window) 341 { 342 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 343 struct tegra_dc *dc = plane->dc; 344 bool yuv, planar; 345 u32 value; 346 347 /* 348 * For YUV planar modes, the number of bytes per pixel takes into 349 * account only the luma component and therefore is 1. 350 */ 351 yuv = tegra_plane_format_is_yuv(window->format, &planar); 352 if (!yuv) 353 bpp = window->bits_per_pixel / 8; 354 else 355 bpp = planar ? 1 : 2; 356 357 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 358 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 359 360 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 361 tegra_plane_writel(plane, value, DC_WIN_POSITION); 362 363 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 364 tegra_plane_writel(plane, value, DC_WIN_SIZE); 365 366 h_offset = window->src.x * bpp; 367 v_offset = window->src.y; 368 h_size = window->src.w * bpp; 369 v_size = window->src.h; 370 371 if (window->reflect_x) 372 h_offset += (window->src.w - 1) * bpp; 373 374 if (window->reflect_y) 375 v_offset += window->src.h - 1; 376 377 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 378 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 379 380 /* 381 * For DDA computations the number of bytes per pixel for YUV planar 382 * modes needs to take into account all Y, U and V components. 383 */ 384 if (yuv && planar) 385 bpp = 2; 386 387 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 388 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 389 390 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 391 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 392 393 h_dda = compute_initial_dda(window->src.x); 394 v_dda = compute_initial_dda(window->src.y); 395 396 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 397 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 398 399 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 400 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 401 402 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 403 404 if (yuv && planar) { 405 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 406 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 407 value = window->stride[1] << 16 | window->stride[0]; 408 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 409 } else { 410 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 411 } 412 413 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 414 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 415 416 if (dc->soc->supports_block_linear) { 417 unsigned long height = window->tiling.value; 418 419 switch (window->tiling.mode) { 420 case TEGRA_BO_TILING_MODE_PITCH: 421 value = DC_WINBUF_SURFACE_KIND_PITCH; 422 break; 423 424 case TEGRA_BO_TILING_MODE_TILED: 425 value = DC_WINBUF_SURFACE_KIND_TILED; 426 break; 427 428 case TEGRA_BO_TILING_MODE_BLOCK: 429 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 430 DC_WINBUF_SURFACE_KIND_BLOCK; 431 break; 432 } 433 434 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 435 } else { 436 switch (window->tiling.mode) { 437 case TEGRA_BO_TILING_MODE_PITCH: 438 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 439 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 440 break; 441 442 case TEGRA_BO_TILING_MODE_TILED: 443 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 444 DC_WIN_BUFFER_ADDR_MODE_TILE; 445 break; 446 447 case TEGRA_BO_TILING_MODE_BLOCK: 448 /* 449 * No need to handle this here because ->atomic_check 450 * will already have filtered it out. 451 */ 452 break; 453 } 454 455 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 456 } 457 458 value = WIN_ENABLE; 459 460 if (yuv) { 461 /* setup default colorspace conversion coefficients */ 462 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 463 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 464 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 465 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 466 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 467 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 468 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 469 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 470 471 value |= CSC_ENABLE; 472 } else if (window->bits_per_pixel < 24) { 473 value |= COLOR_EXPAND; 474 } 475 476 if (window->reflect_x) 477 value |= H_DIRECTION; 478 479 if (window->reflect_y) 480 value |= V_DIRECTION; 481 482 if (tegra_plane_use_horizontal_filtering(plane, window)) { 483 /* 484 * Enable horizontal 6-tap filter and set filtering 485 * coefficients to the default values defined in TRM. 486 */ 487 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0)); 488 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1)); 489 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2)); 490 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3)); 491 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4)); 492 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5)); 493 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6)); 494 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7)); 495 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8)); 496 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9)); 497 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10)); 498 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11)); 499 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12)); 500 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13)); 501 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14)); 502 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15)); 503 504 value |= H_FILTER; 505 } 506 507 if (tegra_plane_use_vertical_filtering(plane, window)) { 508 unsigned int i, k; 509 510 /* 511 * Enable vertical 2-tap filter and set filtering 512 * coefficients to the default values defined in TRM. 513 */ 514 for (i = 0, k = 128; i < 16; i++, k -= 8) 515 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); 516 517 value |= V_FILTER; 518 } 519 520 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 521 522 if (dc->soc->has_legacy_blending) 523 tegra_plane_setup_blending_legacy(plane); 524 else 525 tegra_plane_setup_blending(plane, window); 526 } 527 528 static const u32 tegra20_primary_formats[] = { 529 DRM_FORMAT_ARGB4444, 530 DRM_FORMAT_ARGB1555, 531 DRM_FORMAT_RGB565, 532 DRM_FORMAT_RGBA5551, 533 DRM_FORMAT_ABGR8888, 534 DRM_FORMAT_ARGB8888, 535 /* non-native formats */ 536 DRM_FORMAT_XRGB1555, 537 DRM_FORMAT_RGBX5551, 538 DRM_FORMAT_XBGR8888, 539 DRM_FORMAT_XRGB8888, 540 }; 541 542 static const u64 tegra20_modifiers[] = { 543 DRM_FORMAT_MOD_LINEAR, 544 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 545 DRM_FORMAT_MOD_INVALID 546 }; 547 548 static const u32 tegra114_primary_formats[] = { 549 DRM_FORMAT_ARGB4444, 550 DRM_FORMAT_ARGB1555, 551 DRM_FORMAT_RGB565, 552 DRM_FORMAT_RGBA5551, 553 DRM_FORMAT_ABGR8888, 554 DRM_FORMAT_ARGB8888, 555 /* new on Tegra114 */ 556 DRM_FORMAT_ABGR4444, 557 DRM_FORMAT_ABGR1555, 558 DRM_FORMAT_BGRA5551, 559 DRM_FORMAT_XRGB1555, 560 DRM_FORMAT_RGBX5551, 561 DRM_FORMAT_XBGR1555, 562 DRM_FORMAT_BGRX5551, 563 DRM_FORMAT_BGR565, 564 DRM_FORMAT_BGRA8888, 565 DRM_FORMAT_RGBA8888, 566 DRM_FORMAT_XRGB8888, 567 DRM_FORMAT_XBGR8888, 568 }; 569 570 static const u32 tegra124_primary_formats[] = { 571 DRM_FORMAT_ARGB4444, 572 DRM_FORMAT_ARGB1555, 573 DRM_FORMAT_RGB565, 574 DRM_FORMAT_RGBA5551, 575 DRM_FORMAT_ABGR8888, 576 DRM_FORMAT_ARGB8888, 577 /* new on Tegra114 */ 578 DRM_FORMAT_ABGR4444, 579 DRM_FORMAT_ABGR1555, 580 DRM_FORMAT_BGRA5551, 581 DRM_FORMAT_XRGB1555, 582 DRM_FORMAT_RGBX5551, 583 DRM_FORMAT_XBGR1555, 584 DRM_FORMAT_BGRX5551, 585 DRM_FORMAT_BGR565, 586 DRM_FORMAT_BGRA8888, 587 DRM_FORMAT_RGBA8888, 588 DRM_FORMAT_XRGB8888, 589 DRM_FORMAT_XBGR8888, 590 /* new on Tegra124 */ 591 DRM_FORMAT_RGBX8888, 592 DRM_FORMAT_BGRX8888, 593 }; 594 595 static const u64 tegra124_modifiers[] = { 596 DRM_FORMAT_MOD_LINEAR, 597 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 598 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 599 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 600 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 603 DRM_FORMAT_MOD_INVALID 604 }; 605 606 static int tegra_plane_atomic_check(struct drm_plane *plane, 607 struct drm_atomic_state *state) 608 { 609 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 610 plane); 611 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 612 unsigned int supported_rotation = DRM_MODE_ROTATE_0 | 613 DRM_MODE_REFLECT_X | 614 DRM_MODE_REFLECT_Y; 615 unsigned int rotation = new_plane_state->rotation; 616 struct tegra_bo_tiling *tiling = &plane_state->tiling; 617 struct tegra_plane *tegra = to_tegra_plane(plane); 618 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); 619 int err; 620 621 /* no need for further checks if the plane is being disabled */ 622 if (!new_plane_state->crtc) 623 return 0; 624 625 err = tegra_plane_format(new_plane_state->fb->format->format, 626 &plane_state->format, 627 &plane_state->swap); 628 if (err < 0) 629 return err; 630 631 /* 632 * Tegra20 and Tegra30 are special cases here because they support 633 * only variants of specific formats with an alpha component, but not 634 * the corresponding opaque formats. However, the opaque formats can 635 * be emulated by disabling alpha blending for the plane. 636 */ 637 if (dc->soc->has_legacy_blending) { 638 err = tegra_plane_setup_legacy_state(tegra, plane_state); 639 if (err < 0) 640 return err; 641 } 642 643 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 644 if (err < 0) 645 return err; 646 647 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 648 !dc->soc->supports_block_linear) { 649 DRM_ERROR("hardware doesn't support block linear mode\n"); 650 return -EINVAL; 651 } 652 653 /* 654 * Older userspace used custom BO flag in order to specify the Y 655 * reflection, while modern userspace uses the generic DRM rotation 656 * property in order to achieve the same result. The legacy BO flag 657 * duplicates the DRM rotation property when both are set. 658 */ 659 if (tegra_fb_is_bottom_up(new_plane_state->fb)) 660 rotation |= DRM_MODE_REFLECT_Y; 661 662 rotation = drm_rotation_simplify(rotation, supported_rotation); 663 664 if (rotation & DRM_MODE_REFLECT_X) 665 plane_state->reflect_x = true; 666 else 667 plane_state->reflect_x = false; 668 669 if (rotation & DRM_MODE_REFLECT_Y) 670 plane_state->reflect_y = true; 671 else 672 plane_state->reflect_y = false; 673 674 /* 675 * Tegra doesn't support different strides for U and V planes so we 676 * error out if the user tries to display a framebuffer with such a 677 * configuration. 678 */ 679 if (new_plane_state->fb->format->num_planes > 2) { 680 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { 681 DRM_ERROR("unsupported UV-plane configuration\n"); 682 return -EINVAL; 683 } 684 } 685 686 err = tegra_plane_state_add(tegra, new_plane_state); 687 if (err < 0) 688 return err; 689 690 return 0; 691 } 692 693 static void tegra_plane_atomic_disable(struct drm_plane *plane, 694 struct drm_atomic_state *state) 695 { 696 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 697 plane); 698 struct tegra_plane *p = to_tegra_plane(plane); 699 u32 value; 700 701 /* rien ne va plus */ 702 if (!old_state || !old_state->crtc) 703 return; 704 705 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 706 value &= ~WIN_ENABLE; 707 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 708 } 709 710 static void tegra_plane_atomic_update(struct drm_plane *plane, 711 struct drm_atomic_state *state) 712 { 713 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 714 plane); 715 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 716 struct drm_framebuffer *fb = new_state->fb; 717 struct tegra_plane *p = to_tegra_plane(plane); 718 struct tegra_dc_window window; 719 unsigned int i; 720 721 /* rien ne va plus */ 722 if (!new_state->crtc || !new_state->fb) 723 return; 724 725 if (!new_state->visible) 726 return tegra_plane_atomic_disable(plane, state); 727 728 memset(&window, 0, sizeof(window)); 729 window.src.x = new_state->src.x1 >> 16; 730 window.src.y = new_state->src.y1 >> 16; 731 window.src.w = drm_rect_width(&new_state->src) >> 16; 732 window.src.h = drm_rect_height(&new_state->src) >> 16; 733 window.dst.x = new_state->dst.x1; 734 window.dst.y = new_state->dst.y1; 735 window.dst.w = drm_rect_width(&new_state->dst); 736 window.dst.h = drm_rect_height(&new_state->dst); 737 window.bits_per_pixel = fb->format->cpp[0] * 8; 738 window.reflect_x = tegra_plane_state->reflect_x; 739 window.reflect_y = tegra_plane_state->reflect_y; 740 741 /* copy from state */ 742 window.zpos = new_state->normalized_zpos; 743 window.tiling = tegra_plane_state->tiling; 744 window.format = tegra_plane_state->format; 745 window.swap = tegra_plane_state->swap; 746 747 for (i = 0; i < fb->format->num_planes; i++) { 748 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; 749 750 /* 751 * Tegra uses a shared stride for UV planes. Framebuffers are 752 * already checked for this in the tegra_plane_atomic_check() 753 * function, so it's safe to ignore the V-plane pitch here. 754 */ 755 if (i < 2) 756 window.stride[i] = fb->pitches[i]; 757 } 758 759 tegra_dc_setup_window(p, &window); 760 } 761 762 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 763 .prepare_fb = tegra_plane_prepare_fb, 764 .cleanup_fb = tegra_plane_cleanup_fb, 765 .atomic_check = tegra_plane_atomic_check, 766 .atomic_disable = tegra_plane_atomic_disable, 767 .atomic_update = tegra_plane_atomic_update, 768 }; 769 770 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 771 { 772 /* 773 * Ideally this would use drm_crtc_mask(), but that would require the 774 * CRTC to already be in the mode_config's list of CRTCs. However, it 775 * will only be added to that list in the drm_crtc_init_with_planes() 776 * (in tegra_dc_init()), which in turn requires registration of these 777 * planes. So we have ourselves a nice little chicken and egg problem 778 * here. 779 * 780 * We work around this by manually creating the mask from the number 781 * of CRTCs that have been registered, and should therefore always be 782 * the same as drm_crtc_index() after registration. 783 */ 784 return 1 << drm->mode_config.num_crtc; 785 } 786 787 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 788 struct tegra_dc *dc) 789 { 790 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 791 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 792 struct tegra_plane *plane; 793 unsigned int num_formats; 794 const u64 *modifiers; 795 const u32 *formats; 796 int err; 797 798 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 799 if (!plane) 800 return ERR_PTR(-ENOMEM); 801 802 /* Always use window A as primary window */ 803 plane->offset = 0xa00; 804 plane->index = 0; 805 plane->dc = dc; 806 807 num_formats = dc->soc->num_primary_formats; 808 formats = dc->soc->primary_formats; 809 modifiers = dc->soc->modifiers; 810 811 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 812 &tegra_plane_funcs, formats, 813 num_formats, modifiers, type, NULL); 814 if (err < 0) { 815 kfree(plane); 816 return ERR_PTR(err); 817 } 818 819 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 820 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 821 822 err = drm_plane_create_rotation_property(&plane->base, 823 DRM_MODE_ROTATE_0, 824 DRM_MODE_ROTATE_0 | 825 DRM_MODE_ROTATE_180 | 826 DRM_MODE_REFLECT_X | 827 DRM_MODE_REFLECT_Y); 828 if (err < 0) 829 dev_err(dc->dev, "failed to create rotation property: %d\n", 830 err); 831 832 return &plane->base; 833 } 834 835 static const u32 tegra_legacy_cursor_plane_formats[] = { 836 DRM_FORMAT_RGBA8888, 837 }; 838 839 static const u32 tegra_cursor_plane_formats[] = { 840 DRM_FORMAT_ARGB8888, 841 }; 842 843 static int tegra_cursor_atomic_check(struct drm_plane *plane, 844 struct drm_atomic_state *state) 845 { 846 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 847 plane); 848 struct tegra_plane *tegra = to_tegra_plane(plane); 849 int err; 850 851 /* no need for further checks if the plane is being disabled */ 852 if (!new_plane_state->crtc) 853 return 0; 854 855 /* scaling not supported for cursor */ 856 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || 857 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) 858 return -EINVAL; 859 860 /* only square cursors supported */ 861 if (new_plane_state->src_w != new_plane_state->src_h) 862 return -EINVAL; 863 864 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && 865 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) 866 return -EINVAL; 867 868 err = tegra_plane_state_add(tegra, new_plane_state); 869 if (err < 0) 870 return err; 871 872 return 0; 873 } 874 875 static void tegra_cursor_atomic_update(struct drm_plane *plane, 876 struct drm_atomic_state *state) 877 { 878 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 879 plane); 880 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 881 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 882 struct tegra_drm *tegra = plane->dev->dev_private; 883 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 884 u64 dma_mask = *dc->dev->dma_mask; 885 #endif 886 unsigned int x, y; 887 u32 value = 0; 888 889 /* rien ne va plus */ 890 if (!new_state->crtc || !new_state->fb) 891 return; 892 893 /* 894 * Legacy display supports hardware clipping of the cursor, but 895 * nvdisplay relies on software to clip the cursor to the screen. 896 */ 897 if (!dc->soc->has_nvdisplay) 898 value |= CURSOR_CLIP_DISPLAY; 899 900 switch (new_state->crtc_w) { 901 case 32: 902 value |= CURSOR_SIZE_32x32; 903 break; 904 905 case 64: 906 value |= CURSOR_SIZE_64x64; 907 break; 908 909 case 128: 910 value |= CURSOR_SIZE_128x128; 911 break; 912 913 case 256: 914 value |= CURSOR_SIZE_256x256; 915 break; 916 917 default: 918 WARN(1, "cursor size %ux%u not supported\n", 919 new_state->crtc_w, new_state->crtc_h); 920 return; 921 } 922 923 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; 924 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 925 926 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 927 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); 928 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 929 #endif 930 931 /* enable cursor and set blend mode */ 932 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 933 value |= CURSOR_ENABLE; 934 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 935 936 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 937 value &= ~CURSOR_DST_BLEND_MASK; 938 value &= ~CURSOR_SRC_BLEND_MASK; 939 940 if (dc->soc->has_nvdisplay) 941 value &= ~CURSOR_COMPOSITION_MODE_XOR; 942 else 943 value |= CURSOR_MODE_NORMAL; 944 945 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 946 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 947 value |= CURSOR_ALPHA; 948 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 949 950 /* nvdisplay relies on software for clipping */ 951 if (dc->soc->has_nvdisplay) { 952 struct drm_rect src; 953 954 x = new_state->dst.x1; 955 y = new_state->dst.y1; 956 957 drm_rect_fp_to_int(&src, &new_state->src); 958 959 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); 960 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); 961 962 value = (drm_rect_height(&src) & tegra->vmask) << 16 | 963 (drm_rect_width(&src) & tegra->hmask); 964 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); 965 } else { 966 x = new_state->crtc_x; 967 y = new_state->crtc_y; 968 } 969 970 /* position the cursor */ 971 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); 972 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 973 } 974 975 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 976 struct drm_atomic_state *state) 977 { 978 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 979 plane); 980 struct tegra_dc *dc; 981 u32 value; 982 983 /* rien ne va plus */ 984 if (!old_state || !old_state->crtc) 985 return; 986 987 dc = to_tegra_dc(old_state->crtc); 988 989 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 990 value &= ~CURSOR_ENABLE; 991 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 992 } 993 994 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 995 .prepare_fb = tegra_plane_prepare_fb, 996 .cleanup_fb = tegra_plane_cleanup_fb, 997 .atomic_check = tegra_cursor_atomic_check, 998 .atomic_update = tegra_cursor_atomic_update, 999 .atomic_disable = tegra_cursor_atomic_disable, 1000 }; 1001 1002 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 1003 struct tegra_dc *dc) 1004 { 1005 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1006 struct tegra_plane *plane; 1007 unsigned int num_formats; 1008 const u32 *formats; 1009 int err; 1010 1011 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1012 if (!plane) 1013 return ERR_PTR(-ENOMEM); 1014 1015 /* 1016 * This index is kind of fake. The cursor isn't a regular plane, but 1017 * its update and activation request bits in DC_CMD_STATE_CONTROL do 1018 * use the same programming. Setting this fake index here allows the 1019 * code in tegra_add_plane_state() to do the right thing without the 1020 * need to special-casing the cursor plane. 1021 */ 1022 plane->index = 6; 1023 plane->dc = dc; 1024 1025 if (!dc->soc->has_nvdisplay) { 1026 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats); 1027 formats = tegra_legacy_cursor_plane_formats; 1028 } else { 1029 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 1030 formats = tegra_cursor_plane_formats; 1031 } 1032 1033 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1034 &tegra_plane_funcs, formats, 1035 num_formats, NULL, 1036 DRM_PLANE_TYPE_CURSOR, NULL); 1037 if (err < 0) { 1038 kfree(plane); 1039 return ERR_PTR(err); 1040 } 1041 1042 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 1043 drm_plane_create_zpos_immutable_property(&plane->base, 255); 1044 1045 return &plane->base; 1046 } 1047 1048 static const u32 tegra20_overlay_formats[] = { 1049 DRM_FORMAT_ARGB4444, 1050 DRM_FORMAT_ARGB1555, 1051 DRM_FORMAT_RGB565, 1052 DRM_FORMAT_RGBA5551, 1053 DRM_FORMAT_ABGR8888, 1054 DRM_FORMAT_ARGB8888, 1055 /* non-native formats */ 1056 DRM_FORMAT_XRGB1555, 1057 DRM_FORMAT_RGBX5551, 1058 DRM_FORMAT_XBGR8888, 1059 DRM_FORMAT_XRGB8888, 1060 /* planar formats */ 1061 DRM_FORMAT_UYVY, 1062 DRM_FORMAT_YUYV, 1063 DRM_FORMAT_YUV420, 1064 DRM_FORMAT_YUV422, 1065 }; 1066 1067 static const u32 tegra114_overlay_formats[] = { 1068 DRM_FORMAT_ARGB4444, 1069 DRM_FORMAT_ARGB1555, 1070 DRM_FORMAT_RGB565, 1071 DRM_FORMAT_RGBA5551, 1072 DRM_FORMAT_ABGR8888, 1073 DRM_FORMAT_ARGB8888, 1074 /* new on Tegra114 */ 1075 DRM_FORMAT_ABGR4444, 1076 DRM_FORMAT_ABGR1555, 1077 DRM_FORMAT_BGRA5551, 1078 DRM_FORMAT_XRGB1555, 1079 DRM_FORMAT_RGBX5551, 1080 DRM_FORMAT_XBGR1555, 1081 DRM_FORMAT_BGRX5551, 1082 DRM_FORMAT_BGR565, 1083 DRM_FORMAT_BGRA8888, 1084 DRM_FORMAT_RGBA8888, 1085 DRM_FORMAT_XRGB8888, 1086 DRM_FORMAT_XBGR8888, 1087 /* planar formats */ 1088 DRM_FORMAT_UYVY, 1089 DRM_FORMAT_YUYV, 1090 DRM_FORMAT_YUV420, 1091 DRM_FORMAT_YUV422, 1092 }; 1093 1094 static const u32 tegra124_overlay_formats[] = { 1095 DRM_FORMAT_ARGB4444, 1096 DRM_FORMAT_ARGB1555, 1097 DRM_FORMAT_RGB565, 1098 DRM_FORMAT_RGBA5551, 1099 DRM_FORMAT_ABGR8888, 1100 DRM_FORMAT_ARGB8888, 1101 /* new on Tegra114 */ 1102 DRM_FORMAT_ABGR4444, 1103 DRM_FORMAT_ABGR1555, 1104 DRM_FORMAT_BGRA5551, 1105 DRM_FORMAT_XRGB1555, 1106 DRM_FORMAT_RGBX5551, 1107 DRM_FORMAT_XBGR1555, 1108 DRM_FORMAT_BGRX5551, 1109 DRM_FORMAT_BGR565, 1110 DRM_FORMAT_BGRA8888, 1111 DRM_FORMAT_RGBA8888, 1112 DRM_FORMAT_XRGB8888, 1113 DRM_FORMAT_XBGR8888, 1114 /* new on Tegra124 */ 1115 DRM_FORMAT_RGBX8888, 1116 DRM_FORMAT_BGRX8888, 1117 /* planar formats */ 1118 DRM_FORMAT_UYVY, 1119 DRM_FORMAT_YUYV, 1120 DRM_FORMAT_YUV420, 1121 DRM_FORMAT_YUV422, 1122 }; 1123 1124 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 1125 struct tegra_dc *dc, 1126 unsigned int index, 1127 bool cursor) 1128 { 1129 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1130 struct tegra_plane *plane; 1131 unsigned int num_formats; 1132 enum drm_plane_type type; 1133 const u32 *formats; 1134 int err; 1135 1136 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1137 if (!plane) 1138 return ERR_PTR(-ENOMEM); 1139 1140 plane->offset = 0xa00 + 0x200 * index; 1141 plane->index = index; 1142 plane->dc = dc; 1143 1144 num_formats = dc->soc->num_overlay_formats; 1145 formats = dc->soc->overlay_formats; 1146 1147 if (!cursor) 1148 type = DRM_PLANE_TYPE_OVERLAY; 1149 else 1150 type = DRM_PLANE_TYPE_CURSOR; 1151 1152 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1153 &tegra_plane_funcs, formats, 1154 num_formats, NULL, type, NULL); 1155 if (err < 0) { 1156 kfree(plane); 1157 return ERR_PTR(err); 1158 } 1159 1160 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 1161 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 1162 1163 err = drm_plane_create_rotation_property(&plane->base, 1164 DRM_MODE_ROTATE_0, 1165 DRM_MODE_ROTATE_0 | 1166 DRM_MODE_ROTATE_180 | 1167 DRM_MODE_REFLECT_X | 1168 DRM_MODE_REFLECT_Y); 1169 if (err < 0) 1170 dev_err(dc->dev, "failed to create rotation property: %d\n", 1171 err); 1172 1173 return &plane->base; 1174 } 1175 1176 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 1177 struct tegra_dc *dc) 1178 { 1179 struct drm_plane *plane, *primary = NULL; 1180 unsigned int i, j; 1181 1182 for (i = 0; i < dc->soc->num_wgrps; i++) { 1183 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1184 1185 if (wgrp->dc == dc->pipe) { 1186 for (j = 0; j < wgrp->num_windows; j++) { 1187 unsigned int index = wgrp->windows[j]; 1188 1189 plane = tegra_shared_plane_create(drm, dc, 1190 wgrp->index, 1191 index); 1192 if (IS_ERR(plane)) 1193 return plane; 1194 1195 /* 1196 * Choose the first shared plane owned by this 1197 * head as the primary plane. 1198 */ 1199 if (!primary) { 1200 plane->type = DRM_PLANE_TYPE_PRIMARY; 1201 primary = plane; 1202 } 1203 } 1204 } 1205 } 1206 1207 return primary; 1208 } 1209 1210 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 1211 struct tegra_dc *dc) 1212 { 1213 struct drm_plane *planes[2], *primary; 1214 unsigned int planes_num; 1215 unsigned int i; 1216 int err; 1217 1218 primary = tegra_primary_plane_create(drm, dc); 1219 if (IS_ERR(primary)) 1220 return primary; 1221 1222 if (dc->soc->supports_cursor) 1223 planes_num = 2; 1224 else 1225 planes_num = 1; 1226 1227 for (i = 0; i < planes_num; i++) { 1228 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 1229 false); 1230 if (IS_ERR(planes[i])) { 1231 err = PTR_ERR(planes[i]); 1232 1233 while (i--) 1234 tegra_plane_funcs.destroy(planes[i]); 1235 1236 tegra_plane_funcs.destroy(primary); 1237 return ERR_PTR(err); 1238 } 1239 } 1240 1241 return primary; 1242 } 1243 1244 static void tegra_dc_destroy(struct drm_crtc *crtc) 1245 { 1246 drm_crtc_cleanup(crtc); 1247 } 1248 1249 static void tegra_crtc_reset(struct drm_crtc *crtc) 1250 { 1251 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 1252 1253 if (crtc->state) 1254 tegra_crtc_atomic_destroy_state(crtc, crtc->state); 1255 1256 __drm_atomic_helper_crtc_reset(crtc, &state->base); 1257 } 1258 1259 static struct drm_crtc_state * 1260 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1261 { 1262 struct tegra_dc_state *state = to_dc_state(crtc->state); 1263 struct tegra_dc_state *copy; 1264 1265 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 1266 if (!copy) 1267 return NULL; 1268 1269 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1270 copy->clk = state->clk; 1271 copy->pclk = state->pclk; 1272 copy->div = state->div; 1273 copy->planes = state->planes; 1274 1275 return ©->base; 1276 } 1277 1278 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1279 struct drm_crtc_state *state) 1280 { 1281 __drm_atomic_helper_crtc_destroy_state(state); 1282 kfree(state); 1283 } 1284 1285 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1286 1287 static const struct debugfs_reg32 tegra_dc_regs[] = { 1288 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1289 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1290 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1291 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1292 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1293 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1294 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1295 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1296 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1297 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1298 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1299 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1300 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1301 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1302 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1303 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1304 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1305 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1306 DEBUGFS_REG32(DC_CMD_INT_MASK), 1307 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1308 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1309 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1310 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1311 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1312 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1313 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1314 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1315 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1316 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1317 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1318 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1319 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1320 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1321 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1322 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1323 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1324 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1325 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1326 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1327 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1328 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1329 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1330 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1331 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1332 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1333 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1334 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1335 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1336 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1337 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1338 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1339 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1340 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1341 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1342 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1343 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1344 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1345 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1346 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1347 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1348 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1349 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1350 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1351 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1352 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1353 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1354 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1355 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1356 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1357 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1358 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1359 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1360 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1361 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1362 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1363 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1364 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1365 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1366 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1367 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1368 DEBUGFS_REG32(DC_DISP_ACTIVE), 1369 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1370 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1371 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1372 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1373 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1374 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1375 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1376 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1377 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1378 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1379 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1380 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1381 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1382 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1383 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1384 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1385 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1386 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1387 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1388 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1389 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1390 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1391 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1392 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1393 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1394 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1395 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1396 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1397 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1398 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1399 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1400 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1401 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1402 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1403 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1404 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1405 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1406 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1407 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1408 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1409 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1410 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1411 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1412 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1413 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1414 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1415 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1416 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1417 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1418 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1419 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1420 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1421 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1422 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1423 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1424 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1425 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1426 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1427 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1428 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1429 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1430 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1431 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1432 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1433 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1434 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1435 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1436 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1437 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1438 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1439 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1440 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1441 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1442 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1443 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1444 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1445 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1446 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1447 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1448 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1449 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1450 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1451 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1452 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1453 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1454 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1455 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1456 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1457 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1458 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1459 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1460 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1461 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1462 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1463 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1464 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1465 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1466 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1467 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1468 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1469 DEBUGFS_REG32(DC_WIN_POSITION), 1470 DEBUGFS_REG32(DC_WIN_SIZE), 1471 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1472 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1473 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1474 DEBUGFS_REG32(DC_WIN_DDA_INC), 1475 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1476 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1477 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1478 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1479 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1480 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1481 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1482 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1483 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1484 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1485 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1486 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1487 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1488 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1489 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1490 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1491 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1492 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1493 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1494 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1495 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1496 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1497 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1498 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1499 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1500 }; 1501 1502 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1503 { 1504 struct drm_info_node *node = s->private; 1505 struct tegra_dc *dc = node->info_ent->data; 1506 unsigned int i; 1507 int err = 0; 1508 1509 drm_modeset_lock(&dc->base.mutex, NULL); 1510 1511 if (!dc->base.state->active) { 1512 err = -EBUSY; 1513 goto unlock; 1514 } 1515 1516 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1517 unsigned int offset = tegra_dc_regs[i].offset; 1518 1519 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1520 offset, tegra_dc_readl(dc, offset)); 1521 } 1522 1523 unlock: 1524 drm_modeset_unlock(&dc->base.mutex); 1525 return err; 1526 } 1527 1528 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1529 { 1530 struct drm_info_node *node = s->private; 1531 struct tegra_dc *dc = node->info_ent->data; 1532 int err = 0; 1533 u32 value; 1534 1535 drm_modeset_lock(&dc->base.mutex, NULL); 1536 1537 if (!dc->base.state->active) { 1538 err = -EBUSY; 1539 goto unlock; 1540 } 1541 1542 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1543 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1544 tegra_dc_commit(dc); 1545 1546 drm_crtc_wait_one_vblank(&dc->base); 1547 drm_crtc_wait_one_vblank(&dc->base); 1548 1549 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1550 seq_printf(s, "%08x\n", value); 1551 1552 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1553 1554 unlock: 1555 drm_modeset_unlock(&dc->base.mutex); 1556 return err; 1557 } 1558 1559 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1560 { 1561 struct drm_info_node *node = s->private; 1562 struct tegra_dc *dc = node->info_ent->data; 1563 1564 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1565 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1566 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1567 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1568 1569 return 0; 1570 } 1571 1572 static struct drm_info_list debugfs_files[] = { 1573 { "regs", tegra_dc_show_regs, 0, NULL }, 1574 { "crc", tegra_dc_show_crc, 0, NULL }, 1575 { "stats", tegra_dc_show_stats, 0, NULL }, 1576 }; 1577 1578 static int tegra_dc_late_register(struct drm_crtc *crtc) 1579 { 1580 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1581 struct drm_minor *minor = crtc->dev->primary; 1582 struct dentry *root; 1583 struct tegra_dc *dc = to_tegra_dc(crtc); 1584 1585 #ifdef CONFIG_DEBUG_FS 1586 root = crtc->debugfs_entry; 1587 #else 1588 root = NULL; 1589 #endif 1590 1591 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1592 GFP_KERNEL); 1593 if (!dc->debugfs_files) 1594 return -ENOMEM; 1595 1596 for (i = 0; i < count; i++) 1597 dc->debugfs_files[i].data = dc; 1598 1599 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1600 1601 return 0; 1602 } 1603 1604 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1605 { 1606 unsigned int count = ARRAY_SIZE(debugfs_files); 1607 struct drm_minor *minor = crtc->dev->primary; 1608 struct tegra_dc *dc = to_tegra_dc(crtc); 1609 1610 drm_debugfs_remove_files(dc->debugfs_files, count, minor); 1611 kfree(dc->debugfs_files); 1612 dc->debugfs_files = NULL; 1613 } 1614 1615 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1616 { 1617 struct tegra_dc *dc = to_tegra_dc(crtc); 1618 1619 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1620 if (dc->syncpt && !dc->soc->has_nvdisplay) 1621 return host1x_syncpt_read(dc->syncpt); 1622 1623 /* fallback to software emulated VBLANK counter */ 1624 return (u32)drm_crtc_vblank_count(&dc->base); 1625 } 1626 1627 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1628 { 1629 struct tegra_dc *dc = to_tegra_dc(crtc); 1630 u32 value; 1631 1632 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1633 value |= VBLANK_INT; 1634 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1635 1636 return 0; 1637 } 1638 1639 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1640 { 1641 struct tegra_dc *dc = to_tegra_dc(crtc); 1642 u32 value; 1643 1644 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1645 value &= ~VBLANK_INT; 1646 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1647 } 1648 1649 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1650 .page_flip = drm_atomic_helper_page_flip, 1651 .set_config = drm_atomic_helper_set_config, 1652 .destroy = tegra_dc_destroy, 1653 .reset = tegra_crtc_reset, 1654 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1655 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1656 .late_register = tegra_dc_late_register, 1657 .early_unregister = tegra_dc_early_unregister, 1658 .get_vblank_counter = tegra_dc_get_vblank_counter, 1659 .enable_vblank = tegra_dc_enable_vblank, 1660 .disable_vblank = tegra_dc_disable_vblank, 1661 }; 1662 1663 static int tegra_dc_set_timings(struct tegra_dc *dc, 1664 struct drm_display_mode *mode) 1665 { 1666 unsigned int h_ref_to_sync = 1; 1667 unsigned int v_ref_to_sync = 1; 1668 unsigned long value; 1669 1670 if (!dc->soc->has_nvdisplay) { 1671 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1672 1673 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1674 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1675 } 1676 1677 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1678 ((mode->hsync_end - mode->hsync_start) << 0); 1679 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1680 1681 value = ((mode->vtotal - mode->vsync_end) << 16) | 1682 ((mode->htotal - mode->hsync_end) << 0); 1683 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1684 1685 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1686 ((mode->hsync_start - mode->hdisplay) << 0); 1687 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1688 1689 value = (mode->vdisplay << 16) | mode->hdisplay; 1690 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1691 1692 return 0; 1693 } 1694 1695 /** 1696 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1697 * state 1698 * @dc: display controller 1699 * @crtc_state: CRTC atomic state 1700 * @clk: parent clock for display controller 1701 * @pclk: pixel clock 1702 * @div: shift clock divider 1703 * 1704 * Returns: 1705 * 0 on success or a negative error-code on failure. 1706 */ 1707 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1708 struct drm_crtc_state *crtc_state, 1709 struct clk *clk, unsigned long pclk, 1710 unsigned int div) 1711 { 1712 struct tegra_dc_state *state = to_dc_state(crtc_state); 1713 1714 if (!clk_has_parent(dc->clk, clk)) 1715 return -EINVAL; 1716 1717 state->clk = clk; 1718 state->pclk = pclk; 1719 state->div = div; 1720 1721 return 0; 1722 } 1723 1724 static void tegra_dc_commit_state(struct tegra_dc *dc, 1725 struct tegra_dc_state *state) 1726 { 1727 u32 value; 1728 int err; 1729 1730 err = clk_set_parent(dc->clk, state->clk); 1731 if (err < 0) 1732 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 1733 1734 /* 1735 * Outputs may not want to change the parent clock rate. This is only 1736 * relevant to Tegra20 where only a single display PLL is available. 1737 * Since that PLL would typically be used for HDMI, an internal LVDS 1738 * panel would need to be driven by some other clock such as PLL_P 1739 * which is shared with other peripherals. Changing the clock rate 1740 * should therefore be avoided. 1741 */ 1742 if (state->pclk > 0) { 1743 err = clk_set_rate(state->clk, state->pclk); 1744 if (err < 0) 1745 dev_err(dc->dev, 1746 "failed to set clock rate to %lu Hz\n", 1747 state->pclk); 1748 1749 err = clk_set_rate(dc->clk, state->pclk); 1750 if (err < 0) 1751 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 1752 dc->clk, state->pclk, err); 1753 } 1754 1755 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 1756 state->div); 1757 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1758 1759 if (!dc->soc->has_nvdisplay) { 1760 value = SHIFT_CLK_DIVIDER(state->div) | PIXEL_CLK_DIVIDER_PCD1; 1761 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 1762 } 1763 } 1764 1765 static void tegra_dc_stop(struct tegra_dc *dc) 1766 { 1767 u32 value; 1768 1769 /* stop the display controller */ 1770 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1771 value &= ~DISP_CTRL_MODE_MASK; 1772 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1773 1774 tegra_dc_commit(dc); 1775 } 1776 1777 static bool tegra_dc_idle(struct tegra_dc *dc) 1778 { 1779 u32 value; 1780 1781 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 1782 1783 return (value & DISP_CTRL_MODE_MASK) == 0; 1784 } 1785 1786 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 1787 { 1788 timeout = jiffies + msecs_to_jiffies(timeout); 1789 1790 while (time_before(jiffies, timeout)) { 1791 if (tegra_dc_idle(dc)) 1792 return 0; 1793 1794 usleep_range(1000, 2000); 1795 } 1796 1797 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 1798 return -ETIMEDOUT; 1799 } 1800 1801 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 1802 struct drm_atomic_state *state) 1803 { 1804 struct tegra_dc *dc = to_tegra_dc(crtc); 1805 u32 value; 1806 int err; 1807 1808 if (!tegra_dc_idle(dc)) { 1809 tegra_dc_stop(dc); 1810 1811 /* 1812 * Ignore the return value, there isn't anything useful to do 1813 * in case this fails. 1814 */ 1815 tegra_dc_wait_idle(dc, 100); 1816 } 1817 1818 /* 1819 * This should really be part of the RGB encoder driver, but clearing 1820 * these bits has the side-effect of stopping the display controller. 1821 * When that happens no VBLANK interrupts will be raised. At the same 1822 * time the encoder is disabled before the display controller, so the 1823 * above code is always going to timeout waiting for the controller 1824 * to go idle. 1825 * 1826 * Given the close coupling between the RGB encoder and the display 1827 * controller doing it here is still kind of okay. None of the other 1828 * encoder drivers require these bits to be cleared. 1829 * 1830 * XXX: Perhaps given that the display controller is switched off at 1831 * this point anyway maybe clearing these bits isn't even useful for 1832 * the RGB encoder? 1833 */ 1834 if (dc->rgb) { 1835 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1836 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1837 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 1838 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1839 } 1840 1841 tegra_dc_stats_reset(&dc->stats); 1842 drm_crtc_vblank_off(crtc); 1843 1844 spin_lock_irq(&crtc->dev->event_lock); 1845 1846 if (crtc->state->event) { 1847 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1848 crtc->state->event = NULL; 1849 } 1850 1851 spin_unlock_irq(&crtc->dev->event_lock); 1852 1853 err = host1x_client_suspend(&dc->client); 1854 if (err < 0) 1855 dev_err(dc->dev, "failed to suspend: %d\n", err); 1856 } 1857 1858 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 1859 struct drm_atomic_state *state) 1860 { 1861 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 1862 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); 1863 struct tegra_dc *dc = to_tegra_dc(crtc); 1864 u32 value; 1865 int err; 1866 1867 err = host1x_client_resume(&dc->client); 1868 if (err < 0) { 1869 dev_err(dc->dev, "failed to resume: %d\n", err); 1870 return; 1871 } 1872 1873 /* initialize display controller */ 1874 if (dc->syncpt) { 1875 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 1876 1877 if (dc->soc->has_nvdisplay) 1878 enable = 1 << 31; 1879 else 1880 enable = 1 << 8; 1881 1882 value = SYNCPT_CNTRL_NO_STALL; 1883 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 1884 1885 value = enable | syncpt; 1886 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 1887 } 1888 1889 if (dc->soc->has_nvdisplay) { 1890 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 1891 DSC_OBUF_UF_INT; 1892 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1893 1894 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 1895 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 1896 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 1897 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 1898 VBLANK_INT | FRAME_END_INT; 1899 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1900 1901 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 1902 FRAME_END_INT; 1903 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1904 1905 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 1906 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1907 1908 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 1909 } else { 1910 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1911 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1912 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 1913 1914 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1915 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1916 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 1917 1918 /* initialize timer */ 1919 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 1920 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 1921 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 1922 1923 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 1924 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 1925 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 1926 1927 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1928 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1929 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 1930 1931 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 1932 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 1933 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1934 } 1935 1936 if (dc->soc->supports_background_color) 1937 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 1938 else 1939 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 1940 1941 /* apply PLL and pixel clock changes */ 1942 tegra_dc_commit_state(dc, crtc_state); 1943 1944 /* program display mode */ 1945 tegra_dc_set_timings(dc, mode); 1946 1947 /* interlacing isn't supported yet, so disable it */ 1948 if (dc->soc->supports_interlacing) { 1949 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 1950 value &= ~INTERLACE_ENABLE; 1951 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 1952 } 1953 1954 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1955 value &= ~DISP_CTRL_MODE_MASK; 1956 value |= DISP_CTRL_MODE_C_DISPLAY; 1957 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1958 1959 if (!dc->soc->has_nvdisplay) { 1960 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 1961 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 1962 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 1963 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 1964 } 1965 1966 /* enable underflow reporting and display red for missing pixels */ 1967 if (dc->soc->has_nvdisplay) { 1968 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 1969 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 1970 } 1971 1972 tegra_dc_commit(dc); 1973 1974 drm_crtc_vblank_on(crtc); 1975 } 1976 1977 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 1978 struct drm_atomic_state *state) 1979 { 1980 unsigned long flags; 1981 1982 if (crtc->state->event) { 1983 spin_lock_irqsave(&crtc->dev->event_lock, flags); 1984 1985 if (drm_crtc_vblank_get(crtc) != 0) 1986 drm_crtc_send_vblank_event(crtc, crtc->state->event); 1987 else 1988 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 1989 1990 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 1991 1992 crtc->state->event = NULL; 1993 } 1994 } 1995 1996 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 1997 struct drm_atomic_state *state) 1998 { 1999 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 2000 crtc); 2001 struct tegra_dc_state *dc_state = to_dc_state(crtc_state); 2002 struct tegra_dc *dc = to_tegra_dc(crtc); 2003 u32 value; 2004 2005 value = dc_state->planes << 8 | GENERAL_UPDATE; 2006 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2007 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2008 2009 value = dc_state->planes | GENERAL_ACT_REQ; 2010 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2011 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2012 } 2013 2014 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 2015 .atomic_begin = tegra_crtc_atomic_begin, 2016 .atomic_flush = tegra_crtc_atomic_flush, 2017 .atomic_enable = tegra_crtc_atomic_enable, 2018 .atomic_disable = tegra_crtc_atomic_disable, 2019 }; 2020 2021 static irqreturn_t tegra_dc_irq(int irq, void *data) 2022 { 2023 struct tegra_dc *dc = data; 2024 unsigned long status; 2025 2026 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 2027 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 2028 2029 if (status & FRAME_END_INT) { 2030 /* 2031 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 2032 */ 2033 dc->stats.frames++; 2034 } 2035 2036 if (status & VBLANK_INT) { 2037 /* 2038 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 2039 */ 2040 drm_crtc_handle_vblank(&dc->base); 2041 dc->stats.vblank++; 2042 } 2043 2044 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 2045 /* 2046 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 2047 */ 2048 dc->stats.underflow++; 2049 } 2050 2051 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 2052 /* 2053 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 2054 */ 2055 dc->stats.overflow++; 2056 } 2057 2058 if (status & HEAD_UF_INT) { 2059 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 2060 dc->stats.underflow++; 2061 } 2062 2063 return IRQ_HANDLED; 2064 } 2065 2066 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) 2067 { 2068 unsigned int i; 2069 2070 if (!dc->soc->wgrps) 2071 return true; 2072 2073 for (i = 0; i < dc->soc->num_wgrps; i++) { 2074 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 2075 2076 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) 2077 return true; 2078 } 2079 2080 return false; 2081 } 2082 2083 static int tegra_dc_early_init(struct host1x_client *client) 2084 { 2085 struct drm_device *drm = dev_get_drvdata(client->host); 2086 struct tegra_drm *tegra = drm->dev_private; 2087 2088 tegra->num_crtcs++; 2089 2090 return 0; 2091 } 2092 2093 static int tegra_dc_init(struct host1x_client *client) 2094 { 2095 struct drm_device *drm = dev_get_drvdata(client->host); 2096 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 2097 struct tegra_dc *dc = host1x_client_to_dc(client); 2098 struct tegra_drm *tegra = drm->dev_private; 2099 struct drm_plane *primary = NULL; 2100 struct drm_plane *cursor = NULL; 2101 int err; 2102 2103 /* 2104 * DC has been reset by now, so VBLANK syncpoint can be released 2105 * for general use. 2106 */ 2107 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); 2108 2109 /* 2110 * XXX do not register DCs with no window groups because we cannot 2111 * assign a primary plane to them, which in turn will cause KMS to 2112 * crash. 2113 */ 2114 if (!tegra_dc_has_window_groups(dc)) 2115 return 0; 2116 2117 /* 2118 * Set the display hub as the host1x client parent for the display 2119 * controller. This is needed for the runtime reference counting that 2120 * ensures the display hub is always powered when any of the display 2121 * controllers are. 2122 */ 2123 if (dc->soc->has_nvdisplay) 2124 client->parent = &tegra->hub->client; 2125 2126 dc->syncpt = host1x_syncpt_request(client, flags); 2127 if (!dc->syncpt) 2128 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 2129 2130 err = host1x_client_iommu_attach(client); 2131 if (err < 0 && err != -ENODEV) { 2132 dev_err(client->dev, "failed to attach to domain: %d\n", err); 2133 return err; 2134 } 2135 2136 if (dc->soc->wgrps) 2137 primary = tegra_dc_add_shared_planes(drm, dc); 2138 else 2139 primary = tegra_dc_add_planes(drm, dc); 2140 2141 if (IS_ERR(primary)) { 2142 err = PTR_ERR(primary); 2143 goto cleanup; 2144 } 2145 2146 if (dc->soc->supports_cursor) { 2147 cursor = tegra_dc_cursor_plane_create(drm, dc); 2148 if (IS_ERR(cursor)) { 2149 err = PTR_ERR(cursor); 2150 goto cleanup; 2151 } 2152 } else { 2153 /* dedicate one overlay to mouse cursor */ 2154 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 2155 if (IS_ERR(cursor)) { 2156 err = PTR_ERR(cursor); 2157 goto cleanup; 2158 } 2159 } 2160 2161 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 2162 &tegra_crtc_funcs, NULL); 2163 if (err < 0) 2164 goto cleanup; 2165 2166 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 2167 2168 /* 2169 * Keep track of the minimum pitch alignment across all display 2170 * controllers. 2171 */ 2172 if (dc->soc->pitch_align > tegra->pitch_align) 2173 tegra->pitch_align = dc->soc->pitch_align; 2174 2175 /* track maximum resolution */ 2176 if (dc->soc->has_nvdisplay) 2177 drm->mode_config.max_width = drm->mode_config.max_height = 16384; 2178 else 2179 drm->mode_config.max_width = drm->mode_config.max_height = 4096; 2180 2181 err = tegra_dc_rgb_init(drm, dc); 2182 if (err < 0 && err != -ENODEV) { 2183 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 2184 goto cleanup; 2185 } 2186 2187 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 2188 dev_name(dc->dev), dc); 2189 if (err < 0) { 2190 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 2191 err); 2192 goto cleanup; 2193 } 2194 2195 /* 2196 * Inherit the DMA parameters (such as maximum segment size) from the 2197 * parent host1x device. 2198 */ 2199 client->dev->dma_parms = client->host->dma_parms; 2200 2201 return 0; 2202 2203 cleanup: 2204 if (!IS_ERR_OR_NULL(cursor)) 2205 drm_plane_cleanup(cursor); 2206 2207 if (!IS_ERR(primary)) 2208 drm_plane_cleanup(primary); 2209 2210 host1x_client_iommu_detach(client); 2211 host1x_syncpt_put(dc->syncpt); 2212 2213 return err; 2214 } 2215 2216 static int tegra_dc_exit(struct host1x_client *client) 2217 { 2218 struct tegra_dc *dc = host1x_client_to_dc(client); 2219 int err; 2220 2221 if (!tegra_dc_has_window_groups(dc)) 2222 return 0; 2223 2224 /* avoid a dangling pointer just in case this disappears */ 2225 client->dev->dma_parms = NULL; 2226 2227 devm_free_irq(dc->dev, dc->irq, dc); 2228 2229 err = tegra_dc_rgb_exit(dc); 2230 if (err) { 2231 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 2232 return err; 2233 } 2234 2235 host1x_client_iommu_detach(client); 2236 host1x_syncpt_put(dc->syncpt); 2237 2238 return 0; 2239 } 2240 2241 static int tegra_dc_late_exit(struct host1x_client *client) 2242 { 2243 struct drm_device *drm = dev_get_drvdata(client->host); 2244 struct tegra_drm *tegra = drm->dev_private; 2245 2246 tegra->num_crtcs--; 2247 2248 return 0; 2249 } 2250 2251 static int tegra_dc_runtime_suspend(struct host1x_client *client) 2252 { 2253 struct tegra_dc *dc = host1x_client_to_dc(client); 2254 struct device *dev = client->dev; 2255 int err; 2256 2257 err = reset_control_assert(dc->rst); 2258 if (err < 0) { 2259 dev_err(dev, "failed to assert reset: %d\n", err); 2260 return err; 2261 } 2262 2263 if (dc->soc->has_powergate) 2264 tegra_powergate_power_off(dc->powergate); 2265 2266 clk_disable_unprepare(dc->clk); 2267 pm_runtime_put_sync(dev); 2268 2269 return 0; 2270 } 2271 2272 static int tegra_dc_runtime_resume(struct host1x_client *client) 2273 { 2274 struct tegra_dc *dc = host1x_client_to_dc(client); 2275 struct device *dev = client->dev; 2276 int err; 2277 2278 err = pm_runtime_resume_and_get(dev); 2279 if (err < 0) { 2280 dev_err(dev, "failed to get runtime PM: %d\n", err); 2281 return err; 2282 } 2283 2284 if (dc->soc->has_powergate) { 2285 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, 2286 dc->rst); 2287 if (err < 0) { 2288 dev_err(dev, "failed to power partition: %d\n", err); 2289 goto put_rpm; 2290 } 2291 } else { 2292 err = clk_prepare_enable(dc->clk); 2293 if (err < 0) { 2294 dev_err(dev, "failed to enable clock: %d\n", err); 2295 goto put_rpm; 2296 } 2297 2298 err = reset_control_deassert(dc->rst); 2299 if (err < 0) { 2300 dev_err(dev, "failed to deassert reset: %d\n", err); 2301 goto disable_clk; 2302 } 2303 } 2304 2305 return 0; 2306 2307 disable_clk: 2308 clk_disable_unprepare(dc->clk); 2309 put_rpm: 2310 pm_runtime_put_sync(dev); 2311 return err; 2312 } 2313 2314 static const struct host1x_client_ops dc_client_ops = { 2315 .early_init = tegra_dc_early_init, 2316 .init = tegra_dc_init, 2317 .exit = tegra_dc_exit, 2318 .late_exit = tegra_dc_late_exit, 2319 .suspend = tegra_dc_runtime_suspend, 2320 .resume = tegra_dc_runtime_resume, 2321 }; 2322 2323 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 2324 .supports_background_color = false, 2325 .supports_interlacing = false, 2326 .supports_cursor = false, 2327 .supports_block_linear = false, 2328 .supports_sector_layout = false, 2329 .has_legacy_blending = true, 2330 .pitch_align = 8, 2331 .has_powergate = false, 2332 .coupled_pm = true, 2333 .has_nvdisplay = false, 2334 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2335 .primary_formats = tegra20_primary_formats, 2336 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2337 .overlay_formats = tegra20_overlay_formats, 2338 .modifiers = tegra20_modifiers, 2339 .has_win_a_without_filters = true, 2340 .has_win_c_without_vert_filter = true, 2341 }; 2342 2343 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 2344 .supports_background_color = false, 2345 .supports_interlacing = false, 2346 .supports_cursor = false, 2347 .supports_block_linear = false, 2348 .supports_sector_layout = false, 2349 .has_legacy_blending = true, 2350 .pitch_align = 8, 2351 .has_powergate = false, 2352 .coupled_pm = false, 2353 .has_nvdisplay = false, 2354 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2355 .primary_formats = tegra20_primary_formats, 2356 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2357 .overlay_formats = tegra20_overlay_formats, 2358 .modifiers = tegra20_modifiers, 2359 .has_win_a_without_filters = false, 2360 .has_win_c_without_vert_filter = false, 2361 }; 2362 2363 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2364 .supports_background_color = false, 2365 .supports_interlacing = false, 2366 .supports_cursor = false, 2367 .supports_block_linear = false, 2368 .supports_sector_layout = false, 2369 .has_legacy_blending = true, 2370 .pitch_align = 64, 2371 .has_powergate = true, 2372 .coupled_pm = false, 2373 .has_nvdisplay = false, 2374 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2375 .primary_formats = tegra114_primary_formats, 2376 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2377 .overlay_formats = tegra114_overlay_formats, 2378 .modifiers = tegra20_modifiers, 2379 .has_win_a_without_filters = false, 2380 .has_win_c_without_vert_filter = false, 2381 }; 2382 2383 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 2384 .supports_background_color = true, 2385 .supports_interlacing = true, 2386 .supports_cursor = true, 2387 .supports_block_linear = true, 2388 .supports_sector_layout = false, 2389 .has_legacy_blending = false, 2390 .pitch_align = 64, 2391 .has_powergate = true, 2392 .coupled_pm = false, 2393 .has_nvdisplay = false, 2394 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 2395 .primary_formats = tegra124_primary_formats, 2396 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 2397 .overlay_formats = tegra124_overlay_formats, 2398 .modifiers = tegra124_modifiers, 2399 .has_win_a_without_filters = false, 2400 .has_win_c_without_vert_filter = false, 2401 }; 2402 2403 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2404 .supports_background_color = true, 2405 .supports_interlacing = true, 2406 .supports_cursor = true, 2407 .supports_block_linear = true, 2408 .supports_sector_layout = false, 2409 .has_legacy_blending = false, 2410 .pitch_align = 64, 2411 .has_powergate = true, 2412 .coupled_pm = false, 2413 .has_nvdisplay = false, 2414 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2415 .primary_formats = tegra114_primary_formats, 2416 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2417 .overlay_formats = tegra114_overlay_formats, 2418 .modifiers = tegra124_modifiers, 2419 .has_win_a_without_filters = false, 2420 .has_win_c_without_vert_filter = false, 2421 }; 2422 2423 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 2424 { 2425 .index = 0, 2426 .dc = 0, 2427 .windows = (const unsigned int[]) { 0 }, 2428 .num_windows = 1, 2429 }, { 2430 .index = 1, 2431 .dc = 1, 2432 .windows = (const unsigned int[]) { 1 }, 2433 .num_windows = 1, 2434 }, { 2435 .index = 2, 2436 .dc = 1, 2437 .windows = (const unsigned int[]) { 2 }, 2438 .num_windows = 1, 2439 }, { 2440 .index = 3, 2441 .dc = 2, 2442 .windows = (const unsigned int[]) { 3 }, 2443 .num_windows = 1, 2444 }, { 2445 .index = 4, 2446 .dc = 2, 2447 .windows = (const unsigned int[]) { 4 }, 2448 .num_windows = 1, 2449 }, { 2450 .index = 5, 2451 .dc = 2, 2452 .windows = (const unsigned int[]) { 5 }, 2453 .num_windows = 1, 2454 }, 2455 }; 2456 2457 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 2458 .supports_background_color = true, 2459 .supports_interlacing = true, 2460 .supports_cursor = true, 2461 .supports_block_linear = true, 2462 .supports_sector_layout = false, 2463 .has_legacy_blending = false, 2464 .pitch_align = 64, 2465 .has_powergate = false, 2466 .coupled_pm = false, 2467 .has_nvdisplay = true, 2468 .wgrps = tegra186_dc_wgrps, 2469 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2470 }; 2471 2472 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { 2473 { 2474 .index = 0, 2475 .dc = 0, 2476 .windows = (const unsigned int[]) { 0 }, 2477 .num_windows = 1, 2478 }, { 2479 .index = 1, 2480 .dc = 1, 2481 .windows = (const unsigned int[]) { 1 }, 2482 .num_windows = 1, 2483 }, { 2484 .index = 2, 2485 .dc = 1, 2486 .windows = (const unsigned int[]) { 2 }, 2487 .num_windows = 1, 2488 }, { 2489 .index = 3, 2490 .dc = 2, 2491 .windows = (const unsigned int[]) { 3 }, 2492 .num_windows = 1, 2493 }, { 2494 .index = 4, 2495 .dc = 2, 2496 .windows = (const unsigned int[]) { 4 }, 2497 .num_windows = 1, 2498 }, { 2499 .index = 5, 2500 .dc = 2, 2501 .windows = (const unsigned int[]) { 5 }, 2502 .num_windows = 1, 2503 }, 2504 }; 2505 2506 static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 2507 .supports_background_color = true, 2508 .supports_interlacing = true, 2509 .supports_cursor = true, 2510 .supports_block_linear = true, 2511 .supports_sector_layout = true, 2512 .has_legacy_blending = false, 2513 .pitch_align = 64, 2514 .has_powergate = false, 2515 .coupled_pm = false, 2516 .has_nvdisplay = true, 2517 .wgrps = tegra194_dc_wgrps, 2518 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), 2519 }; 2520 2521 static const struct of_device_id tegra_dc_of_match[] = { 2522 { 2523 .compatible = "nvidia,tegra194-dc", 2524 .data = &tegra194_dc_soc_info, 2525 }, { 2526 .compatible = "nvidia,tegra186-dc", 2527 .data = &tegra186_dc_soc_info, 2528 }, { 2529 .compatible = "nvidia,tegra210-dc", 2530 .data = &tegra210_dc_soc_info, 2531 }, { 2532 .compatible = "nvidia,tegra124-dc", 2533 .data = &tegra124_dc_soc_info, 2534 }, { 2535 .compatible = "nvidia,tegra114-dc", 2536 .data = &tegra114_dc_soc_info, 2537 }, { 2538 .compatible = "nvidia,tegra30-dc", 2539 .data = &tegra30_dc_soc_info, 2540 }, { 2541 .compatible = "nvidia,tegra20-dc", 2542 .data = &tegra20_dc_soc_info, 2543 }, { 2544 /* sentinel */ 2545 } 2546 }; 2547 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 2548 2549 static int tegra_dc_parse_dt(struct tegra_dc *dc) 2550 { 2551 struct device_node *np; 2552 u32 value = 0; 2553 int err; 2554 2555 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 2556 if (err < 0) { 2557 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 2558 2559 /* 2560 * If the nvidia,head property isn't present, try to find the 2561 * correct head number by looking up the position of this 2562 * display controller's node within the device tree. Assuming 2563 * that the nodes are ordered properly in the DTS file and 2564 * that the translation into a flattened device tree blob 2565 * preserves that ordering this will actually yield the right 2566 * head number. 2567 * 2568 * If those assumptions don't hold, this will still work for 2569 * cases where only a single display controller is used. 2570 */ 2571 for_each_matching_node(np, tegra_dc_of_match) { 2572 if (np == dc->dev->of_node) { 2573 of_node_put(np); 2574 break; 2575 } 2576 2577 value++; 2578 } 2579 } 2580 2581 dc->pipe = value; 2582 2583 return 0; 2584 } 2585 2586 static int tegra_dc_match_by_pipe(struct device *dev, const void *data) 2587 { 2588 struct tegra_dc *dc = dev_get_drvdata(dev); 2589 unsigned int pipe = (unsigned long)(void *)data; 2590 2591 return dc->pipe == pipe; 2592 } 2593 2594 static int tegra_dc_couple(struct tegra_dc *dc) 2595 { 2596 /* 2597 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 2598 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 2599 * POWER_CONTROL registers during CRTC enabling. 2600 */ 2601 if (dc->soc->coupled_pm && dc->pipe == 1) { 2602 struct device *companion; 2603 struct tegra_dc *parent; 2604 2605 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, 2606 tegra_dc_match_by_pipe); 2607 if (!companion) 2608 return -EPROBE_DEFER; 2609 2610 parent = dev_get_drvdata(companion); 2611 dc->client.parent = &parent->client; 2612 2613 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); 2614 } 2615 2616 return 0; 2617 } 2618 2619 static int tegra_dc_probe(struct platform_device *pdev) 2620 { 2621 u64 dma_mask = dma_get_mask(pdev->dev.parent); 2622 struct tegra_dc *dc; 2623 int err; 2624 2625 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); 2626 if (err < 0) { 2627 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 2628 return err; 2629 } 2630 2631 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 2632 if (!dc) 2633 return -ENOMEM; 2634 2635 dc->soc = of_device_get_match_data(&pdev->dev); 2636 2637 INIT_LIST_HEAD(&dc->list); 2638 dc->dev = &pdev->dev; 2639 2640 err = tegra_dc_parse_dt(dc); 2641 if (err < 0) 2642 return err; 2643 2644 err = tegra_dc_couple(dc); 2645 if (err < 0) 2646 return err; 2647 2648 dc->clk = devm_clk_get(&pdev->dev, NULL); 2649 if (IS_ERR(dc->clk)) { 2650 dev_err(&pdev->dev, "failed to get clock\n"); 2651 return PTR_ERR(dc->clk); 2652 } 2653 2654 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 2655 if (IS_ERR(dc->rst)) { 2656 dev_err(&pdev->dev, "failed to get reset\n"); 2657 return PTR_ERR(dc->rst); 2658 } 2659 2660 /* assert reset and disable clock */ 2661 err = clk_prepare_enable(dc->clk); 2662 if (err < 0) 2663 return err; 2664 2665 usleep_range(2000, 4000); 2666 2667 err = reset_control_assert(dc->rst); 2668 if (err < 0) 2669 return err; 2670 2671 usleep_range(2000, 4000); 2672 2673 clk_disable_unprepare(dc->clk); 2674 2675 if (dc->soc->has_powergate) { 2676 if (dc->pipe == 0) 2677 dc->powergate = TEGRA_POWERGATE_DIS; 2678 else 2679 dc->powergate = TEGRA_POWERGATE_DISB; 2680 2681 tegra_powergate_power_off(dc->powergate); 2682 } 2683 2684 dc->regs = devm_platform_ioremap_resource(pdev, 0); 2685 if (IS_ERR(dc->regs)) 2686 return PTR_ERR(dc->regs); 2687 2688 dc->irq = platform_get_irq(pdev, 0); 2689 if (dc->irq < 0) 2690 return -ENXIO; 2691 2692 err = tegra_dc_rgb_probe(dc); 2693 if (err < 0 && err != -ENODEV) { 2694 const char *level = KERN_ERR; 2695 2696 if (err == -EPROBE_DEFER) 2697 level = KERN_DEBUG; 2698 2699 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", 2700 err); 2701 return err; 2702 } 2703 2704 platform_set_drvdata(pdev, dc); 2705 pm_runtime_enable(&pdev->dev); 2706 2707 INIT_LIST_HEAD(&dc->client.list); 2708 dc->client.ops = &dc_client_ops; 2709 dc->client.dev = &pdev->dev; 2710 2711 err = host1x_client_register(&dc->client); 2712 if (err < 0) { 2713 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 2714 err); 2715 goto disable_pm; 2716 } 2717 2718 return 0; 2719 2720 disable_pm: 2721 pm_runtime_disable(&pdev->dev); 2722 tegra_dc_rgb_remove(dc); 2723 2724 return err; 2725 } 2726 2727 static int tegra_dc_remove(struct platform_device *pdev) 2728 { 2729 struct tegra_dc *dc = platform_get_drvdata(pdev); 2730 int err; 2731 2732 err = host1x_client_unregister(&dc->client); 2733 if (err < 0) { 2734 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 2735 err); 2736 return err; 2737 } 2738 2739 err = tegra_dc_rgb_remove(dc); 2740 if (err < 0) { 2741 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 2742 return err; 2743 } 2744 2745 pm_runtime_disable(&pdev->dev); 2746 2747 return 0; 2748 } 2749 2750 struct platform_driver tegra_dc_driver = { 2751 .driver = { 2752 .name = "tegra-dc", 2753 .of_match_table = tegra_dc_of_match, 2754 }, 2755 .probe = tegra_dc_probe, 2756 .remove = tegra_dc_remove, 2757 }; 2758