1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2012 Avionic Design GmbH 4 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved. 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/debugfs.h> 9 #include <linux/delay.h> 10 #include <linux/iommu.h> 11 #include <linux/interconnect.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/pm_domain.h> 15 #include <linux/pm_opp.h> 16 #include <linux/pm_runtime.h> 17 #include <linux/reset.h> 18 19 #include <soc/tegra/common.h> 20 #include <soc/tegra/pmc.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_debugfs.h> 25 #include <drm/drm_fourcc.h> 26 #include <drm/drm_plane_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "dc.h" 30 #include "drm.h" 31 #include "gem.h" 32 #include "hub.h" 33 #include "plane.h" 34 35 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 36 struct drm_crtc_state *state); 37 38 static void tegra_dc_stats_reset(struct tegra_dc_stats *stats) 39 { 40 stats->frames = 0; 41 stats->vblank = 0; 42 stats->underflow = 0; 43 stats->overflow = 0; 44 } 45 46 /* Reads the active copy of a register. */ 47 static u32 tegra_dc_readl_active(struct tegra_dc *dc, unsigned long offset) 48 { 49 u32 value; 50 51 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 52 value = tegra_dc_readl(dc, offset); 53 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS); 54 55 return value; 56 } 57 58 static inline unsigned int tegra_plane_offset(struct tegra_plane *plane, 59 unsigned int offset) 60 { 61 if (offset >= 0x500 && offset <= 0x638) { 62 offset = 0x000 + (offset - 0x500); 63 return plane->offset + offset; 64 } 65 66 if (offset >= 0x700 && offset <= 0x719) { 67 offset = 0x180 + (offset - 0x700); 68 return plane->offset + offset; 69 } 70 71 if (offset >= 0x800 && offset <= 0x839) { 72 offset = 0x1c0 + (offset - 0x800); 73 return plane->offset + offset; 74 } 75 76 dev_WARN(plane->dc->dev, "invalid offset: %x\n", offset); 77 78 return plane->offset + offset; 79 } 80 81 static inline u32 tegra_plane_readl(struct tegra_plane *plane, 82 unsigned int offset) 83 { 84 return tegra_dc_readl(plane->dc, tegra_plane_offset(plane, offset)); 85 } 86 87 static inline void tegra_plane_writel(struct tegra_plane *plane, u32 value, 88 unsigned int offset) 89 { 90 tegra_dc_writel(plane->dc, value, tegra_plane_offset(plane, offset)); 91 } 92 93 bool tegra_dc_has_output(struct tegra_dc *dc, struct device *dev) 94 { 95 struct device_node *np = dc->dev->of_node; 96 struct of_phandle_iterator it; 97 int err; 98 99 of_for_each_phandle(&it, err, np, "nvidia,outputs", NULL, 0) 100 if (it.node == dev->of_node) 101 return true; 102 103 return false; 104 } 105 106 /* 107 * Double-buffered registers have two copies: ASSEMBLY and ACTIVE. When the 108 * *_ACT_REQ bits are set the ASSEMBLY copy is latched into the ACTIVE copy. 109 * Latching happens mmediately if the display controller is in STOP mode or 110 * on the next frame boundary otherwise. 111 * 112 * Triple-buffered registers have three copies: ASSEMBLY, ARM and ACTIVE. The 113 * ASSEMBLY copy is latched into the ARM copy immediately after *_UPDATE bits 114 * are written. When the *_ACT_REQ bits are written, the ARM copy is latched 115 * into the ACTIVE copy, either immediately if the display controller is in 116 * STOP mode, or at the next frame boundary otherwise. 117 */ 118 void tegra_dc_commit(struct tegra_dc *dc) 119 { 120 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL); 121 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL); 122 } 123 124 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v, 125 unsigned int bpp) 126 { 127 fixed20_12 outf = dfixed_init(out); 128 fixed20_12 inf = dfixed_init(in); 129 u32 dda_inc; 130 int max; 131 132 if (v) 133 max = 15; 134 else { 135 switch (bpp) { 136 case 2: 137 max = 8; 138 break; 139 140 default: 141 WARN_ON_ONCE(1); 142 fallthrough; 143 case 4: 144 max = 4; 145 break; 146 } 147 } 148 149 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1)); 150 inf.full -= dfixed_const(1); 151 152 dda_inc = dfixed_div(inf, outf); 153 dda_inc = min_t(u32, dda_inc, dfixed_const(max)); 154 155 return dda_inc; 156 } 157 158 static inline u32 compute_initial_dda(unsigned int in) 159 { 160 fixed20_12 inf = dfixed_init(in); 161 return dfixed_frac(inf); 162 } 163 164 static void tegra_plane_setup_blending_legacy(struct tegra_plane *plane) 165 { 166 u32 background[3] = { 167 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 168 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 169 BLEND_WEIGHT1(0) | BLEND_WEIGHT0(0) | BLEND_COLOR_KEY_NONE, 170 }; 171 u32 foreground = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255) | 172 BLEND_COLOR_KEY_NONE; 173 u32 blendnokey = BLEND_WEIGHT1(255) | BLEND_WEIGHT0(255); 174 struct tegra_plane_state *state; 175 u32 blending[2]; 176 unsigned int i; 177 178 /* disable blending for non-overlapping case */ 179 tegra_plane_writel(plane, blendnokey, DC_WIN_BLEND_NOKEY); 180 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_1WIN); 181 182 state = to_tegra_plane_state(plane->base.state); 183 184 if (state->opaque) { 185 /* 186 * Since custom fix-weight blending isn't utilized and weight 187 * of top window is set to max, we can enforce dependent 188 * blending which in this case results in transparent bottom 189 * window if top window is opaque and if top window enables 190 * alpha blending, then bottom window is getting alpha value 191 * of 1 minus the sum of alpha components of the overlapping 192 * plane. 193 */ 194 background[0] |= BLEND_CONTROL_DEPENDENT; 195 background[1] |= BLEND_CONTROL_DEPENDENT; 196 197 /* 198 * The region where three windows overlap is the intersection 199 * of the two regions where two windows overlap. It contributes 200 * to the area if all of the windows on top of it have an alpha 201 * component. 202 */ 203 switch (state->base.normalized_zpos) { 204 case 0: 205 if (state->blending[0].alpha && 206 state->blending[1].alpha) 207 background[2] |= BLEND_CONTROL_DEPENDENT; 208 break; 209 210 case 1: 211 background[2] |= BLEND_CONTROL_DEPENDENT; 212 break; 213 } 214 } else { 215 /* 216 * Enable alpha blending if pixel format has an alpha 217 * component. 218 */ 219 foreground |= BLEND_CONTROL_ALPHA; 220 221 /* 222 * If any of the windows on top of this window is opaque, it 223 * will completely conceal this window within that area. If 224 * top window has an alpha component, it is blended over the 225 * bottom window. 226 */ 227 for (i = 0; i < 2; i++) { 228 if (state->blending[i].alpha && 229 state->blending[i].top) 230 background[i] |= BLEND_CONTROL_DEPENDENT; 231 } 232 233 switch (state->base.normalized_zpos) { 234 case 0: 235 if (state->blending[0].alpha && 236 state->blending[1].alpha) 237 background[2] |= BLEND_CONTROL_DEPENDENT; 238 break; 239 240 case 1: 241 /* 242 * When both middle and topmost windows have an alpha, 243 * these windows a mixed together and then the result 244 * is blended over the bottom window. 245 */ 246 if (state->blending[0].alpha && 247 state->blending[0].top) 248 background[2] |= BLEND_CONTROL_ALPHA; 249 250 if (state->blending[1].alpha && 251 state->blending[1].top) 252 background[2] |= BLEND_CONTROL_ALPHA; 253 break; 254 } 255 } 256 257 switch (state->base.normalized_zpos) { 258 case 0: 259 tegra_plane_writel(plane, background[0], DC_WIN_BLEND_2WIN_X); 260 tegra_plane_writel(plane, background[1], DC_WIN_BLEND_2WIN_Y); 261 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 262 break; 263 264 case 1: 265 /* 266 * If window B / C is topmost, then X / Y registers are 267 * matching the order of blending[...] state indices, 268 * otherwise a swap is required. 269 */ 270 if (!state->blending[0].top && state->blending[1].top) { 271 blending[0] = foreground; 272 blending[1] = background[1]; 273 } else { 274 blending[0] = background[0]; 275 blending[1] = foreground; 276 } 277 278 tegra_plane_writel(plane, blending[0], DC_WIN_BLEND_2WIN_X); 279 tegra_plane_writel(plane, blending[1], DC_WIN_BLEND_2WIN_Y); 280 tegra_plane_writel(plane, background[2], DC_WIN_BLEND_3WIN_XY); 281 break; 282 283 case 2: 284 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_X); 285 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_2WIN_Y); 286 tegra_plane_writel(plane, foreground, DC_WIN_BLEND_3WIN_XY); 287 break; 288 } 289 } 290 291 static void tegra_plane_setup_blending(struct tegra_plane *plane, 292 const struct tegra_dc_window *window) 293 { 294 u32 value; 295 296 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 297 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 298 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 299 tegra_plane_writel(plane, value, DC_WIN_BLEND_MATCH_SELECT); 300 301 value = BLEND_FACTOR_DST_ALPHA_ZERO | BLEND_FACTOR_SRC_ALPHA_K2 | 302 BLEND_FACTOR_DST_COLOR_NEG_K1_TIMES_SRC | 303 BLEND_FACTOR_SRC_COLOR_K1_TIMES_SRC; 304 tegra_plane_writel(plane, value, DC_WIN_BLEND_NOMATCH_SELECT); 305 306 value = K2(255) | K1(255) | WINDOW_LAYER_DEPTH(255 - window->zpos); 307 tegra_plane_writel(plane, value, DC_WIN_BLEND_LAYER_CONTROL); 308 } 309 310 static bool 311 tegra_plane_use_horizontal_filtering(struct tegra_plane *plane, 312 const struct tegra_dc_window *window) 313 { 314 struct tegra_dc *dc = plane->dc; 315 316 if (window->src.w == window->dst.w) 317 return false; 318 319 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 320 return false; 321 322 return true; 323 } 324 325 static bool 326 tegra_plane_use_vertical_filtering(struct tegra_plane *plane, 327 const struct tegra_dc_window *window) 328 { 329 struct tegra_dc *dc = plane->dc; 330 331 if (window->src.h == window->dst.h) 332 return false; 333 334 if (plane->index == 0 && dc->soc->has_win_a_without_filters) 335 return false; 336 337 if (plane->index == 2 && dc->soc->has_win_c_without_vert_filter) 338 return false; 339 340 return true; 341 } 342 343 static void tegra_dc_setup_window(struct tegra_plane *plane, 344 const struct tegra_dc_window *window) 345 { 346 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp; 347 struct tegra_dc *dc = plane->dc; 348 bool yuv, planar; 349 u32 value; 350 351 /* 352 * For YUV planar modes, the number of bytes per pixel takes into 353 * account only the luma component and therefore is 1. 354 */ 355 yuv = tegra_plane_format_is_yuv(window->format, &planar, NULL); 356 if (!yuv) 357 bpp = window->bits_per_pixel / 8; 358 else 359 bpp = planar ? 1 : 2; 360 361 tegra_plane_writel(plane, window->format, DC_WIN_COLOR_DEPTH); 362 tegra_plane_writel(plane, window->swap, DC_WIN_BYTE_SWAP); 363 364 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x); 365 tegra_plane_writel(plane, value, DC_WIN_POSITION); 366 367 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w); 368 tegra_plane_writel(plane, value, DC_WIN_SIZE); 369 370 h_offset = window->src.x * bpp; 371 v_offset = window->src.y; 372 h_size = window->src.w * bpp; 373 v_size = window->src.h; 374 375 if (window->reflect_x) 376 h_offset += (window->src.w - 1) * bpp; 377 378 if (window->reflect_y) 379 v_offset += window->src.h - 1; 380 381 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size); 382 tegra_plane_writel(plane, value, DC_WIN_PRESCALED_SIZE); 383 384 /* 385 * For DDA computations the number of bytes per pixel for YUV planar 386 * modes needs to take into account all Y, U and V components. 387 */ 388 if (yuv && planar) 389 bpp = 2; 390 391 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp); 392 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp); 393 394 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda); 395 tegra_plane_writel(plane, value, DC_WIN_DDA_INC); 396 397 h_dda = compute_initial_dda(window->src.x); 398 v_dda = compute_initial_dda(window->src.y); 399 400 tegra_plane_writel(plane, h_dda, DC_WIN_H_INITIAL_DDA); 401 tegra_plane_writel(plane, v_dda, DC_WIN_V_INITIAL_DDA); 402 403 tegra_plane_writel(plane, 0, DC_WIN_UV_BUF_STRIDE); 404 tegra_plane_writel(plane, 0, DC_WIN_BUF_STRIDE); 405 406 tegra_plane_writel(plane, window->base[0], DC_WINBUF_START_ADDR); 407 408 if (yuv && planar) { 409 tegra_plane_writel(plane, window->base[1], DC_WINBUF_START_ADDR_U); 410 tegra_plane_writel(plane, window->base[2], DC_WINBUF_START_ADDR_V); 411 value = window->stride[1] << 16 | window->stride[0]; 412 tegra_plane_writel(plane, value, DC_WIN_LINE_STRIDE); 413 } else { 414 tegra_plane_writel(plane, window->stride[0], DC_WIN_LINE_STRIDE); 415 } 416 417 tegra_plane_writel(plane, h_offset, DC_WINBUF_ADDR_H_OFFSET); 418 tegra_plane_writel(plane, v_offset, DC_WINBUF_ADDR_V_OFFSET); 419 420 if (dc->soc->supports_block_linear) { 421 unsigned long height = window->tiling.value; 422 423 switch (window->tiling.mode) { 424 case TEGRA_BO_TILING_MODE_PITCH: 425 value = DC_WINBUF_SURFACE_KIND_PITCH; 426 break; 427 428 case TEGRA_BO_TILING_MODE_TILED: 429 value = DC_WINBUF_SURFACE_KIND_TILED; 430 break; 431 432 case TEGRA_BO_TILING_MODE_BLOCK: 433 value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) | 434 DC_WINBUF_SURFACE_KIND_BLOCK; 435 break; 436 } 437 438 tegra_plane_writel(plane, value, DC_WINBUF_SURFACE_KIND); 439 } else { 440 switch (window->tiling.mode) { 441 case TEGRA_BO_TILING_MODE_PITCH: 442 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV | 443 DC_WIN_BUFFER_ADDR_MODE_LINEAR; 444 break; 445 446 case TEGRA_BO_TILING_MODE_TILED: 447 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV | 448 DC_WIN_BUFFER_ADDR_MODE_TILE; 449 break; 450 451 case TEGRA_BO_TILING_MODE_BLOCK: 452 /* 453 * No need to handle this here because ->atomic_check 454 * will already have filtered it out. 455 */ 456 break; 457 } 458 459 tegra_plane_writel(plane, value, DC_WIN_BUFFER_ADDR_MODE); 460 } 461 462 value = WIN_ENABLE; 463 464 if (yuv) { 465 /* setup default colorspace conversion coefficients */ 466 tegra_plane_writel(plane, 0x00f0, DC_WIN_CSC_YOF); 467 tegra_plane_writel(plane, 0x012a, DC_WIN_CSC_KYRGB); 468 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KUR); 469 tegra_plane_writel(plane, 0x0198, DC_WIN_CSC_KVR); 470 tegra_plane_writel(plane, 0x039b, DC_WIN_CSC_KUG); 471 tegra_plane_writel(plane, 0x032f, DC_WIN_CSC_KVG); 472 tegra_plane_writel(plane, 0x0204, DC_WIN_CSC_KUB); 473 tegra_plane_writel(plane, 0x0000, DC_WIN_CSC_KVB); 474 475 value |= CSC_ENABLE; 476 } else if (window->bits_per_pixel < 24) { 477 value |= COLOR_EXPAND; 478 } 479 480 if (window->reflect_x) 481 value |= H_DIRECTION; 482 483 if (window->reflect_y) 484 value |= V_DIRECTION; 485 486 if (tegra_plane_use_horizontal_filtering(plane, window)) { 487 /* 488 * Enable horizontal 6-tap filter and set filtering 489 * coefficients to the default values defined in TRM. 490 */ 491 tegra_plane_writel(plane, 0x00008000, DC_WIN_H_FILTER_P(0)); 492 tegra_plane_writel(plane, 0x3e087ce1, DC_WIN_H_FILTER_P(1)); 493 tegra_plane_writel(plane, 0x3b117ac1, DC_WIN_H_FILTER_P(2)); 494 tegra_plane_writel(plane, 0x591b73aa, DC_WIN_H_FILTER_P(3)); 495 tegra_plane_writel(plane, 0x57256d9a, DC_WIN_H_FILTER_P(4)); 496 tegra_plane_writel(plane, 0x552f668b, DC_WIN_H_FILTER_P(5)); 497 tegra_plane_writel(plane, 0x73385e8b, DC_WIN_H_FILTER_P(6)); 498 tegra_plane_writel(plane, 0x72435583, DC_WIN_H_FILTER_P(7)); 499 tegra_plane_writel(plane, 0x714c4c8b, DC_WIN_H_FILTER_P(8)); 500 tegra_plane_writel(plane, 0x70554393, DC_WIN_H_FILTER_P(9)); 501 tegra_plane_writel(plane, 0x715e389b, DC_WIN_H_FILTER_P(10)); 502 tegra_plane_writel(plane, 0x71662faa, DC_WIN_H_FILTER_P(11)); 503 tegra_plane_writel(plane, 0x536d25ba, DC_WIN_H_FILTER_P(12)); 504 tegra_plane_writel(plane, 0x55731bca, DC_WIN_H_FILTER_P(13)); 505 tegra_plane_writel(plane, 0x387a11d9, DC_WIN_H_FILTER_P(14)); 506 tegra_plane_writel(plane, 0x3c7c08f1, DC_WIN_H_FILTER_P(15)); 507 508 value |= H_FILTER; 509 } 510 511 if (tegra_plane_use_vertical_filtering(plane, window)) { 512 unsigned int i, k; 513 514 /* 515 * Enable vertical 2-tap filter and set filtering 516 * coefficients to the default values defined in TRM. 517 */ 518 for (i = 0, k = 128; i < 16; i++, k -= 8) 519 tegra_plane_writel(plane, k, DC_WIN_V_FILTER_P(i)); 520 521 value |= V_FILTER; 522 } 523 524 tegra_plane_writel(plane, value, DC_WIN_WIN_OPTIONS); 525 526 if (dc->soc->has_legacy_blending) 527 tegra_plane_setup_blending_legacy(plane); 528 else 529 tegra_plane_setup_blending(plane, window); 530 } 531 532 static const u32 tegra20_primary_formats[] = { 533 DRM_FORMAT_ARGB4444, 534 DRM_FORMAT_ARGB1555, 535 DRM_FORMAT_RGB565, 536 DRM_FORMAT_RGBA5551, 537 DRM_FORMAT_ABGR8888, 538 DRM_FORMAT_ARGB8888, 539 /* non-native formats */ 540 DRM_FORMAT_XRGB1555, 541 DRM_FORMAT_RGBX5551, 542 DRM_FORMAT_XBGR8888, 543 DRM_FORMAT_XRGB8888, 544 }; 545 546 static const u64 tegra20_modifiers[] = { 547 DRM_FORMAT_MOD_LINEAR, 548 DRM_FORMAT_MOD_NVIDIA_TEGRA_TILED, 549 DRM_FORMAT_MOD_INVALID 550 }; 551 552 static const u32 tegra114_primary_formats[] = { 553 DRM_FORMAT_ARGB4444, 554 DRM_FORMAT_ARGB1555, 555 DRM_FORMAT_RGB565, 556 DRM_FORMAT_RGBA5551, 557 DRM_FORMAT_ABGR8888, 558 DRM_FORMAT_ARGB8888, 559 /* new on Tegra114 */ 560 DRM_FORMAT_ABGR4444, 561 DRM_FORMAT_ABGR1555, 562 DRM_FORMAT_BGRA5551, 563 DRM_FORMAT_XRGB1555, 564 DRM_FORMAT_RGBX5551, 565 DRM_FORMAT_XBGR1555, 566 DRM_FORMAT_BGRX5551, 567 DRM_FORMAT_BGR565, 568 DRM_FORMAT_BGRA8888, 569 DRM_FORMAT_RGBA8888, 570 DRM_FORMAT_XRGB8888, 571 DRM_FORMAT_XBGR8888, 572 }; 573 574 static const u32 tegra124_primary_formats[] = { 575 DRM_FORMAT_ARGB4444, 576 DRM_FORMAT_ARGB1555, 577 DRM_FORMAT_RGB565, 578 DRM_FORMAT_RGBA5551, 579 DRM_FORMAT_ABGR8888, 580 DRM_FORMAT_ARGB8888, 581 /* new on Tegra114 */ 582 DRM_FORMAT_ABGR4444, 583 DRM_FORMAT_ABGR1555, 584 DRM_FORMAT_BGRA5551, 585 DRM_FORMAT_XRGB1555, 586 DRM_FORMAT_RGBX5551, 587 DRM_FORMAT_XBGR1555, 588 DRM_FORMAT_BGRX5551, 589 DRM_FORMAT_BGR565, 590 DRM_FORMAT_BGRA8888, 591 DRM_FORMAT_RGBA8888, 592 DRM_FORMAT_XRGB8888, 593 DRM_FORMAT_XBGR8888, 594 /* new on Tegra124 */ 595 DRM_FORMAT_RGBX8888, 596 DRM_FORMAT_BGRX8888, 597 }; 598 599 static const u64 tegra124_modifiers[] = { 600 DRM_FORMAT_MOD_LINEAR, 601 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(0), 602 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(1), 603 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(2), 604 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(3), 605 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(4), 606 DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK(5), 607 DRM_FORMAT_MOD_INVALID 608 }; 609 610 static int tegra_plane_atomic_check(struct drm_plane *plane, 611 struct drm_atomic_state *state) 612 { 613 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 614 plane); 615 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 616 unsigned int supported_rotation = DRM_MODE_ROTATE_0 | 617 DRM_MODE_REFLECT_X | 618 DRM_MODE_REFLECT_Y; 619 unsigned int rotation = new_plane_state->rotation; 620 struct tegra_bo_tiling *tiling = &plane_state->tiling; 621 struct tegra_plane *tegra = to_tegra_plane(plane); 622 struct tegra_dc *dc = to_tegra_dc(new_plane_state->crtc); 623 int err; 624 625 plane_state->peak_memory_bandwidth = 0; 626 plane_state->avg_memory_bandwidth = 0; 627 628 /* no need for further checks if the plane is being disabled */ 629 if (!new_plane_state->crtc) { 630 plane_state->total_peak_memory_bandwidth = 0; 631 return 0; 632 } 633 634 err = tegra_plane_format(new_plane_state->fb->format->format, 635 &plane_state->format, 636 &plane_state->swap); 637 if (err < 0) 638 return err; 639 640 /* 641 * Tegra20 and Tegra30 are special cases here because they support 642 * only variants of specific formats with an alpha component, but not 643 * the corresponding opaque formats. However, the opaque formats can 644 * be emulated by disabling alpha blending for the plane. 645 */ 646 if (dc->soc->has_legacy_blending) { 647 err = tegra_plane_setup_legacy_state(tegra, plane_state); 648 if (err < 0) 649 return err; 650 } 651 652 err = tegra_fb_get_tiling(new_plane_state->fb, tiling); 653 if (err < 0) 654 return err; 655 656 if (tiling->mode == TEGRA_BO_TILING_MODE_BLOCK && 657 !dc->soc->supports_block_linear) { 658 DRM_ERROR("hardware doesn't support block linear mode\n"); 659 return -EINVAL; 660 } 661 662 /* 663 * Older userspace used custom BO flag in order to specify the Y 664 * reflection, while modern userspace uses the generic DRM rotation 665 * property in order to achieve the same result. The legacy BO flag 666 * duplicates the DRM rotation property when both are set. 667 */ 668 if (tegra_fb_is_bottom_up(new_plane_state->fb)) 669 rotation |= DRM_MODE_REFLECT_Y; 670 671 rotation = drm_rotation_simplify(rotation, supported_rotation); 672 673 if (rotation & DRM_MODE_REFLECT_X) 674 plane_state->reflect_x = true; 675 else 676 plane_state->reflect_x = false; 677 678 if (rotation & DRM_MODE_REFLECT_Y) 679 plane_state->reflect_y = true; 680 else 681 plane_state->reflect_y = false; 682 683 /* 684 * Tegra doesn't support different strides for U and V planes so we 685 * error out if the user tries to display a framebuffer with such a 686 * configuration. 687 */ 688 if (new_plane_state->fb->format->num_planes > 2) { 689 if (new_plane_state->fb->pitches[2] != new_plane_state->fb->pitches[1]) { 690 DRM_ERROR("unsupported UV-plane configuration\n"); 691 return -EINVAL; 692 } 693 } 694 695 err = tegra_plane_state_add(tegra, new_plane_state); 696 if (err < 0) 697 return err; 698 699 return 0; 700 } 701 702 static void tegra_plane_atomic_disable(struct drm_plane *plane, 703 struct drm_atomic_state *state) 704 { 705 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 706 plane); 707 struct tegra_plane *p = to_tegra_plane(plane); 708 u32 value; 709 710 /* rien ne va plus */ 711 if (!old_state || !old_state->crtc) 712 return; 713 714 value = tegra_plane_readl(p, DC_WIN_WIN_OPTIONS); 715 value &= ~WIN_ENABLE; 716 tegra_plane_writel(p, value, DC_WIN_WIN_OPTIONS); 717 } 718 719 static void tegra_plane_atomic_update(struct drm_plane *plane, 720 struct drm_atomic_state *state) 721 { 722 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 723 plane); 724 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 725 struct drm_framebuffer *fb = new_state->fb; 726 struct tegra_plane *p = to_tegra_plane(plane); 727 struct tegra_dc_window window; 728 unsigned int i; 729 730 /* rien ne va plus */ 731 if (!new_state->crtc || !new_state->fb) 732 return; 733 734 if (!new_state->visible) 735 return tegra_plane_atomic_disable(plane, state); 736 737 memset(&window, 0, sizeof(window)); 738 window.src.x = new_state->src.x1 >> 16; 739 window.src.y = new_state->src.y1 >> 16; 740 window.src.w = drm_rect_width(&new_state->src) >> 16; 741 window.src.h = drm_rect_height(&new_state->src) >> 16; 742 window.dst.x = new_state->dst.x1; 743 window.dst.y = new_state->dst.y1; 744 window.dst.w = drm_rect_width(&new_state->dst); 745 window.dst.h = drm_rect_height(&new_state->dst); 746 window.bits_per_pixel = fb->format->cpp[0] * 8; 747 window.reflect_x = tegra_plane_state->reflect_x; 748 window.reflect_y = tegra_plane_state->reflect_y; 749 750 /* copy from state */ 751 window.zpos = new_state->normalized_zpos; 752 window.tiling = tegra_plane_state->tiling; 753 window.format = tegra_plane_state->format; 754 window.swap = tegra_plane_state->swap; 755 756 for (i = 0; i < fb->format->num_planes; i++) { 757 window.base[i] = tegra_plane_state->iova[i] + fb->offsets[i]; 758 759 /* 760 * Tegra uses a shared stride for UV planes. Framebuffers are 761 * already checked for this in the tegra_plane_atomic_check() 762 * function, so it's safe to ignore the V-plane pitch here. 763 */ 764 if (i < 2) 765 window.stride[i] = fb->pitches[i]; 766 } 767 768 tegra_dc_setup_window(p, &window); 769 } 770 771 static const struct drm_plane_helper_funcs tegra_plane_helper_funcs = { 772 .prepare_fb = tegra_plane_prepare_fb, 773 .cleanup_fb = tegra_plane_cleanup_fb, 774 .atomic_check = tegra_plane_atomic_check, 775 .atomic_disable = tegra_plane_atomic_disable, 776 .atomic_update = tegra_plane_atomic_update, 777 }; 778 779 static unsigned long tegra_plane_get_possible_crtcs(struct drm_device *drm) 780 { 781 /* 782 * Ideally this would use drm_crtc_mask(), but that would require the 783 * CRTC to already be in the mode_config's list of CRTCs. However, it 784 * will only be added to that list in the drm_crtc_init_with_planes() 785 * (in tegra_dc_init()), which in turn requires registration of these 786 * planes. So we have ourselves a nice little chicken and egg problem 787 * here. 788 * 789 * We work around this by manually creating the mask from the number 790 * of CRTCs that have been registered, and should therefore always be 791 * the same as drm_crtc_index() after registration. 792 */ 793 return 1 << drm->mode_config.num_crtc; 794 } 795 796 static struct drm_plane *tegra_primary_plane_create(struct drm_device *drm, 797 struct tegra_dc *dc) 798 { 799 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 800 enum drm_plane_type type = DRM_PLANE_TYPE_PRIMARY; 801 struct tegra_plane *plane; 802 unsigned int num_formats; 803 const u64 *modifiers; 804 const u32 *formats; 805 int err; 806 807 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 808 if (!plane) 809 return ERR_PTR(-ENOMEM); 810 811 /* Always use window A as primary window */ 812 plane->offset = 0xa00; 813 plane->index = 0; 814 plane->dc = dc; 815 816 num_formats = dc->soc->num_primary_formats; 817 formats = dc->soc->primary_formats; 818 modifiers = dc->soc->modifiers; 819 820 err = tegra_plane_interconnect_init(plane); 821 if (err) { 822 kfree(plane); 823 return ERR_PTR(err); 824 } 825 826 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 827 &tegra_plane_funcs, formats, 828 num_formats, modifiers, type, NULL); 829 if (err < 0) { 830 kfree(plane); 831 return ERR_PTR(err); 832 } 833 834 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 835 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 836 837 err = drm_plane_create_rotation_property(&plane->base, 838 DRM_MODE_ROTATE_0, 839 DRM_MODE_ROTATE_0 | 840 DRM_MODE_ROTATE_180 | 841 DRM_MODE_REFLECT_X | 842 DRM_MODE_REFLECT_Y); 843 if (err < 0) 844 dev_err(dc->dev, "failed to create rotation property: %d\n", 845 err); 846 847 return &plane->base; 848 } 849 850 static const u32 tegra_legacy_cursor_plane_formats[] = { 851 DRM_FORMAT_RGBA8888, 852 }; 853 854 static const u32 tegra_cursor_plane_formats[] = { 855 DRM_FORMAT_ARGB8888, 856 }; 857 858 static int tegra_cursor_atomic_check(struct drm_plane *plane, 859 struct drm_atomic_state *state) 860 { 861 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 862 plane); 863 struct tegra_plane_state *plane_state = to_tegra_plane_state(new_plane_state); 864 struct tegra_plane *tegra = to_tegra_plane(plane); 865 int err; 866 867 plane_state->peak_memory_bandwidth = 0; 868 plane_state->avg_memory_bandwidth = 0; 869 870 /* no need for further checks if the plane is being disabled */ 871 if (!new_plane_state->crtc) { 872 plane_state->total_peak_memory_bandwidth = 0; 873 return 0; 874 } 875 876 /* scaling not supported for cursor */ 877 if ((new_plane_state->src_w >> 16 != new_plane_state->crtc_w) || 878 (new_plane_state->src_h >> 16 != new_plane_state->crtc_h)) 879 return -EINVAL; 880 881 /* only square cursors supported */ 882 if (new_plane_state->src_w != new_plane_state->src_h) 883 return -EINVAL; 884 885 if (new_plane_state->crtc_w != 32 && new_plane_state->crtc_w != 64 && 886 new_plane_state->crtc_w != 128 && new_plane_state->crtc_w != 256) 887 return -EINVAL; 888 889 err = tegra_plane_state_add(tegra, new_plane_state); 890 if (err < 0) 891 return err; 892 893 return 0; 894 } 895 896 static void __tegra_cursor_atomic_update(struct drm_plane *plane, 897 struct drm_plane_state *new_state) 898 { 899 struct tegra_plane_state *tegra_plane_state = to_tegra_plane_state(new_state); 900 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 901 struct tegra_drm *tegra = plane->dev->dev_private; 902 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 903 u64 dma_mask = *dc->dev->dma_mask; 904 #endif 905 unsigned int x, y; 906 u32 value = 0; 907 908 /* rien ne va plus */ 909 if (!new_state->crtc || !new_state->fb) 910 return; 911 912 /* 913 * Legacy display supports hardware clipping of the cursor, but 914 * nvdisplay relies on software to clip the cursor to the screen. 915 */ 916 if (!dc->soc->has_nvdisplay) 917 value |= CURSOR_CLIP_DISPLAY; 918 919 switch (new_state->crtc_w) { 920 case 32: 921 value |= CURSOR_SIZE_32x32; 922 break; 923 924 case 64: 925 value |= CURSOR_SIZE_64x64; 926 break; 927 928 case 128: 929 value |= CURSOR_SIZE_128x128; 930 break; 931 932 case 256: 933 value |= CURSOR_SIZE_256x256; 934 break; 935 936 default: 937 WARN(1, "cursor size %ux%u not supported\n", 938 new_state->crtc_w, new_state->crtc_h); 939 return; 940 } 941 942 value |= (tegra_plane_state->iova[0] >> 10) & 0x3fffff; 943 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR); 944 945 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 946 value = (tegra_plane_state->iova[0] >> 32) & (dma_mask >> 32); 947 tegra_dc_writel(dc, value, DC_DISP_CURSOR_START_ADDR_HI); 948 #endif 949 950 /* enable cursor and set blend mode */ 951 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 952 value |= CURSOR_ENABLE; 953 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 954 955 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL); 956 value &= ~CURSOR_DST_BLEND_MASK; 957 value &= ~CURSOR_SRC_BLEND_MASK; 958 959 if (dc->soc->has_nvdisplay) 960 value &= ~CURSOR_COMPOSITION_MODE_XOR; 961 else 962 value |= CURSOR_MODE_NORMAL; 963 964 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC; 965 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC; 966 value |= CURSOR_ALPHA; 967 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL); 968 969 /* nvdisplay relies on software for clipping */ 970 if (dc->soc->has_nvdisplay) { 971 struct drm_rect src; 972 973 x = new_state->dst.x1; 974 y = new_state->dst.y1; 975 976 drm_rect_fp_to_int(&src, &new_state->src); 977 978 value = (src.y1 & tegra->vmask) << 16 | (src.x1 & tegra->hmask); 979 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_POINT_IN_CURSOR); 980 981 value = (drm_rect_height(&src) & tegra->vmask) << 16 | 982 (drm_rect_width(&src) & tegra->hmask); 983 tegra_dc_writel(dc, value, DC_DISP_PCALC_HEAD_SET_CROPPED_SIZE_IN_CURSOR); 984 } else { 985 x = new_state->crtc_x; 986 y = new_state->crtc_y; 987 } 988 989 /* position the cursor */ 990 value = ((y & tegra->vmask) << 16) | (x & tegra->hmask); 991 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION); 992 } 993 994 static void tegra_cursor_atomic_update(struct drm_plane *plane, 995 struct drm_atomic_state *state) 996 { 997 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 998 999 __tegra_cursor_atomic_update(plane, new_state); 1000 } 1001 1002 static void tegra_cursor_atomic_disable(struct drm_plane *plane, 1003 struct drm_atomic_state *state) 1004 { 1005 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 1006 plane); 1007 struct tegra_dc *dc; 1008 u32 value; 1009 1010 /* rien ne va plus */ 1011 if (!old_state || !old_state->crtc) 1012 return; 1013 1014 dc = to_tegra_dc(old_state->crtc); 1015 1016 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); 1017 value &= ~CURSOR_ENABLE; 1018 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); 1019 } 1020 1021 static int tegra_cursor_atomic_async_check(struct drm_plane *plane, struct drm_atomic_state *state) 1022 { 1023 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1024 struct drm_crtc_state *crtc_state; 1025 int min_scale, max_scale; 1026 int err; 1027 1028 crtc_state = drm_atomic_get_existing_crtc_state(state, new_state->crtc); 1029 if (WARN_ON(!crtc_state)) 1030 return -EINVAL; 1031 1032 if (!crtc_state->active) 1033 return -EINVAL; 1034 1035 if (plane->state->crtc != new_state->crtc || 1036 plane->state->src_w != new_state->src_w || 1037 plane->state->src_h != new_state->src_h || 1038 plane->state->crtc_w != new_state->crtc_w || 1039 plane->state->crtc_h != new_state->crtc_h || 1040 plane->state->fb != new_state->fb || 1041 plane->state->fb == NULL) 1042 return -EINVAL; 1043 1044 min_scale = (1 << 16) / 8; 1045 max_scale = (8 << 16) / 1; 1046 1047 err = drm_atomic_helper_check_plane_state(new_state, crtc_state, min_scale, max_scale, 1048 true, true); 1049 if (err < 0) 1050 return err; 1051 1052 if (new_state->visible != plane->state->visible) 1053 return -EINVAL; 1054 1055 return 0; 1056 } 1057 1058 static void tegra_cursor_atomic_async_update(struct drm_plane *plane, 1059 struct drm_atomic_state *state) 1060 { 1061 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane); 1062 struct tegra_dc *dc = to_tegra_dc(new_state->crtc); 1063 1064 plane->state->src_x = new_state->src_x; 1065 plane->state->src_y = new_state->src_y; 1066 plane->state->crtc_x = new_state->crtc_x; 1067 plane->state->crtc_y = new_state->crtc_y; 1068 1069 if (new_state->visible) { 1070 struct tegra_plane *p = to_tegra_plane(plane); 1071 u32 value; 1072 1073 __tegra_cursor_atomic_update(plane, new_state); 1074 1075 value = (WIN_A_ACT_REQ << p->index) << 8 | GENERAL_UPDATE; 1076 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1077 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1078 1079 value = (WIN_A_ACT_REQ << p->index) | GENERAL_ACT_REQ; 1080 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 1081 (void)tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 1082 } 1083 } 1084 1085 static const struct drm_plane_helper_funcs tegra_cursor_plane_helper_funcs = { 1086 .prepare_fb = tegra_plane_prepare_fb, 1087 .cleanup_fb = tegra_plane_cleanup_fb, 1088 .atomic_check = tegra_cursor_atomic_check, 1089 .atomic_update = tegra_cursor_atomic_update, 1090 .atomic_disable = tegra_cursor_atomic_disable, 1091 .atomic_async_check = tegra_cursor_atomic_async_check, 1092 .atomic_async_update = tegra_cursor_atomic_async_update, 1093 }; 1094 1095 static const uint64_t linear_modifiers[] = { 1096 DRM_FORMAT_MOD_LINEAR, 1097 DRM_FORMAT_MOD_INVALID 1098 }; 1099 1100 static struct drm_plane *tegra_dc_cursor_plane_create(struct drm_device *drm, 1101 struct tegra_dc *dc) 1102 { 1103 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1104 struct tegra_plane *plane; 1105 unsigned int num_formats; 1106 const u32 *formats; 1107 int err; 1108 1109 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1110 if (!plane) 1111 return ERR_PTR(-ENOMEM); 1112 1113 /* 1114 * This index is kind of fake. The cursor isn't a regular plane, but 1115 * its update and activation request bits in DC_CMD_STATE_CONTROL do 1116 * use the same programming. Setting this fake index here allows the 1117 * code in tegra_add_plane_state() to do the right thing without the 1118 * need to special-casing the cursor plane. 1119 */ 1120 plane->index = 6; 1121 plane->dc = dc; 1122 1123 if (!dc->soc->has_nvdisplay) { 1124 num_formats = ARRAY_SIZE(tegra_legacy_cursor_plane_formats); 1125 formats = tegra_legacy_cursor_plane_formats; 1126 1127 err = tegra_plane_interconnect_init(plane); 1128 if (err) { 1129 kfree(plane); 1130 return ERR_PTR(err); 1131 } 1132 } else { 1133 num_formats = ARRAY_SIZE(tegra_cursor_plane_formats); 1134 formats = tegra_cursor_plane_formats; 1135 } 1136 1137 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1138 &tegra_plane_funcs, formats, 1139 num_formats, linear_modifiers, 1140 DRM_PLANE_TYPE_CURSOR, NULL); 1141 if (err < 0) { 1142 kfree(plane); 1143 return ERR_PTR(err); 1144 } 1145 1146 drm_plane_helper_add(&plane->base, &tegra_cursor_plane_helper_funcs); 1147 drm_plane_create_zpos_immutable_property(&plane->base, 255); 1148 1149 return &plane->base; 1150 } 1151 1152 static const u32 tegra20_overlay_formats[] = { 1153 DRM_FORMAT_ARGB4444, 1154 DRM_FORMAT_ARGB1555, 1155 DRM_FORMAT_RGB565, 1156 DRM_FORMAT_RGBA5551, 1157 DRM_FORMAT_ABGR8888, 1158 DRM_FORMAT_ARGB8888, 1159 /* non-native formats */ 1160 DRM_FORMAT_XRGB1555, 1161 DRM_FORMAT_RGBX5551, 1162 DRM_FORMAT_XBGR8888, 1163 DRM_FORMAT_XRGB8888, 1164 /* planar formats */ 1165 DRM_FORMAT_UYVY, 1166 DRM_FORMAT_YUYV, 1167 DRM_FORMAT_YUV420, 1168 DRM_FORMAT_YUV422, 1169 }; 1170 1171 static const u32 tegra114_overlay_formats[] = { 1172 DRM_FORMAT_ARGB4444, 1173 DRM_FORMAT_ARGB1555, 1174 DRM_FORMAT_RGB565, 1175 DRM_FORMAT_RGBA5551, 1176 DRM_FORMAT_ABGR8888, 1177 DRM_FORMAT_ARGB8888, 1178 /* new on Tegra114 */ 1179 DRM_FORMAT_ABGR4444, 1180 DRM_FORMAT_ABGR1555, 1181 DRM_FORMAT_BGRA5551, 1182 DRM_FORMAT_XRGB1555, 1183 DRM_FORMAT_RGBX5551, 1184 DRM_FORMAT_XBGR1555, 1185 DRM_FORMAT_BGRX5551, 1186 DRM_FORMAT_BGR565, 1187 DRM_FORMAT_BGRA8888, 1188 DRM_FORMAT_RGBA8888, 1189 DRM_FORMAT_XRGB8888, 1190 DRM_FORMAT_XBGR8888, 1191 /* planar formats */ 1192 DRM_FORMAT_UYVY, 1193 DRM_FORMAT_YUYV, 1194 DRM_FORMAT_YUV420, 1195 DRM_FORMAT_YUV422, 1196 }; 1197 1198 static const u32 tegra124_overlay_formats[] = { 1199 DRM_FORMAT_ARGB4444, 1200 DRM_FORMAT_ARGB1555, 1201 DRM_FORMAT_RGB565, 1202 DRM_FORMAT_RGBA5551, 1203 DRM_FORMAT_ABGR8888, 1204 DRM_FORMAT_ARGB8888, 1205 /* new on Tegra114 */ 1206 DRM_FORMAT_ABGR4444, 1207 DRM_FORMAT_ABGR1555, 1208 DRM_FORMAT_BGRA5551, 1209 DRM_FORMAT_XRGB1555, 1210 DRM_FORMAT_RGBX5551, 1211 DRM_FORMAT_XBGR1555, 1212 DRM_FORMAT_BGRX5551, 1213 DRM_FORMAT_BGR565, 1214 DRM_FORMAT_BGRA8888, 1215 DRM_FORMAT_RGBA8888, 1216 DRM_FORMAT_XRGB8888, 1217 DRM_FORMAT_XBGR8888, 1218 /* new on Tegra124 */ 1219 DRM_FORMAT_RGBX8888, 1220 DRM_FORMAT_BGRX8888, 1221 /* planar formats */ 1222 DRM_FORMAT_UYVY, 1223 DRM_FORMAT_YUYV, 1224 DRM_FORMAT_YUV420, 1225 DRM_FORMAT_YUV422, 1226 }; 1227 1228 static struct drm_plane *tegra_dc_overlay_plane_create(struct drm_device *drm, 1229 struct tegra_dc *dc, 1230 unsigned int index, 1231 bool cursor) 1232 { 1233 unsigned long possible_crtcs = tegra_plane_get_possible_crtcs(drm); 1234 struct tegra_plane *plane; 1235 unsigned int num_formats; 1236 enum drm_plane_type type; 1237 const u32 *formats; 1238 int err; 1239 1240 plane = kzalloc(sizeof(*plane), GFP_KERNEL); 1241 if (!plane) 1242 return ERR_PTR(-ENOMEM); 1243 1244 plane->offset = 0xa00 + 0x200 * index; 1245 plane->index = index; 1246 plane->dc = dc; 1247 1248 num_formats = dc->soc->num_overlay_formats; 1249 formats = dc->soc->overlay_formats; 1250 1251 err = tegra_plane_interconnect_init(plane); 1252 if (err) { 1253 kfree(plane); 1254 return ERR_PTR(err); 1255 } 1256 1257 if (!cursor) 1258 type = DRM_PLANE_TYPE_OVERLAY; 1259 else 1260 type = DRM_PLANE_TYPE_CURSOR; 1261 1262 err = drm_universal_plane_init(drm, &plane->base, possible_crtcs, 1263 &tegra_plane_funcs, formats, 1264 num_formats, linear_modifiers, 1265 type, NULL); 1266 if (err < 0) { 1267 kfree(plane); 1268 return ERR_PTR(err); 1269 } 1270 1271 drm_plane_helper_add(&plane->base, &tegra_plane_helper_funcs); 1272 drm_plane_create_zpos_property(&plane->base, plane->index, 0, 255); 1273 1274 err = drm_plane_create_rotation_property(&plane->base, 1275 DRM_MODE_ROTATE_0, 1276 DRM_MODE_ROTATE_0 | 1277 DRM_MODE_ROTATE_180 | 1278 DRM_MODE_REFLECT_X | 1279 DRM_MODE_REFLECT_Y); 1280 if (err < 0) 1281 dev_err(dc->dev, "failed to create rotation property: %d\n", 1282 err); 1283 1284 return &plane->base; 1285 } 1286 1287 static struct drm_plane *tegra_dc_add_shared_planes(struct drm_device *drm, 1288 struct tegra_dc *dc) 1289 { 1290 struct drm_plane *plane, *primary = NULL; 1291 unsigned int i, j; 1292 1293 for (i = 0; i < dc->soc->num_wgrps; i++) { 1294 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 1295 1296 if (wgrp->dc == dc->pipe) { 1297 for (j = 0; j < wgrp->num_windows; j++) { 1298 unsigned int index = wgrp->windows[j]; 1299 1300 plane = tegra_shared_plane_create(drm, dc, 1301 wgrp->index, 1302 index); 1303 if (IS_ERR(plane)) 1304 return plane; 1305 1306 /* 1307 * Choose the first shared plane owned by this 1308 * head as the primary plane. 1309 */ 1310 if (!primary) { 1311 plane->type = DRM_PLANE_TYPE_PRIMARY; 1312 primary = plane; 1313 } 1314 } 1315 } 1316 } 1317 1318 return primary; 1319 } 1320 1321 static struct drm_plane *tegra_dc_add_planes(struct drm_device *drm, 1322 struct tegra_dc *dc) 1323 { 1324 struct drm_plane *planes[2], *primary; 1325 unsigned int planes_num; 1326 unsigned int i; 1327 int err; 1328 1329 primary = tegra_primary_plane_create(drm, dc); 1330 if (IS_ERR(primary)) 1331 return primary; 1332 1333 if (dc->soc->supports_cursor) 1334 planes_num = 2; 1335 else 1336 planes_num = 1; 1337 1338 for (i = 0; i < planes_num; i++) { 1339 planes[i] = tegra_dc_overlay_plane_create(drm, dc, 1 + i, 1340 false); 1341 if (IS_ERR(planes[i])) { 1342 err = PTR_ERR(planes[i]); 1343 1344 while (i--) 1345 planes[i]->funcs->destroy(planes[i]); 1346 1347 primary->funcs->destroy(primary); 1348 return ERR_PTR(err); 1349 } 1350 } 1351 1352 return primary; 1353 } 1354 1355 static void tegra_dc_destroy(struct drm_crtc *crtc) 1356 { 1357 drm_crtc_cleanup(crtc); 1358 } 1359 1360 static void tegra_crtc_reset(struct drm_crtc *crtc) 1361 { 1362 struct tegra_dc_state *state = kzalloc(sizeof(*state), GFP_KERNEL); 1363 1364 if (crtc->state) 1365 tegra_crtc_atomic_destroy_state(crtc, crtc->state); 1366 1367 __drm_atomic_helper_crtc_reset(crtc, &state->base); 1368 } 1369 1370 static struct drm_crtc_state * 1371 tegra_crtc_atomic_duplicate_state(struct drm_crtc *crtc) 1372 { 1373 struct tegra_dc_state *state = to_dc_state(crtc->state); 1374 struct tegra_dc_state *copy; 1375 1376 copy = kmalloc(sizeof(*copy), GFP_KERNEL); 1377 if (!copy) 1378 return NULL; 1379 1380 __drm_atomic_helper_crtc_duplicate_state(crtc, ©->base); 1381 copy->clk = state->clk; 1382 copy->pclk = state->pclk; 1383 copy->div = state->div; 1384 copy->planes = state->planes; 1385 1386 return ©->base; 1387 } 1388 1389 static void tegra_crtc_atomic_destroy_state(struct drm_crtc *crtc, 1390 struct drm_crtc_state *state) 1391 { 1392 __drm_atomic_helper_crtc_destroy_state(state); 1393 kfree(state); 1394 } 1395 1396 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name } 1397 1398 static const struct debugfs_reg32 tegra_dc_regs[] = { 1399 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT), 1400 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL), 1401 DEBUGFS_REG32(DC_CMD_GENERAL_INCR_SYNCPT_ERROR), 1402 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT), 1403 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL), 1404 DEBUGFS_REG32(DC_CMD_WIN_A_INCR_SYNCPT_ERROR), 1405 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT), 1406 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL), 1407 DEBUGFS_REG32(DC_CMD_WIN_B_INCR_SYNCPT_ERROR), 1408 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT), 1409 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL), 1410 DEBUGFS_REG32(DC_CMD_WIN_C_INCR_SYNCPT_ERROR), 1411 DEBUGFS_REG32(DC_CMD_CONT_SYNCPT_VSYNC), 1412 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND_OPTION0), 1413 DEBUGFS_REG32(DC_CMD_DISPLAY_COMMAND), 1414 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE), 1415 DEBUGFS_REG32(DC_CMD_DISPLAY_POWER_CONTROL), 1416 DEBUGFS_REG32(DC_CMD_INT_STATUS), 1417 DEBUGFS_REG32(DC_CMD_INT_MASK), 1418 DEBUGFS_REG32(DC_CMD_INT_ENABLE), 1419 DEBUGFS_REG32(DC_CMD_INT_TYPE), 1420 DEBUGFS_REG32(DC_CMD_INT_POLARITY), 1421 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE1), 1422 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE2), 1423 DEBUGFS_REG32(DC_CMD_SIGNAL_RAISE3), 1424 DEBUGFS_REG32(DC_CMD_STATE_ACCESS), 1425 DEBUGFS_REG32(DC_CMD_STATE_CONTROL), 1426 DEBUGFS_REG32(DC_CMD_DISPLAY_WINDOW_HEADER), 1427 DEBUGFS_REG32(DC_CMD_REG_ACT_CONTROL), 1428 DEBUGFS_REG32(DC_COM_CRC_CONTROL), 1429 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM), 1430 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(0)), 1431 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(1)), 1432 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(2)), 1433 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_ENABLE(3)), 1434 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(0)), 1435 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(1)), 1436 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(2)), 1437 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_POLARITY(3)), 1438 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(0)), 1439 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(1)), 1440 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(2)), 1441 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_DATA(3)), 1442 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(0)), 1443 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(1)), 1444 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(2)), 1445 DEBUGFS_REG32(DC_COM_PIN_INPUT_ENABLE(3)), 1446 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(0)), 1447 DEBUGFS_REG32(DC_COM_PIN_INPUT_DATA(1)), 1448 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(0)), 1449 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(1)), 1450 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(2)), 1451 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(3)), 1452 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(4)), 1453 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(5)), 1454 DEBUGFS_REG32(DC_COM_PIN_OUTPUT_SELECT(6)), 1455 DEBUGFS_REG32(DC_COM_PIN_MISC_CONTROL), 1456 DEBUGFS_REG32(DC_COM_PIN_PM0_CONTROL), 1457 DEBUGFS_REG32(DC_COM_PIN_PM0_DUTY_CYCLE), 1458 DEBUGFS_REG32(DC_COM_PIN_PM1_CONTROL), 1459 DEBUGFS_REG32(DC_COM_PIN_PM1_DUTY_CYCLE), 1460 DEBUGFS_REG32(DC_COM_SPI_CONTROL), 1461 DEBUGFS_REG32(DC_COM_SPI_START_BYTE), 1462 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_AB), 1463 DEBUGFS_REG32(DC_COM_HSPI_WRITE_DATA_CD), 1464 DEBUGFS_REG32(DC_COM_HSPI_CS_DC), 1465 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_A), 1466 DEBUGFS_REG32(DC_COM_SCRATCH_REGISTER_B), 1467 DEBUGFS_REG32(DC_COM_GPIO_CTRL), 1468 DEBUGFS_REG32(DC_COM_GPIO_DEBOUNCE_COUNTER), 1469 DEBUGFS_REG32(DC_COM_CRC_CHECKSUM_LATCHED), 1470 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS0), 1471 DEBUGFS_REG32(DC_DISP_DISP_SIGNAL_OPTIONS1), 1472 DEBUGFS_REG32(DC_DISP_DISP_WIN_OPTIONS), 1473 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY), 1474 DEBUGFS_REG32(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER), 1475 DEBUGFS_REG32(DC_DISP_DISP_TIMING_OPTIONS), 1476 DEBUGFS_REG32(DC_DISP_REF_TO_SYNC), 1477 DEBUGFS_REG32(DC_DISP_SYNC_WIDTH), 1478 DEBUGFS_REG32(DC_DISP_BACK_PORCH), 1479 DEBUGFS_REG32(DC_DISP_ACTIVE), 1480 DEBUGFS_REG32(DC_DISP_FRONT_PORCH), 1481 DEBUGFS_REG32(DC_DISP_H_PULSE0_CONTROL), 1482 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_A), 1483 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_B), 1484 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_C), 1485 DEBUGFS_REG32(DC_DISP_H_PULSE0_POSITION_D), 1486 DEBUGFS_REG32(DC_DISP_H_PULSE1_CONTROL), 1487 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_A), 1488 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_B), 1489 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_C), 1490 DEBUGFS_REG32(DC_DISP_H_PULSE1_POSITION_D), 1491 DEBUGFS_REG32(DC_DISP_H_PULSE2_CONTROL), 1492 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_A), 1493 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_B), 1494 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_C), 1495 DEBUGFS_REG32(DC_DISP_H_PULSE2_POSITION_D), 1496 DEBUGFS_REG32(DC_DISP_V_PULSE0_CONTROL), 1497 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_A), 1498 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_B), 1499 DEBUGFS_REG32(DC_DISP_V_PULSE0_POSITION_C), 1500 DEBUGFS_REG32(DC_DISP_V_PULSE1_CONTROL), 1501 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_A), 1502 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_B), 1503 DEBUGFS_REG32(DC_DISP_V_PULSE1_POSITION_C), 1504 DEBUGFS_REG32(DC_DISP_V_PULSE2_CONTROL), 1505 DEBUGFS_REG32(DC_DISP_V_PULSE2_POSITION_A), 1506 DEBUGFS_REG32(DC_DISP_V_PULSE3_CONTROL), 1507 DEBUGFS_REG32(DC_DISP_V_PULSE3_POSITION_A), 1508 DEBUGFS_REG32(DC_DISP_M0_CONTROL), 1509 DEBUGFS_REG32(DC_DISP_M1_CONTROL), 1510 DEBUGFS_REG32(DC_DISP_DI_CONTROL), 1511 DEBUGFS_REG32(DC_DISP_PP_CONTROL), 1512 DEBUGFS_REG32(DC_DISP_PP_SELECT_A), 1513 DEBUGFS_REG32(DC_DISP_PP_SELECT_B), 1514 DEBUGFS_REG32(DC_DISP_PP_SELECT_C), 1515 DEBUGFS_REG32(DC_DISP_PP_SELECT_D), 1516 DEBUGFS_REG32(DC_DISP_DISP_CLOCK_CONTROL), 1517 DEBUGFS_REG32(DC_DISP_DISP_INTERFACE_CONTROL), 1518 DEBUGFS_REG32(DC_DISP_DISP_COLOR_CONTROL), 1519 DEBUGFS_REG32(DC_DISP_SHIFT_CLOCK_OPTIONS), 1520 DEBUGFS_REG32(DC_DISP_DATA_ENABLE_OPTIONS), 1521 DEBUGFS_REG32(DC_DISP_SERIAL_INTERFACE_OPTIONS), 1522 DEBUGFS_REG32(DC_DISP_LCD_SPI_OPTIONS), 1523 DEBUGFS_REG32(DC_DISP_BORDER_COLOR), 1524 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_LOWER), 1525 DEBUGFS_REG32(DC_DISP_COLOR_KEY0_UPPER), 1526 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_LOWER), 1527 DEBUGFS_REG32(DC_DISP_COLOR_KEY1_UPPER), 1528 DEBUGFS_REG32(DC_DISP_CURSOR_FOREGROUND), 1529 DEBUGFS_REG32(DC_DISP_CURSOR_BACKGROUND), 1530 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR), 1531 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_NS), 1532 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION), 1533 DEBUGFS_REG32(DC_DISP_CURSOR_POSITION_NS), 1534 DEBUGFS_REG32(DC_DISP_INIT_SEQ_CONTROL), 1535 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_A), 1536 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_B), 1537 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_C), 1538 DEBUGFS_REG32(DC_DISP_SPI_INIT_SEQ_DATA_D), 1539 DEBUGFS_REG32(DC_DISP_DC_MCCIF_FIFOCTRL), 1540 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0A_HYST), 1541 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY0B_HYST), 1542 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1A_HYST), 1543 DEBUGFS_REG32(DC_DISP_MCCIF_DISPLAY1B_HYST), 1544 DEBUGFS_REG32(DC_DISP_DAC_CRT_CTRL), 1545 DEBUGFS_REG32(DC_DISP_DISP_MISC_CONTROL), 1546 DEBUGFS_REG32(DC_DISP_SD_CONTROL), 1547 DEBUGFS_REG32(DC_DISP_SD_CSC_COEFF), 1548 DEBUGFS_REG32(DC_DISP_SD_LUT(0)), 1549 DEBUGFS_REG32(DC_DISP_SD_LUT(1)), 1550 DEBUGFS_REG32(DC_DISP_SD_LUT(2)), 1551 DEBUGFS_REG32(DC_DISP_SD_LUT(3)), 1552 DEBUGFS_REG32(DC_DISP_SD_LUT(4)), 1553 DEBUGFS_REG32(DC_DISP_SD_LUT(5)), 1554 DEBUGFS_REG32(DC_DISP_SD_LUT(6)), 1555 DEBUGFS_REG32(DC_DISP_SD_LUT(7)), 1556 DEBUGFS_REG32(DC_DISP_SD_LUT(8)), 1557 DEBUGFS_REG32(DC_DISP_SD_FLICKER_CONTROL), 1558 DEBUGFS_REG32(DC_DISP_DC_PIXEL_COUNT), 1559 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(0)), 1560 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(1)), 1561 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(2)), 1562 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(3)), 1563 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(4)), 1564 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(5)), 1565 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(6)), 1566 DEBUGFS_REG32(DC_DISP_SD_HISTOGRAM(7)), 1567 DEBUGFS_REG32(DC_DISP_SD_BL_TF(0)), 1568 DEBUGFS_REG32(DC_DISP_SD_BL_TF(1)), 1569 DEBUGFS_REG32(DC_DISP_SD_BL_TF(2)), 1570 DEBUGFS_REG32(DC_DISP_SD_BL_TF(3)), 1571 DEBUGFS_REG32(DC_DISP_SD_BL_CONTROL), 1572 DEBUGFS_REG32(DC_DISP_SD_HW_K_VALUES), 1573 DEBUGFS_REG32(DC_DISP_SD_MAN_K_VALUES), 1574 DEBUGFS_REG32(DC_DISP_CURSOR_START_ADDR_HI), 1575 DEBUGFS_REG32(DC_DISP_BLEND_CURSOR_CONTROL), 1576 DEBUGFS_REG32(DC_WIN_WIN_OPTIONS), 1577 DEBUGFS_REG32(DC_WIN_BYTE_SWAP), 1578 DEBUGFS_REG32(DC_WIN_BUFFER_CONTROL), 1579 DEBUGFS_REG32(DC_WIN_COLOR_DEPTH), 1580 DEBUGFS_REG32(DC_WIN_POSITION), 1581 DEBUGFS_REG32(DC_WIN_SIZE), 1582 DEBUGFS_REG32(DC_WIN_PRESCALED_SIZE), 1583 DEBUGFS_REG32(DC_WIN_H_INITIAL_DDA), 1584 DEBUGFS_REG32(DC_WIN_V_INITIAL_DDA), 1585 DEBUGFS_REG32(DC_WIN_DDA_INC), 1586 DEBUGFS_REG32(DC_WIN_LINE_STRIDE), 1587 DEBUGFS_REG32(DC_WIN_BUF_STRIDE), 1588 DEBUGFS_REG32(DC_WIN_UV_BUF_STRIDE), 1589 DEBUGFS_REG32(DC_WIN_BUFFER_ADDR_MODE), 1590 DEBUGFS_REG32(DC_WIN_DV_CONTROL), 1591 DEBUGFS_REG32(DC_WIN_BLEND_NOKEY), 1592 DEBUGFS_REG32(DC_WIN_BLEND_1WIN), 1593 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_X), 1594 DEBUGFS_REG32(DC_WIN_BLEND_2WIN_Y), 1595 DEBUGFS_REG32(DC_WIN_BLEND_3WIN_XY), 1596 DEBUGFS_REG32(DC_WIN_HP_FETCH_CONTROL), 1597 DEBUGFS_REG32(DC_WINBUF_START_ADDR), 1598 DEBUGFS_REG32(DC_WINBUF_START_ADDR_NS), 1599 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U), 1600 DEBUGFS_REG32(DC_WINBUF_START_ADDR_U_NS), 1601 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V), 1602 DEBUGFS_REG32(DC_WINBUF_START_ADDR_V_NS), 1603 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET), 1604 DEBUGFS_REG32(DC_WINBUF_ADDR_H_OFFSET_NS), 1605 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET), 1606 DEBUGFS_REG32(DC_WINBUF_ADDR_V_OFFSET_NS), 1607 DEBUGFS_REG32(DC_WINBUF_UFLOW_STATUS), 1608 DEBUGFS_REG32(DC_WINBUF_AD_UFLOW_STATUS), 1609 DEBUGFS_REG32(DC_WINBUF_BD_UFLOW_STATUS), 1610 DEBUGFS_REG32(DC_WINBUF_CD_UFLOW_STATUS), 1611 }; 1612 1613 static int tegra_dc_show_regs(struct seq_file *s, void *data) 1614 { 1615 struct drm_info_node *node = s->private; 1616 struct tegra_dc *dc = node->info_ent->data; 1617 unsigned int i; 1618 int err = 0; 1619 1620 drm_modeset_lock(&dc->base.mutex, NULL); 1621 1622 if (!dc->base.state->active) { 1623 err = -EBUSY; 1624 goto unlock; 1625 } 1626 1627 for (i = 0; i < ARRAY_SIZE(tegra_dc_regs); i++) { 1628 unsigned int offset = tegra_dc_regs[i].offset; 1629 1630 seq_printf(s, "%-40s %#05x %08x\n", tegra_dc_regs[i].name, 1631 offset, tegra_dc_readl(dc, offset)); 1632 } 1633 1634 unlock: 1635 drm_modeset_unlock(&dc->base.mutex); 1636 return err; 1637 } 1638 1639 static int tegra_dc_show_crc(struct seq_file *s, void *data) 1640 { 1641 struct drm_info_node *node = s->private; 1642 struct tegra_dc *dc = node->info_ent->data; 1643 int err = 0; 1644 u32 value; 1645 1646 drm_modeset_lock(&dc->base.mutex, NULL); 1647 1648 if (!dc->base.state->active) { 1649 err = -EBUSY; 1650 goto unlock; 1651 } 1652 1653 value = DC_COM_CRC_CONTROL_ACTIVE_DATA | DC_COM_CRC_CONTROL_ENABLE; 1654 tegra_dc_writel(dc, value, DC_COM_CRC_CONTROL); 1655 tegra_dc_commit(dc); 1656 1657 drm_crtc_wait_one_vblank(&dc->base); 1658 drm_crtc_wait_one_vblank(&dc->base); 1659 1660 value = tegra_dc_readl(dc, DC_COM_CRC_CHECKSUM); 1661 seq_printf(s, "%08x\n", value); 1662 1663 tegra_dc_writel(dc, 0, DC_COM_CRC_CONTROL); 1664 1665 unlock: 1666 drm_modeset_unlock(&dc->base.mutex); 1667 return err; 1668 } 1669 1670 static int tegra_dc_show_stats(struct seq_file *s, void *data) 1671 { 1672 struct drm_info_node *node = s->private; 1673 struct tegra_dc *dc = node->info_ent->data; 1674 1675 seq_printf(s, "frames: %lu\n", dc->stats.frames); 1676 seq_printf(s, "vblank: %lu\n", dc->stats.vblank); 1677 seq_printf(s, "underflow: %lu\n", dc->stats.underflow); 1678 seq_printf(s, "overflow: %lu\n", dc->stats.overflow); 1679 1680 seq_printf(s, "frames total: %lu\n", dc->stats.frames_total); 1681 seq_printf(s, "vblank total: %lu\n", dc->stats.vblank_total); 1682 seq_printf(s, "underflow total: %lu\n", dc->stats.underflow_total); 1683 seq_printf(s, "overflow total: %lu\n", dc->stats.overflow_total); 1684 1685 return 0; 1686 } 1687 1688 static struct drm_info_list debugfs_files[] = { 1689 { "regs", tegra_dc_show_regs, 0, NULL }, 1690 { "crc", tegra_dc_show_crc, 0, NULL }, 1691 { "stats", tegra_dc_show_stats, 0, NULL }, 1692 }; 1693 1694 static int tegra_dc_late_register(struct drm_crtc *crtc) 1695 { 1696 unsigned int i, count = ARRAY_SIZE(debugfs_files); 1697 struct drm_minor *minor = crtc->dev->primary; 1698 struct dentry *root; 1699 struct tegra_dc *dc = to_tegra_dc(crtc); 1700 1701 #ifdef CONFIG_DEBUG_FS 1702 root = crtc->debugfs_entry; 1703 #else 1704 root = NULL; 1705 #endif 1706 1707 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), 1708 GFP_KERNEL); 1709 if (!dc->debugfs_files) 1710 return -ENOMEM; 1711 1712 for (i = 0; i < count; i++) 1713 dc->debugfs_files[i].data = dc; 1714 1715 drm_debugfs_create_files(dc->debugfs_files, count, root, minor); 1716 1717 return 0; 1718 } 1719 1720 static void tegra_dc_early_unregister(struct drm_crtc *crtc) 1721 { 1722 unsigned int count = ARRAY_SIZE(debugfs_files); 1723 struct drm_minor *minor = crtc->dev->primary; 1724 struct tegra_dc *dc = to_tegra_dc(crtc); 1725 1726 drm_debugfs_remove_files(dc->debugfs_files, count, minor); 1727 kfree(dc->debugfs_files); 1728 dc->debugfs_files = NULL; 1729 } 1730 1731 static u32 tegra_dc_get_vblank_counter(struct drm_crtc *crtc) 1732 { 1733 struct tegra_dc *dc = to_tegra_dc(crtc); 1734 1735 /* XXX vblank syncpoints don't work with nvdisplay yet */ 1736 if (dc->syncpt && !dc->soc->has_nvdisplay) 1737 return host1x_syncpt_read(dc->syncpt); 1738 1739 /* fallback to software emulated VBLANK counter */ 1740 return (u32)drm_crtc_vblank_count(&dc->base); 1741 } 1742 1743 static int tegra_dc_enable_vblank(struct drm_crtc *crtc) 1744 { 1745 struct tegra_dc *dc = to_tegra_dc(crtc); 1746 u32 value; 1747 1748 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1749 value |= VBLANK_INT; 1750 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1751 1752 return 0; 1753 } 1754 1755 static void tegra_dc_disable_vblank(struct drm_crtc *crtc) 1756 { 1757 struct tegra_dc *dc = to_tegra_dc(crtc); 1758 u32 value; 1759 1760 value = tegra_dc_readl(dc, DC_CMD_INT_MASK); 1761 value &= ~VBLANK_INT; 1762 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 1763 } 1764 1765 static const struct drm_crtc_funcs tegra_crtc_funcs = { 1766 .page_flip = drm_atomic_helper_page_flip, 1767 .set_config = drm_atomic_helper_set_config, 1768 .destroy = tegra_dc_destroy, 1769 .reset = tegra_crtc_reset, 1770 .atomic_duplicate_state = tegra_crtc_atomic_duplicate_state, 1771 .atomic_destroy_state = tegra_crtc_atomic_destroy_state, 1772 .late_register = tegra_dc_late_register, 1773 .early_unregister = tegra_dc_early_unregister, 1774 .get_vblank_counter = tegra_dc_get_vblank_counter, 1775 .enable_vblank = tegra_dc_enable_vblank, 1776 .disable_vblank = tegra_dc_disable_vblank, 1777 }; 1778 1779 static int tegra_dc_set_timings(struct tegra_dc *dc, 1780 struct drm_display_mode *mode) 1781 { 1782 unsigned int h_ref_to_sync = 1; 1783 unsigned int v_ref_to_sync = 1; 1784 unsigned long value; 1785 1786 if (!dc->soc->has_nvdisplay) { 1787 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS); 1788 1789 value = (v_ref_to_sync << 16) | h_ref_to_sync; 1790 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC); 1791 } 1792 1793 value = ((mode->vsync_end - mode->vsync_start) << 16) | 1794 ((mode->hsync_end - mode->hsync_start) << 0); 1795 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH); 1796 1797 value = ((mode->vtotal - mode->vsync_end) << 16) | 1798 ((mode->htotal - mode->hsync_end) << 0); 1799 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH); 1800 1801 value = ((mode->vsync_start - mode->vdisplay) << 16) | 1802 ((mode->hsync_start - mode->hdisplay) << 0); 1803 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH); 1804 1805 value = (mode->vdisplay << 16) | mode->hdisplay; 1806 tegra_dc_writel(dc, value, DC_DISP_ACTIVE); 1807 1808 return 0; 1809 } 1810 1811 /** 1812 * tegra_dc_state_setup_clock - check clock settings and store them in atomic 1813 * state 1814 * @dc: display controller 1815 * @crtc_state: CRTC atomic state 1816 * @clk: parent clock for display controller 1817 * @pclk: pixel clock 1818 * @div: shift clock divider 1819 * 1820 * Returns: 1821 * 0 on success or a negative error-code on failure. 1822 */ 1823 int tegra_dc_state_setup_clock(struct tegra_dc *dc, 1824 struct drm_crtc_state *crtc_state, 1825 struct clk *clk, unsigned long pclk, 1826 unsigned int div) 1827 { 1828 struct tegra_dc_state *state = to_dc_state(crtc_state); 1829 1830 if (!clk_has_parent(dc->clk, clk)) 1831 return -EINVAL; 1832 1833 state->clk = clk; 1834 state->pclk = pclk; 1835 state->div = div; 1836 1837 return 0; 1838 } 1839 1840 static void tegra_dc_update_voltage_state(struct tegra_dc *dc, 1841 struct tegra_dc_state *state) 1842 { 1843 unsigned long rate, pstate; 1844 struct dev_pm_opp *opp; 1845 int err; 1846 1847 if (!dc->has_opp_table) 1848 return; 1849 1850 /* calculate actual pixel clock rate which depends on internal divider */ 1851 rate = DIV_ROUND_UP(clk_get_rate(dc->clk) * 2, state->div + 2); 1852 1853 /* find suitable OPP for the rate */ 1854 opp = dev_pm_opp_find_freq_ceil(dc->dev, &rate); 1855 1856 /* 1857 * Very high resolution modes may results in a clock rate that is 1858 * above the characterized maximum. In this case it's okay to fall 1859 * back to the characterized maximum. 1860 */ 1861 if (opp == ERR_PTR(-ERANGE)) 1862 opp = dev_pm_opp_find_freq_floor(dc->dev, &rate); 1863 1864 if (IS_ERR(opp)) { 1865 dev_err(dc->dev, "failed to find OPP for %luHz: %pe\n", 1866 rate, opp); 1867 return; 1868 } 1869 1870 pstate = dev_pm_opp_get_required_pstate(opp, 0); 1871 dev_pm_opp_put(opp); 1872 1873 /* 1874 * The minimum core voltage depends on the pixel clock rate (which 1875 * depends on internal clock divider of the CRTC) and not on the 1876 * rate of the display controller clock. This is why we're not using 1877 * dev_pm_opp_set_rate() API and instead controlling the power domain 1878 * directly. 1879 */ 1880 err = dev_pm_genpd_set_performance_state(dc->dev, pstate); 1881 if (err) 1882 dev_err(dc->dev, "failed to set power domain state to %lu: %d\n", 1883 pstate, err); 1884 } 1885 1886 static void tegra_dc_set_clock_rate(struct tegra_dc *dc, 1887 struct tegra_dc_state *state) 1888 { 1889 int err; 1890 1891 err = clk_set_parent(dc->clk, state->clk); 1892 if (err < 0) 1893 dev_err(dc->dev, "failed to set parent clock: %d\n", err); 1894 1895 /* 1896 * Outputs may not want to change the parent clock rate. This is only 1897 * relevant to Tegra20 where only a single display PLL is available. 1898 * Since that PLL would typically be used for HDMI, an internal LVDS 1899 * panel would need to be driven by some other clock such as PLL_P 1900 * which is shared with other peripherals. Changing the clock rate 1901 * should therefore be avoided. 1902 */ 1903 if (state->pclk > 0) { 1904 err = clk_set_rate(state->clk, state->pclk); 1905 if (err < 0) 1906 dev_err(dc->dev, 1907 "failed to set clock rate to %lu Hz\n", 1908 state->pclk); 1909 1910 err = clk_set_rate(dc->clk, state->pclk); 1911 if (err < 0) 1912 dev_err(dc->dev, "failed to set clock %pC to %lu Hz: %d\n", 1913 dc->clk, state->pclk, err); 1914 } 1915 1916 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), 1917 state->div); 1918 DRM_DEBUG_KMS("pclk: %lu\n", state->pclk); 1919 1920 tegra_dc_update_voltage_state(dc, state); 1921 } 1922 1923 static void tegra_dc_stop(struct tegra_dc *dc) 1924 { 1925 u32 value; 1926 1927 /* stop the display controller */ 1928 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 1929 value &= ~DISP_CTRL_MODE_MASK; 1930 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 1931 1932 tegra_dc_commit(dc); 1933 } 1934 1935 static bool tegra_dc_idle(struct tegra_dc *dc) 1936 { 1937 u32 value; 1938 1939 value = tegra_dc_readl_active(dc, DC_CMD_DISPLAY_COMMAND); 1940 1941 return (value & DISP_CTRL_MODE_MASK) == 0; 1942 } 1943 1944 static int tegra_dc_wait_idle(struct tegra_dc *dc, unsigned long timeout) 1945 { 1946 timeout = jiffies + msecs_to_jiffies(timeout); 1947 1948 while (time_before(jiffies, timeout)) { 1949 if (tegra_dc_idle(dc)) 1950 return 0; 1951 1952 usleep_range(1000, 2000); 1953 } 1954 1955 dev_dbg(dc->dev, "timeout waiting for DC to become idle\n"); 1956 return -ETIMEDOUT; 1957 } 1958 1959 static void 1960 tegra_crtc_update_memory_bandwidth(struct drm_crtc *crtc, 1961 struct drm_atomic_state *state, 1962 bool prepare_bandwidth_transition) 1963 { 1964 const struct tegra_plane_state *old_tegra_state, *new_tegra_state; 1965 u32 i, new_avg_bw, old_avg_bw, new_peak_bw, old_peak_bw; 1966 const struct drm_plane_state *old_plane_state; 1967 const struct drm_crtc_state *old_crtc_state; 1968 struct tegra_dc_window window, old_window; 1969 struct tegra_dc *dc = to_tegra_dc(crtc); 1970 struct tegra_plane *tegra; 1971 struct drm_plane *plane; 1972 1973 if (dc->soc->has_nvdisplay) 1974 return; 1975 1976 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc); 1977 1978 if (!crtc->state->active) { 1979 if (!old_crtc_state->active) 1980 return; 1981 1982 /* 1983 * When CRTC is disabled on DPMS, the state of attached planes 1984 * is kept unchanged. Hence we need to enforce removal of the 1985 * bandwidths from the ICC paths. 1986 */ 1987 drm_atomic_crtc_for_each_plane(plane, crtc) { 1988 tegra = to_tegra_plane(plane); 1989 1990 icc_set_bw(tegra->icc_mem, 0, 0); 1991 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 1992 } 1993 1994 return; 1995 } 1996 1997 for_each_old_plane_in_state(old_crtc_state->state, plane, 1998 old_plane_state, i) { 1999 old_tegra_state = to_const_tegra_plane_state(old_plane_state); 2000 new_tegra_state = to_const_tegra_plane_state(plane->state); 2001 tegra = to_tegra_plane(plane); 2002 2003 /* 2004 * We're iterating over the global atomic state and it contains 2005 * planes from another CRTC, hence we need to filter out the 2006 * planes unrelated to this CRTC. 2007 */ 2008 if (tegra->dc != dc) 2009 continue; 2010 2011 new_avg_bw = new_tegra_state->avg_memory_bandwidth; 2012 old_avg_bw = old_tegra_state->avg_memory_bandwidth; 2013 2014 new_peak_bw = new_tegra_state->total_peak_memory_bandwidth; 2015 old_peak_bw = old_tegra_state->total_peak_memory_bandwidth; 2016 2017 /* 2018 * See the comment related to !crtc->state->active above, 2019 * which explains why bandwidths need to be updated when 2020 * CRTC is turning ON. 2021 */ 2022 if (new_avg_bw == old_avg_bw && new_peak_bw == old_peak_bw && 2023 old_crtc_state->active) 2024 continue; 2025 2026 window.src.h = drm_rect_height(&plane->state->src) >> 16; 2027 window.dst.h = drm_rect_height(&plane->state->dst); 2028 2029 old_window.src.h = drm_rect_height(&old_plane_state->src) >> 16; 2030 old_window.dst.h = drm_rect_height(&old_plane_state->dst); 2031 2032 /* 2033 * During the preparation phase (atomic_begin), the memory 2034 * freq should go high before the DC changes are committed 2035 * if bandwidth requirement goes up, otherwise memory freq 2036 * should to stay high if BW requirement goes down. The 2037 * opposite applies to the completion phase (post_commit). 2038 */ 2039 if (prepare_bandwidth_transition) { 2040 new_avg_bw = max(old_avg_bw, new_avg_bw); 2041 new_peak_bw = max(old_peak_bw, new_peak_bw); 2042 2043 if (tegra_plane_use_vertical_filtering(tegra, &old_window)) 2044 window = old_window; 2045 } 2046 2047 icc_set_bw(tegra->icc_mem, new_avg_bw, new_peak_bw); 2048 2049 if (tegra_plane_use_vertical_filtering(tegra, &window)) 2050 icc_set_bw(tegra->icc_mem_vfilter, new_avg_bw, new_peak_bw); 2051 else 2052 icc_set_bw(tegra->icc_mem_vfilter, 0, 0); 2053 } 2054 } 2055 2056 static void tegra_crtc_atomic_disable(struct drm_crtc *crtc, 2057 struct drm_atomic_state *state) 2058 { 2059 struct tegra_dc *dc = to_tegra_dc(crtc); 2060 u32 value; 2061 int err; 2062 2063 if (!tegra_dc_idle(dc)) { 2064 tegra_dc_stop(dc); 2065 2066 /* 2067 * Ignore the return value, there isn't anything useful to do 2068 * in case this fails. 2069 */ 2070 tegra_dc_wait_idle(dc, 100); 2071 } 2072 2073 /* 2074 * This should really be part of the RGB encoder driver, but clearing 2075 * these bits has the side-effect of stopping the display controller. 2076 * When that happens no VBLANK interrupts will be raised. At the same 2077 * time the encoder is disabled before the display controller, so the 2078 * above code is always going to timeout waiting for the controller 2079 * to go idle. 2080 * 2081 * Given the close coupling between the RGB encoder and the display 2082 * controller doing it here is still kind of okay. None of the other 2083 * encoder drivers require these bits to be cleared. 2084 * 2085 * XXX: Perhaps given that the display controller is switched off at 2086 * this point anyway maybe clearing these bits isn't even useful for 2087 * the RGB encoder? 2088 */ 2089 if (dc->rgb) { 2090 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2091 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2092 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE); 2093 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2094 } 2095 2096 tegra_dc_stats_reset(&dc->stats); 2097 drm_crtc_vblank_off(crtc); 2098 2099 spin_lock_irq(&crtc->dev->event_lock); 2100 2101 if (crtc->state->event) { 2102 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2103 crtc->state->event = NULL; 2104 } 2105 2106 spin_unlock_irq(&crtc->dev->event_lock); 2107 2108 err = host1x_client_suspend(&dc->client); 2109 if (err < 0) 2110 dev_err(dc->dev, "failed to suspend: %d\n", err); 2111 2112 if (dc->has_opp_table) { 2113 err = dev_pm_genpd_set_performance_state(dc->dev, 0); 2114 if (err) 2115 dev_err(dc->dev, 2116 "failed to clear power domain state: %d\n", err); 2117 } 2118 } 2119 2120 static void tegra_crtc_atomic_enable(struct drm_crtc *crtc, 2121 struct drm_atomic_state *state) 2122 { 2123 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 2124 struct tegra_dc_state *crtc_state = to_dc_state(crtc->state); 2125 struct tegra_dc *dc = to_tegra_dc(crtc); 2126 u32 value; 2127 int err; 2128 2129 /* apply PLL changes */ 2130 tegra_dc_set_clock_rate(dc, crtc_state); 2131 2132 err = host1x_client_resume(&dc->client); 2133 if (err < 0) { 2134 dev_err(dc->dev, "failed to resume: %d\n", err); 2135 return; 2136 } 2137 2138 /* initialize display controller */ 2139 if (dc->syncpt) { 2140 u32 syncpt = host1x_syncpt_id(dc->syncpt), enable; 2141 2142 if (dc->soc->has_nvdisplay) 2143 enable = 1 << 31; 2144 else 2145 enable = 1 << 8; 2146 2147 value = SYNCPT_CNTRL_NO_STALL; 2148 tegra_dc_writel(dc, value, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL); 2149 2150 value = enable | syncpt; 2151 tegra_dc_writel(dc, value, DC_CMD_CONT_SYNCPT_VSYNC); 2152 } 2153 2154 if (dc->soc->has_nvdisplay) { 2155 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2156 DSC_OBUF_UF_INT; 2157 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2158 2159 value = DSC_TO_UF_INT | DSC_BBUF_UF_INT | DSC_RBUF_UF_INT | 2160 DSC_OBUF_UF_INT | SD3_BUCKET_WALK_DONE_INT | 2161 HEAD_UF_INT | MSF_INT | REG_TMOUT_INT | 2162 REGION_CRC_INT | V_PULSE2_INT | V_PULSE3_INT | 2163 VBLANK_INT | FRAME_END_INT; 2164 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2165 2166 value = SD3_BUCKET_WALK_DONE_INT | HEAD_UF_INT | VBLANK_INT | 2167 FRAME_END_INT; 2168 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2169 2170 value = HEAD_UF_INT | REG_TMOUT_INT | FRAME_END_INT; 2171 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2172 2173 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS); 2174 } else { 2175 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2176 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2177 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE); 2178 2179 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2180 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2181 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY); 2182 2183 /* initialize timer */ 2184 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) | 2185 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20); 2186 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY); 2187 2188 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) | 2189 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1); 2190 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER); 2191 2192 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2193 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2194 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE); 2195 2196 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | 2197 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT; 2198 tegra_dc_writel(dc, value, DC_CMD_INT_MASK); 2199 } 2200 2201 if (dc->soc->supports_background_color) 2202 tegra_dc_writel(dc, 0, DC_DISP_BLEND_BACKGROUND_COLOR); 2203 else 2204 tegra_dc_writel(dc, 0, DC_DISP_BORDER_COLOR); 2205 2206 /* apply pixel clock changes */ 2207 if (!dc->soc->has_nvdisplay) { 2208 value = SHIFT_CLK_DIVIDER(crtc_state->div) | PIXEL_CLK_DIVIDER_PCD1; 2209 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL); 2210 } 2211 2212 /* program display mode */ 2213 tegra_dc_set_timings(dc, mode); 2214 2215 /* interlacing isn't supported yet, so disable it */ 2216 if (dc->soc->supports_interlacing) { 2217 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL); 2218 value &= ~INTERLACE_ENABLE; 2219 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL); 2220 } 2221 2222 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND); 2223 value &= ~DISP_CTRL_MODE_MASK; 2224 value |= DISP_CTRL_MODE_C_DISPLAY; 2225 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND); 2226 2227 if (!dc->soc->has_nvdisplay) { 2228 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL); 2229 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE | 2230 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE; 2231 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL); 2232 } 2233 2234 /* enable underflow reporting and display red for missing pixels */ 2235 if (dc->soc->has_nvdisplay) { 2236 value = UNDERFLOW_MODE_RED | UNDERFLOW_REPORT_ENABLE; 2237 tegra_dc_writel(dc, value, DC_COM_RG_UNDERFLOW); 2238 } 2239 2240 if (dc->rgb) { 2241 /* XXX: parameterize? */ 2242 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE; 2243 tegra_dc_writel(dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS); 2244 } 2245 2246 tegra_dc_commit(dc); 2247 2248 drm_crtc_vblank_on(crtc); 2249 } 2250 2251 static void tegra_crtc_atomic_begin(struct drm_crtc *crtc, 2252 struct drm_atomic_state *state) 2253 { 2254 unsigned long flags; 2255 2256 tegra_crtc_update_memory_bandwidth(crtc, state, true); 2257 2258 if (crtc->state->event) { 2259 spin_lock_irqsave(&crtc->dev->event_lock, flags); 2260 2261 if (drm_crtc_vblank_get(crtc) != 0) 2262 drm_crtc_send_vblank_event(crtc, crtc->state->event); 2263 else 2264 drm_crtc_arm_vblank_event(crtc, crtc->state->event); 2265 2266 spin_unlock_irqrestore(&crtc->dev->event_lock, flags); 2267 2268 crtc->state->event = NULL; 2269 } 2270 } 2271 2272 static void tegra_crtc_atomic_flush(struct drm_crtc *crtc, 2273 struct drm_atomic_state *state) 2274 { 2275 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, 2276 crtc); 2277 struct tegra_dc_state *dc_state = to_dc_state(crtc_state); 2278 struct tegra_dc *dc = to_tegra_dc(crtc); 2279 u32 value; 2280 2281 value = dc_state->planes << 8 | GENERAL_UPDATE; 2282 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2283 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2284 2285 value = dc_state->planes | GENERAL_ACT_REQ; 2286 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL); 2287 value = tegra_dc_readl(dc, DC_CMD_STATE_CONTROL); 2288 } 2289 2290 static bool tegra_plane_is_cursor(const struct drm_plane_state *state) 2291 { 2292 const struct tegra_dc_soc_info *soc = to_tegra_dc(state->crtc)->soc; 2293 const struct drm_format_info *fmt = state->fb->format; 2294 unsigned int src_w = drm_rect_width(&state->src) >> 16; 2295 unsigned int dst_w = drm_rect_width(&state->dst); 2296 2297 if (state->plane->type != DRM_PLANE_TYPE_CURSOR) 2298 return false; 2299 2300 if (soc->supports_cursor) 2301 return true; 2302 2303 if (src_w != dst_w || fmt->num_planes != 1 || src_w * fmt->cpp[0] > 256) 2304 return false; 2305 2306 return true; 2307 } 2308 2309 static unsigned long 2310 tegra_plane_overlap_mask(struct drm_crtc_state *state, 2311 const struct drm_plane_state *plane_state) 2312 { 2313 const struct drm_plane_state *other_state; 2314 const struct tegra_plane *tegra; 2315 unsigned long overlap_mask = 0; 2316 struct drm_plane *plane; 2317 struct drm_rect rect; 2318 2319 if (!plane_state->visible || !plane_state->fb) 2320 return 0; 2321 2322 /* 2323 * Data-prefetch FIFO will easily help to overcome temporal memory 2324 * pressure if other plane overlaps with the cursor plane. 2325 */ 2326 if (tegra_plane_is_cursor(plane_state)) 2327 return 0; 2328 2329 drm_atomic_crtc_state_for_each_plane_state(plane, other_state, state) { 2330 rect = plane_state->dst; 2331 2332 tegra = to_tegra_plane(other_state->plane); 2333 2334 if (!other_state->visible || !other_state->fb) 2335 continue; 2336 2337 /* 2338 * Ignore cursor plane overlaps because it's not practical to 2339 * assume that it contributes to the bandwidth in overlapping 2340 * area if window width is small. 2341 */ 2342 if (tegra_plane_is_cursor(other_state)) 2343 continue; 2344 2345 if (drm_rect_intersect(&rect, &other_state->dst)) 2346 overlap_mask |= BIT(tegra->index); 2347 } 2348 2349 return overlap_mask; 2350 } 2351 2352 static int tegra_crtc_calculate_memory_bandwidth(struct drm_crtc *crtc, 2353 struct drm_atomic_state *state) 2354 { 2355 ulong overlap_mask[TEGRA_DC_LEGACY_PLANES_NUM] = {}, mask; 2356 u32 plane_peak_bw[TEGRA_DC_LEGACY_PLANES_NUM] = {}; 2357 bool all_planes_overlap_simultaneously = true; 2358 const struct tegra_plane_state *tegra_state; 2359 const struct drm_plane_state *plane_state; 2360 struct tegra_dc *dc = to_tegra_dc(crtc); 2361 const struct drm_crtc_state *old_state; 2362 struct drm_crtc_state *new_state; 2363 struct tegra_plane *tegra; 2364 struct drm_plane *plane; 2365 2366 /* 2367 * The nv-display uses shared planes. The algorithm below assumes 2368 * maximum 3 planes per-CRTC, this assumption isn't applicable to 2369 * the nv-display. Note that T124 support has additional windows, 2370 * but currently they aren't supported by the driver. 2371 */ 2372 if (dc->soc->has_nvdisplay) 2373 return 0; 2374 2375 new_state = drm_atomic_get_new_crtc_state(state, crtc); 2376 old_state = drm_atomic_get_old_crtc_state(state, crtc); 2377 2378 /* 2379 * For overlapping planes pixel's data is fetched for each plane at 2380 * the same time, hence bandwidths are accumulated in this case. 2381 * This needs to be taken into account for calculating total bandwidth 2382 * consumed by all planes. 2383 * 2384 * Here we get the overlapping state of each plane, which is a 2385 * bitmask of plane indices telling with what planes there is an 2386 * overlap. Note that bitmask[plane] includes BIT(plane) in order 2387 * to make further code nicer and simpler. 2388 */ 2389 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2390 tegra_state = to_const_tegra_plane_state(plane_state); 2391 tegra = to_tegra_plane(plane); 2392 2393 if (WARN_ON_ONCE(tegra->index >= TEGRA_DC_LEGACY_PLANES_NUM)) 2394 return -EINVAL; 2395 2396 plane_peak_bw[tegra->index] = tegra_state->peak_memory_bandwidth; 2397 mask = tegra_plane_overlap_mask(new_state, plane_state); 2398 overlap_mask[tegra->index] = mask; 2399 2400 if (hweight_long(mask) != 3) 2401 all_planes_overlap_simultaneously = false; 2402 } 2403 2404 /* 2405 * Then we calculate maximum bandwidth of each plane state. 2406 * The bandwidth includes the plane BW + BW of the "simultaneously" 2407 * overlapping planes, where "simultaneously" means areas where DC 2408 * fetches from the planes simultaneously during of scan-out process. 2409 * 2410 * For example, if plane A overlaps with planes B and C, but B and C 2411 * don't overlap, then the peak bandwidth will be either in area where 2412 * A-and-B or A-and-C planes overlap. 2413 * 2414 * The plane_peak_bw[] contains peak memory bandwidth values of 2415 * each plane, this information is needed by interconnect provider 2416 * in order to set up latency allowance based on the peak BW, see 2417 * tegra_crtc_update_memory_bandwidth(). 2418 */ 2419 drm_atomic_crtc_state_for_each_plane_state(plane, plane_state, new_state) { 2420 u32 i, old_peak_bw, new_peak_bw, overlap_bw = 0; 2421 2422 /* 2423 * Note that plane's atomic check doesn't touch the 2424 * total_peak_memory_bandwidth of enabled plane, hence the 2425 * current state contains the old bandwidth state from the 2426 * previous CRTC commit. 2427 */ 2428 tegra_state = to_const_tegra_plane_state(plane_state); 2429 tegra = to_tegra_plane(plane); 2430 2431 for_each_set_bit(i, &overlap_mask[tegra->index], 3) { 2432 if (i == tegra->index) 2433 continue; 2434 2435 if (all_planes_overlap_simultaneously) 2436 overlap_bw += plane_peak_bw[i]; 2437 else 2438 overlap_bw = max(overlap_bw, plane_peak_bw[i]); 2439 } 2440 2441 new_peak_bw = plane_peak_bw[tegra->index] + overlap_bw; 2442 old_peak_bw = tegra_state->total_peak_memory_bandwidth; 2443 2444 /* 2445 * If plane's peak bandwidth changed (for example plane isn't 2446 * overlapped anymore) and plane isn't in the atomic state, 2447 * then add plane to the state in order to have the bandwidth 2448 * updated. 2449 */ 2450 if (old_peak_bw != new_peak_bw) { 2451 struct tegra_plane_state *new_tegra_state; 2452 struct drm_plane_state *new_plane_state; 2453 2454 new_plane_state = drm_atomic_get_plane_state(state, plane); 2455 if (IS_ERR(new_plane_state)) 2456 return PTR_ERR(new_plane_state); 2457 2458 new_tegra_state = to_tegra_plane_state(new_plane_state); 2459 new_tegra_state->total_peak_memory_bandwidth = new_peak_bw; 2460 } 2461 } 2462 2463 return 0; 2464 } 2465 2466 static int tegra_crtc_atomic_check(struct drm_crtc *crtc, 2467 struct drm_atomic_state *state) 2468 { 2469 int err; 2470 2471 err = tegra_crtc_calculate_memory_bandwidth(crtc, state); 2472 if (err) 2473 return err; 2474 2475 return 0; 2476 } 2477 2478 void tegra_crtc_atomic_post_commit(struct drm_crtc *crtc, 2479 struct drm_atomic_state *state) 2480 { 2481 /* 2482 * Display bandwidth is allowed to go down only once hardware state 2483 * is known to be armed, i.e. state was committed and VBLANK event 2484 * received. 2485 */ 2486 tegra_crtc_update_memory_bandwidth(crtc, state, false); 2487 } 2488 2489 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = { 2490 .atomic_check = tegra_crtc_atomic_check, 2491 .atomic_begin = tegra_crtc_atomic_begin, 2492 .atomic_flush = tegra_crtc_atomic_flush, 2493 .atomic_enable = tegra_crtc_atomic_enable, 2494 .atomic_disable = tegra_crtc_atomic_disable, 2495 }; 2496 2497 static irqreturn_t tegra_dc_irq(int irq, void *data) 2498 { 2499 struct tegra_dc *dc = data; 2500 unsigned long status; 2501 2502 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS); 2503 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS); 2504 2505 if (status & FRAME_END_INT) { 2506 /* 2507 dev_dbg(dc->dev, "%s(): frame end\n", __func__); 2508 */ 2509 dc->stats.frames_total++; 2510 dc->stats.frames++; 2511 } 2512 2513 if (status & VBLANK_INT) { 2514 /* 2515 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__); 2516 */ 2517 drm_crtc_handle_vblank(&dc->base); 2518 dc->stats.vblank_total++; 2519 dc->stats.vblank++; 2520 } 2521 2522 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) { 2523 /* 2524 dev_dbg(dc->dev, "%s(): underflow\n", __func__); 2525 */ 2526 dc->stats.underflow_total++; 2527 dc->stats.underflow++; 2528 } 2529 2530 if (status & (WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT)) { 2531 /* 2532 dev_dbg(dc->dev, "%s(): overflow\n", __func__); 2533 */ 2534 dc->stats.overflow_total++; 2535 dc->stats.overflow++; 2536 } 2537 2538 if (status & HEAD_UF_INT) { 2539 dev_dbg_ratelimited(dc->dev, "%s(): head underflow\n", __func__); 2540 dc->stats.underflow_total++; 2541 dc->stats.underflow++; 2542 } 2543 2544 return IRQ_HANDLED; 2545 } 2546 2547 static bool tegra_dc_has_window_groups(struct tegra_dc *dc) 2548 { 2549 unsigned int i; 2550 2551 if (!dc->soc->wgrps) 2552 return true; 2553 2554 for (i = 0; i < dc->soc->num_wgrps; i++) { 2555 const struct tegra_windowgroup_soc *wgrp = &dc->soc->wgrps[i]; 2556 2557 if (wgrp->dc == dc->pipe && wgrp->num_windows > 0) 2558 return true; 2559 } 2560 2561 return false; 2562 } 2563 2564 static int tegra_dc_early_init(struct host1x_client *client) 2565 { 2566 struct drm_device *drm = dev_get_drvdata(client->host); 2567 struct tegra_drm *tegra = drm->dev_private; 2568 2569 tegra->num_crtcs++; 2570 2571 return 0; 2572 } 2573 2574 static int tegra_dc_init(struct host1x_client *client) 2575 { 2576 struct drm_device *drm = dev_get_drvdata(client->host); 2577 unsigned long flags = HOST1X_SYNCPT_CLIENT_MANAGED; 2578 struct tegra_dc *dc = host1x_client_to_dc(client); 2579 struct tegra_drm *tegra = drm->dev_private; 2580 struct drm_plane *primary = NULL; 2581 struct drm_plane *cursor = NULL; 2582 int err; 2583 2584 /* 2585 * DC has been reset by now, so VBLANK syncpoint can be released 2586 * for general use. 2587 */ 2588 host1x_syncpt_release_vblank_reservation(client, 26 + dc->pipe); 2589 2590 /* 2591 * XXX do not register DCs with no window groups because we cannot 2592 * assign a primary plane to them, which in turn will cause KMS to 2593 * crash. 2594 */ 2595 if (!tegra_dc_has_window_groups(dc)) 2596 return 0; 2597 2598 /* 2599 * Set the display hub as the host1x client parent for the display 2600 * controller. This is needed for the runtime reference counting that 2601 * ensures the display hub is always powered when any of the display 2602 * controllers are. 2603 */ 2604 if (dc->soc->has_nvdisplay) 2605 client->parent = &tegra->hub->client; 2606 2607 dc->syncpt = host1x_syncpt_request(client, flags); 2608 if (!dc->syncpt) 2609 dev_warn(dc->dev, "failed to allocate syncpoint\n"); 2610 2611 err = host1x_client_iommu_attach(client); 2612 if (err < 0 && err != -ENODEV) { 2613 dev_err(client->dev, "failed to attach to domain: %d\n", err); 2614 return err; 2615 } 2616 2617 if (dc->soc->wgrps) 2618 primary = tegra_dc_add_shared_planes(drm, dc); 2619 else 2620 primary = tegra_dc_add_planes(drm, dc); 2621 2622 if (IS_ERR(primary)) { 2623 err = PTR_ERR(primary); 2624 goto cleanup; 2625 } 2626 2627 if (dc->soc->supports_cursor) { 2628 cursor = tegra_dc_cursor_plane_create(drm, dc); 2629 if (IS_ERR(cursor)) { 2630 err = PTR_ERR(cursor); 2631 goto cleanup; 2632 } 2633 } else { 2634 /* dedicate one overlay to mouse cursor */ 2635 cursor = tegra_dc_overlay_plane_create(drm, dc, 2, true); 2636 if (IS_ERR(cursor)) { 2637 err = PTR_ERR(cursor); 2638 goto cleanup; 2639 } 2640 } 2641 2642 err = drm_crtc_init_with_planes(drm, &dc->base, primary, cursor, 2643 &tegra_crtc_funcs, NULL); 2644 if (err < 0) 2645 goto cleanup; 2646 2647 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs); 2648 2649 /* 2650 * Keep track of the minimum pitch alignment across all display 2651 * controllers. 2652 */ 2653 if (dc->soc->pitch_align > tegra->pitch_align) 2654 tegra->pitch_align = dc->soc->pitch_align; 2655 2656 /* track maximum resolution */ 2657 if (dc->soc->has_nvdisplay) 2658 drm->mode_config.max_width = drm->mode_config.max_height = 16384; 2659 else 2660 drm->mode_config.max_width = drm->mode_config.max_height = 4096; 2661 2662 err = tegra_dc_rgb_init(drm, dc); 2663 if (err < 0 && err != -ENODEV) { 2664 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err); 2665 goto cleanup; 2666 } 2667 2668 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0, 2669 dev_name(dc->dev), dc); 2670 if (err < 0) { 2671 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq, 2672 err); 2673 goto cleanup; 2674 } 2675 2676 /* 2677 * Inherit the DMA parameters (such as maximum segment size) from the 2678 * parent host1x device. 2679 */ 2680 client->dev->dma_parms = client->host->dma_parms; 2681 2682 return 0; 2683 2684 cleanup: 2685 if (!IS_ERR_OR_NULL(cursor)) 2686 drm_plane_cleanup(cursor); 2687 2688 if (!IS_ERR(primary)) 2689 drm_plane_cleanup(primary); 2690 2691 host1x_client_iommu_detach(client); 2692 host1x_syncpt_put(dc->syncpt); 2693 2694 return err; 2695 } 2696 2697 static int tegra_dc_exit(struct host1x_client *client) 2698 { 2699 struct tegra_dc *dc = host1x_client_to_dc(client); 2700 int err; 2701 2702 if (!tegra_dc_has_window_groups(dc)) 2703 return 0; 2704 2705 /* avoid a dangling pointer just in case this disappears */ 2706 client->dev->dma_parms = NULL; 2707 2708 devm_free_irq(dc->dev, dc->irq, dc); 2709 2710 err = tegra_dc_rgb_exit(dc); 2711 if (err) { 2712 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err); 2713 return err; 2714 } 2715 2716 host1x_client_iommu_detach(client); 2717 host1x_syncpt_put(dc->syncpt); 2718 2719 return 0; 2720 } 2721 2722 static int tegra_dc_late_exit(struct host1x_client *client) 2723 { 2724 struct drm_device *drm = dev_get_drvdata(client->host); 2725 struct tegra_drm *tegra = drm->dev_private; 2726 2727 tegra->num_crtcs--; 2728 2729 return 0; 2730 } 2731 2732 static int tegra_dc_runtime_suspend(struct host1x_client *client) 2733 { 2734 struct tegra_dc *dc = host1x_client_to_dc(client); 2735 struct device *dev = client->dev; 2736 int err; 2737 2738 err = reset_control_assert(dc->rst); 2739 if (err < 0) { 2740 dev_err(dev, "failed to assert reset: %d\n", err); 2741 return err; 2742 } 2743 2744 if (dc->soc->has_powergate) 2745 tegra_powergate_power_off(dc->powergate); 2746 2747 clk_disable_unprepare(dc->clk); 2748 pm_runtime_put_sync(dev); 2749 2750 return 0; 2751 } 2752 2753 static int tegra_dc_runtime_resume(struct host1x_client *client) 2754 { 2755 struct tegra_dc *dc = host1x_client_to_dc(client); 2756 struct device *dev = client->dev; 2757 int err; 2758 2759 err = pm_runtime_resume_and_get(dev); 2760 if (err < 0) { 2761 dev_err(dev, "failed to get runtime PM: %d\n", err); 2762 return err; 2763 } 2764 2765 if (dc->soc->has_powergate) { 2766 err = tegra_powergate_sequence_power_up(dc->powergate, dc->clk, 2767 dc->rst); 2768 if (err < 0) { 2769 dev_err(dev, "failed to power partition: %d\n", err); 2770 goto put_rpm; 2771 } 2772 } else { 2773 err = clk_prepare_enable(dc->clk); 2774 if (err < 0) { 2775 dev_err(dev, "failed to enable clock: %d\n", err); 2776 goto put_rpm; 2777 } 2778 2779 err = reset_control_deassert(dc->rst); 2780 if (err < 0) { 2781 dev_err(dev, "failed to deassert reset: %d\n", err); 2782 goto disable_clk; 2783 } 2784 } 2785 2786 return 0; 2787 2788 disable_clk: 2789 clk_disable_unprepare(dc->clk); 2790 put_rpm: 2791 pm_runtime_put_sync(dev); 2792 return err; 2793 } 2794 2795 static const struct host1x_client_ops dc_client_ops = { 2796 .early_init = tegra_dc_early_init, 2797 .init = tegra_dc_init, 2798 .exit = tegra_dc_exit, 2799 .late_exit = tegra_dc_late_exit, 2800 .suspend = tegra_dc_runtime_suspend, 2801 .resume = tegra_dc_runtime_resume, 2802 }; 2803 2804 static const struct tegra_dc_soc_info tegra20_dc_soc_info = { 2805 .supports_background_color = false, 2806 .supports_interlacing = false, 2807 .supports_cursor = false, 2808 .supports_block_linear = false, 2809 .supports_sector_layout = false, 2810 .has_legacy_blending = true, 2811 .pitch_align = 8, 2812 .has_powergate = false, 2813 .coupled_pm = true, 2814 .has_nvdisplay = false, 2815 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2816 .primary_formats = tegra20_primary_formats, 2817 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2818 .overlay_formats = tegra20_overlay_formats, 2819 .modifiers = tegra20_modifiers, 2820 .has_win_a_without_filters = true, 2821 .has_win_b_vfilter_mem_client = true, 2822 .has_win_c_without_vert_filter = true, 2823 .plane_tiled_memory_bandwidth_x2 = false, 2824 .has_pll_d2_out0 = false, 2825 }; 2826 2827 static const struct tegra_dc_soc_info tegra30_dc_soc_info = { 2828 .supports_background_color = false, 2829 .supports_interlacing = false, 2830 .supports_cursor = false, 2831 .supports_block_linear = false, 2832 .supports_sector_layout = false, 2833 .has_legacy_blending = true, 2834 .pitch_align = 8, 2835 .has_powergate = false, 2836 .coupled_pm = false, 2837 .has_nvdisplay = false, 2838 .num_primary_formats = ARRAY_SIZE(tegra20_primary_formats), 2839 .primary_formats = tegra20_primary_formats, 2840 .num_overlay_formats = ARRAY_SIZE(tegra20_overlay_formats), 2841 .overlay_formats = tegra20_overlay_formats, 2842 .modifiers = tegra20_modifiers, 2843 .has_win_a_without_filters = false, 2844 .has_win_b_vfilter_mem_client = true, 2845 .has_win_c_without_vert_filter = false, 2846 .plane_tiled_memory_bandwidth_x2 = true, 2847 .has_pll_d2_out0 = true, 2848 }; 2849 2850 static const struct tegra_dc_soc_info tegra114_dc_soc_info = { 2851 .supports_background_color = false, 2852 .supports_interlacing = false, 2853 .supports_cursor = false, 2854 .supports_block_linear = false, 2855 .supports_sector_layout = false, 2856 .has_legacy_blending = true, 2857 .pitch_align = 64, 2858 .has_powergate = true, 2859 .coupled_pm = false, 2860 .has_nvdisplay = false, 2861 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2862 .primary_formats = tegra114_primary_formats, 2863 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2864 .overlay_formats = tegra114_overlay_formats, 2865 .modifiers = tegra20_modifiers, 2866 .has_win_a_without_filters = false, 2867 .has_win_b_vfilter_mem_client = false, 2868 .has_win_c_without_vert_filter = false, 2869 .plane_tiled_memory_bandwidth_x2 = true, 2870 .has_pll_d2_out0 = true, 2871 }; 2872 2873 static const struct tegra_dc_soc_info tegra124_dc_soc_info = { 2874 .supports_background_color = true, 2875 .supports_interlacing = true, 2876 .supports_cursor = true, 2877 .supports_block_linear = true, 2878 .supports_sector_layout = false, 2879 .has_legacy_blending = false, 2880 .pitch_align = 64, 2881 .has_powergate = true, 2882 .coupled_pm = false, 2883 .has_nvdisplay = false, 2884 .num_primary_formats = ARRAY_SIZE(tegra124_primary_formats), 2885 .primary_formats = tegra124_primary_formats, 2886 .num_overlay_formats = ARRAY_SIZE(tegra124_overlay_formats), 2887 .overlay_formats = tegra124_overlay_formats, 2888 .modifiers = tegra124_modifiers, 2889 .has_win_a_without_filters = false, 2890 .has_win_b_vfilter_mem_client = false, 2891 .has_win_c_without_vert_filter = false, 2892 .plane_tiled_memory_bandwidth_x2 = false, 2893 .has_pll_d2_out0 = true, 2894 }; 2895 2896 static const struct tegra_dc_soc_info tegra210_dc_soc_info = { 2897 .supports_background_color = true, 2898 .supports_interlacing = true, 2899 .supports_cursor = true, 2900 .supports_block_linear = true, 2901 .supports_sector_layout = false, 2902 .has_legacy_blending = false, 2903 .pitch_align = 64, 2904 .has_powergate = true, 2905 .coupled_pm = false, 2906 .has_nvdisplay = false, 2907 .num_primary_formats = ARRAY_SIZE(tegra114_primary_formats), 2908 .primary_formats = tegra114_primary_formats, 2909 .num_overlay_formats = ARRAY_SIZE(tegra114_overlay_formats), 2910 .overlay_formats = tegra114_overlay_formats, 2911 .modifiers = tegra124_modifiers, 2912 .has_win_a_without_filters = false, 2913 .has_win_b_vfilter_mem_client = false, 2914 .has_win_c_without_vert_filter = false, 2915 .plane_tiled_memory_bandwidth_x2 = false, 2916 .has_pll_d2_out0 = true, 2917 }; 2918 2919 static const struct tegra_windowgroup_soc tegra186_dc_wgrps[] = { 2920 { 2921 .index = 0, 2922 .dc = 0, 2923 .windows = (const unsigned int[]) { 0 }, 2924 .num_windows = 1, 2925 }, { 2926 .index = 1, 2927 .dc = 1, 2928 .windows = (const unsigned int[]) { 1 }, 2929 .num_windows = 1, 2930 }, { 2931 .index = 2, 2932 .dc = 1, 2933 .windows = (const unsigned int[]) { 2 }, 2934 .num_windows = 1, 2935 }, { 2936 .index = 3, 2937 .dc = 2, 2938 .windows = (const unsigned int[]) { 3 }, 2939 .num_windows = 1, 2940 }, { 2941 .index = 4, 2942 .dc = 2, 2943 .windows = (const unsigned int[]) { 4 }, 2944 .num_windows = 1, 2945 }, { 2946 .index = 5, 2947 .dc = 2, 2948 .windows = (const unsigned int[]) { 5 }, 2949 .num_windows = 1, 2950 }, 2951 }; 2952 2953 static const struct tegra_dc_soc_info tegra186_dc_soc_info = { 2954 .supports_background_color = true, 2955 .supports_interlacing = true, 2956 .supports_cursor = true, 2957 .supports_block_linear = true, 2958 .supports_sector_layout = false, 2959 .has_legacy_blending = false, 2960 .pitch_align = 64, 2961 .has_powergate = false, 2962 .coupled_pm = false, 2963 .has_nvdisplay = true, 2964 .wgrps = tegra186_dc_wgrps, 2965 .num_wgrps = ARRAY_SIZE(tegra186_dc_wgrps), 2966 .plane_tiled_memory_bandwidth_x2 = false, 2967 .has_pll_d2_out0 = false, 2968 }; 2969 2970 static const struct tegra_windowgroup_soc tegra194_dc_wgrps[] = { 2971 { 2972 .index = 0, 2973 .dc = 0, 2974 .windows = (const unsigned int[]) { 0 }, 2975 .num_windows = 1, 2976 }, { 2977 .index = 1, 2978 .dc = 1, 2979 .windows = (const unsigned int[]) { 1 }, 2980 .num_windows = 1, 2981 }, { 2982 .index = 2, 2983 .dc = 1, 2984 .windows = (const unsigned int[]) { 2 }, 2985 .num_windows = 1, 2986 }, { 2987 .index = 3, 2988 .dc = 2, 2989 .windows = (const unsigned int[]) { 3 }, 2990 .num_windows = 1, 2991 }, { 2992 .index = 4, 2993 .dc = 2, 2994 .windows = (const unsigned int[]) { 4 }, 2995 .num_windows = 1, 2996 }, { 2997 .index = 5, 2998 .dc = 2, 2999 .windows = (const unsigned int[]) { 5 }, 3000 .num_windows = 1, 3001 }, 3002 }; 3003 3004 static const struct tegra_dc_soc_info tegra194_dc_soc_info = { 3005 .supports_background_color = true, 3006 .supports_interlacing = true, 3007 .supports_cursor = true, 3008 .supports_block_linear = true, 3009 .supports_sector_layout = true, 3010 .has_legacy_blending = false, 3011 .pitch_align = 64, 3012 .has_powergate = false, 3013 .coupled_pm = false, 3014 .has_nvdisplay = true, 3015 .wgrps = tegra194_dc_wgrps, 3016 .num_wgrps = ARRAY_SIZE(tegra194_dc_wgrps), 3017 .plane_tiled_memory_bandwidth_x2 = false, 3018 .has_pll_d2_out0 = false, 3019 }; 3020 3021 static const struct of_device_id tegra_dc_of_match[] = { 3022 { 3023 .compatible = "nvidia,tegra194-dc", 3024 .data = &tegra194_dc_soc_info, 3025 }, { 3026 .compatible = "nvidia,tegra186-dc", 3027 .data = &tegra186_dc_soc_info, 3028 }, { 3029 .compatible = "nvidia,tegra210-dc", 3030 .data = &tegra210_dc_soc_info, 3031 }, { 3032 .compatible = "nvidia,tegra124-dc", 3033 .data = &tegra124_dc_soc_info, 3034 }, { 3035 .compatible = "nvidia,tegra114-dc", 3036 .data = &tegra114_dc_soc_info, 3037 }, { 3038 .compatible = "nvidia,tegra30-dc", 3039 .data = &tegra30_dc_soc_info, 3040 }, { 3041 .compatible = "nvidia,tegra20-dc", 3042 .data = &tegra20_dc_soc_info, 3043 }, { 3044 /* sentinel */ 3045 } 3046 }; 3047 MODULE_DEVICE_TABLE(of, tegra_dc_of_match); 3048 3049 static int tegra_dc_parse_dt(struct tegra_dc *dc) 3050 { 3051 struct device_node *np; 3052 u32 value = 0; 3053 int err; 3054 3055 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value); 3056 if (err < 0) { 3057 dev_err(dc->dev, "missing \"nvidia,head\" property\n"); 3058 3059 /* 3060 * If the nvidia,head property isn't present, try to find the 3061 * correct head number by looking up the position of this 3062 * display controller's node within the device tree. Assuming 3063 * that the nodes are ordered properly in the DTS file and 3064 * that the translation into a flattened device tree blob 3065 * preserves that ordering this will actually yield the right 3066 * head number. 3067 * 3068 * If those assumptions don't hold, this will still work for 3069 * cases where only a single display controller is used. 3070 */ 3071 for_each_matching_node(np, tegra_dc_of_match) { 3072 if (np == dc->dev->of_node) { 3073 of_node_put(np); 3074 break; 3075 } 3076 3077 value++; 3078 } 3079 } 3080 3081 dc->pipe = value; 3082 3083 return 0; 3084 } 3085 3086 static int tegra_dc_match_by_pipe(struct device *dev, const void *data) 3087 { 3088 struct tegra_dc *dc = dev_get_drvdata(dev); 3089 unsigned int pipe = (unsigned long)(void *)data; 3090 3091 return dc->pipe == pipe; 3092 } 3093 3094 static int tegra_dc_couple(struct tegra_dc *dc) 3095 { 3096 /* 3097 * On Tegra20, DC1 requires DC0 to be taken out of reset in order to 3098 * be enabled, otherwise CPU hangs on writing to CMD_DISPLAY_COMMAND / 3099 * POWER_CONTROL registers during CRTC enabling. 3100 */ 3101 if (dc->soc->coupled_pm && dc->pipe == 1) { 3102 struct device *companion; 3103 struct tegra_dc *parent; 3104 3105 companion = driver_find_device(dc->dev->driver, NULL, (const void *)0, 3106 tegra_dc_match_by_pipe); 3107 if (!companion) 3108 return -EPROBE_DEFER; 3109 3110 parent = dev_get_drvdata(companion); 3111 dc->client.parent = &parent->client; 3112 3113 dev_dbg(dc->dev, "coupled to %s\n", dev_name(companion)); 3114 } 3115 3116 return 0; 3117 } 3118 3119 static int tegra_dc_init_opp_table(struct tegra_dc *dc) 3120 { 3121 struct tegra_core_opp_params opp_params = {}; 3122 int err; 3123 3124 err = devm_tegra_core_dev_init_opp_table(dc->dev, &opp_params); 3125 if (err && err != -ENODEV) 3126 return err; 3127 3128 if (err) 3129 dc->has_opp_table = false; 3130 else 3131 dc->has_opp_table = true; 3132 3133 return 0; 3134 } 3135 3136 static int tegra_dc_probe(struct platform_device *pdev) 3137 { 3138 u64 dma_mask = dma_get_mask(pdev->dev.parent); 3139 struct tegra_dc *dc; 3140 int err; 3141 3142 err = dma_coerce_mask_and_coherent(&pdev->dev, dma_mask); 3143 if (err < 0) { 3144 dev_err(&pdev->dev, "failed to set DMA mask: %d\n", err); 3145 return err; 3146 } 3147 3148 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL); 3149 if (!dc) 3150 return -ENOMEM; 3151 3152 dc->soc = of_device_get_match_data(&pdev->dev); 3153 3154 INIT_LIST_HEAD(&dc->list); 3155 dc->dev = &pdev->dev; 3156 3157 err = tegra_dc_parse_dt(dc); 3158 if (err < 0) 3159 return err; 3160 3161 err = tegra_dc_couple(dc); 3162 if (err < 0) 3163 return err; 3164 3165 dc->clk = devm_clk_get(&pdev->dev, NULL); 3166 if (IS_ERR(dc->clk)) { 3167 dev_err(&pdev->dev, "failed to get clock\n"); 3168 return PTR_ERR(dc->clk); 3169 } 3170 3171 dc->rst = devm_reset_control_get(&pdev->dev, "dc"); 3172 if (IS_ERR(dc->rst)) { 3173 dev_err(&pdev->dev, "failed to get reset\n"); 3174 return PTR_ERR(dc->rst); 3175 } 3176 3177 /* assert reset and disable clock */ 3178 err = clk_prepare_enable(dc->clk); 3179 if (err < 0) 3180 return err; 3181 3182 usleep_range(2000, 4000); 3183 3184 err = reset_control_assert(dc->rst); 3185 if (err < 0) 3186 return err; 3187 3188 usleep_range(2000, 4000); 3189 3190 clk_disable_unprepare(dc->clk); 3191 3192 if (dc->soc->has_powergate) { 3193 if (dc->pipe == 0) 3194 dc->powergate = TEGRA_POWERGATE_DIS; 3195 else 3196 dc->powergate = TEGRA_POWERGATE_DISB; 3197 3198 tegra_powergate_power_off(dc->powergate); 3199 } 3200 3201 err = tegra_dc_init_opp_table(dc); 3202 if (err < 0) 3203 return err; 3204 3205 dc->regs = devm_platform_ioremap_resource(pdev, 0); 3206 if (IS_ERR(dc->regs)) 3207 return PTR_ERR(dc->regs); 3208 3209 dc->irq = platform_get_irq(pdev, 0); 3210 if (dc->irq < 0) 3211 return -ENXIO; 3212 3213 err = tegra_dc_rgb_probe(dc); 3214 if (err < 0 && err != -ENODEV) { 3215 const char *level = KERN_ERR; 3216 3217 if (err == -EPROBE_DEFER) 3218 level = KERN_DEBUG; 3219 3220 dev_printk(level, dc->dev, "failed to probe RGB output: %d\n", 3221 err); 3222 return err; 3223 } 3224 3225 platform_set_drvdata(pdev, dc); 3226 pm_runtime_enable(&pdev->dev); 3227 3228 INIT_LIST_HEAD(&dc->client.list); 3229 dc->client.ops = &dc_client_ops; 3230 dc->client.dev = &pdev->dev; 3231 3232 err = host1x_client_register(&dc->client); 3233 if (err < 0) { 3234 dev_err(&pdev->dev, "failed to register host1x client: %d\n", 3235 err); 3236 goto disable_pm; 3237 } 3238 3239 return 0; 3240 3241 disable_pm: 3242 pm_runtime_disable(&pdev->dev); 3243 tegra_dc_rgb_remove(dc); 3244 3245 return err; 3246 } 3247 3248 static int tegra_dc_remove(struct platform_device *pdev) 3249 { 3250 struct tegra_dc *dc = platform_get_drvdata(pdev); 3251 int err; 3252 3253 err = host1x_client_unregister(&dc->client); 3254 if (err < 0) { 3255 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n", 3256 err); 3257 return err; 3258 } 3259 3260 err = tegra_dc_rgb_remove(dc); 3261 if (err < 0) { 3262 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err); 3263 return err; 3264 } 3265 3266 pm_runtime_disable(&pdev->dev); 3267 3268 return 0; 3269 } 3270 3271 struct platform_driver tegra_dc_driver = { 3272 .driver = { 3273 .name = "tegra-dc", 3274 .of_match_table = tegra_dc_of_match, 3275 }, 3276 .probe = tegra_dc_probe, 3277 .remove = tegra_dc_remove, 3278 }; 3279