1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) Icenowy Zheng <icenowy@aosc.io> 4 * 5 * Based on sun4i_layer.h, which is: 6 * Copyright (C) 2015 Free Electrons 7 * Copyright (C) 2015 NextThing Co 8 * 9 * Maxime Ripard <maxime.ripard@free-electrons.com> 10 */ 11 12 #include <drm/drm_atomic.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc.h> 15 #include <drm/drm_fb_cma_helper.h> 16 #include <drm/drm_fourcc.h> 17 #include <drm/drm_gem_atomic_helper.h> 18 #include <drm/drm_gem_cma_helper.h> 19 #include <drm/drm_plane_helper.h> 20 #include <drm/drm_probe_helper.h> 21 22 #include "sun8i_mixer.h" 23 #include "sun8i_ui_layer.h" 24 #include "sun8i_ui_scaler.h" 25 26 static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, 27 int overlay, bool enable, unsigned int zpos, 28 unsigned int old_zpos) 29 { 30 u32 val, bld_base, ch_base; 31 32 bld_base = sun8i_blender_base(mixer); 33 ch_base = sun8i_channel_base(mixer, channel); 34 35 DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n", 36 enable ? "En" : "Dis", channel, overlay); 37 38 if (enable) 39 val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; 40 else 41 val = 0; 42 43 regmap_update_bits(mixer->engine.regs, 44 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), 45 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); 46 47 if (!enable || zpos != old_zpos) { 48 regmap_update_bits(mixer->engine.regs, 49 SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), 50 SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), 51 0); 52 53 regmap_update_bits(mixer->engine.regs, 54 SUN8I_MIXER_BLEND_ROUTE(bld_base), 55 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), 56 0); 57 } 58 59 if (enable) { 60 val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); 61 62 regmap_update_bits(mixer->engine.regs, 63 SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), 64 val, val); 65 66 val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); 67 68 regmap_update_bits(mixer->engine.regs, 69 SUN8I_MIXER_BLEND_ROUTE(bld_base), 70 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos), 71 val); 72 } 73 } 74 75 static void sun8i_ui_layer_update_alpha(struct sun8i_mixer *mixer, int channel, 76 int overlay, struct drm_plane *plane) 77 { 78 u32 mask, val, ch_base; 79 80 ch_base = sun8i_channel_base(mixer, channel); 81 82 mask = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_MASK | 83 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MASK; 84 85 val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA(plane->state->alpha >> 8); 86 87 val |= (plane->state->alpha == DRM_BLEND_ALPHA_OPAQUE) ? 88 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_PIXEL : 89 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_ALPHA_MODE_COMBINED; 90 91 regmap_update_bits(mixer->engine.regs, 92 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), 93 mask, val); 94 } 95 96 static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, 97 int overlay, struct drm_plane *plane, 98 unsigned int zpos) 99 { 100 struct drm_plane_state *state = plane->state; 101 u32 src_w, src_h, dst_w, dst_h; 102 u32 bld_base, ch_base; 103 u32 outsize, insize; 104 u32 hphase, vphase; 105 106 DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n", 107 channel, overlay); 108 109 bld_base = sun8i_blender_base(mixer); 110 ch_base = sun8i_channel_base(mixer, channel); 111 112 src_w = drm_rect_width(&state->src) >> 16; 113 src_h = drm_rect_height(&state->src) >> 16; 114 dst_w = drm_rect_width(&state->dst); 115 dst_h = drm_rect_height(&state->dst); 116 117 hphase = state->src.x1 & 0xffff; 118 vphase = state->src.y1 & 0xffff; 119 120 insize = SUN8I_MIXER_SIZE(src_w, src_h); 121 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); 122 123 /* Set height and width */ 124 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", 125 state->src.x1 >> 16, state->src.y1 >> 16); 126 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); 127 regmap_write(mixer->engine.regs, 128 SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay), 129 insize); 130 regmap_write(mixer->engine.regs, 131 SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base), 132 insize); 133 134 if (insize != outsize || hphase || vphase) { 135 u32 hscale, vscale; 136 137 DRM_DEBUG_DRIVER("HW scaling is enabled\n"); 138 139 hscale = state->src_w / state->crtc_w; 140 vscale = state->src_h / state->crtc_h; 141 142 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, 143 dst_h, hscale, vscale, hphase, vphase); 144 sun8i_ui_scaler_enable(mixer, channel, true); 145 } else { 146 DRM_DEBUG_DRIVER("HW scaling is not needed\n"); 147 sun8i_ui_scaler_enable(mixer, channel, false); 148 } 149 150 /* Set base coordinates */ 151 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", 152 state->dst.x1, state->dst.y1); 153 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); 154 regmap_write(mixer->engine.regs, 155 SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), 156 SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1)); 157 regmap_write(mixer->engine.regs, 158 SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), 159 outsize); 160 161 return 0; 162 } 163 164 static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel, 165 int overlay, struct drm_plane *plane) 166 { 167 struct drm_plane_state *state = plane->state; 168 const struct drm_format_info *fmt; 169 u32 val, ch_base, hw_fmt; 170 int ret; 171 172 ch_base = sun8i_channel_base(mixer, channel); 173 174 fmt = state->fb->format; 175 ret = sun8i_mixer_drm_format_to_hw(fmt->format, &hw_fmt); 176 if (ret || fmt->is_yuv) { 177 DRM_DEBUG_DRIVER("Invalid format\n"); 178 return -EINVAL; 179 } 180 181 val = hw_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; 182 regmap_update_bits(mixer->engine.regs, 183 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), 184 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val); 185 186 return 0; 187 } 188 189 static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel, 190 int overlay, struct drm_plane *plane) 191 { 192 struct drm_plane_state *state = plane->state; 193 struct drm_framebuffer *fb = state->fb; 194 struct drm_gem_cma_object *gem; 195 dma_addr_t paddr; 196 u32 ch_base; 197 int bpp; 198 199 ch_base = sun8i_channel_base(mixer, channel); 200 201 /* Get the physical address of the buffer in memory */ 202 gem = drm_fb_cma_get_gem_obj(fb, 0); 203 204 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr); 205 206 /* Compute the start of the displayed memory */ 207 bpp = fb->format->cpp[0]; 208 paddr = gem->paddr + fb->offsets[0]; 209 210 /* Fixup framebuffer address for src coordinates */ 211 paddr += (state->src.x1 >> 16) * bpp; 212 paddr += (state->src.y1 >> 16) * fb->pitches[0]; 213 214 /* Set the line width */ 215 DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]); 216 regmap_write(mixer->engine.regs, 217 SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay), 218 fb->pitches[0]); 219 220 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); 221 222 regmap_write(mixer->engine.regs, 223 SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay), 224 lower_32_bits(paddr)); 225 226 return 0; 227 } 228 229 static int sun8i_ui_layer_atomic_check(struct drm_plane *plane, 230 struct drm_atomic_state *state) 231 { 232 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state, 233 plane); 234 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); 235 struct drm_crtc *crtc = new_plane_state->crtc; 236 struct drm_crtc_state *crtc_state; 237 int min_scale, max_scale; 238 239 if (!crtc) 240 return 0; 241 242 crtc_state = drm_atomic_get_existing_crtc_state(state, 243 crtc); 244 if (WARN_ON(!crtc_state)) 245 return -EINVAL; 246 247 min_scale = DRM_PLANE_HELPER_NO_SCALING; 248 max_scale = DRM_PLANE_HELPER_NO_SCALING; 249 250 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { 251 min_scale = SUN8I_UI_SCALER_SCALE_MIN; 252 max_scale = SUN8I_UI_SCALER_SCALE_MAX; 253 } 254 255 return drm_atomic_helper_check_plane_state(new_plane_state, 256 crtc_state, 257 min_scale, max_scale, 258 true, true); 259 } 260 261 static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane, 262 struct drm_atomic_state *state) 263 { 264 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 265 plane); 266 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); 267 unsigned int old_zpos = old_state->normalized_zpos; 268 struct sun8i_mixer *mixer = layer->mixer; 269 270 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, 271 old_zpos); 272 } 273 274 static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, 275 struct drm_atomic_state *state) 276 { 277 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, 278 plane); 279 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, 280 plane); 281 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); 282 unsigned int zpos = new_state->normalized_zpos; 283 unsigned int old_zpos = old_state->normalized_zpos; 284 struct sun8i_mixer *mixer = layer->mixer; 285 286 if (!new_state->visible) { 287 sun8i_ui_layer_enable(mixer, layer->channel, 288 layer->overlay, false, 0, old_zpos); 289 return; 290 } 291 292 sun8i_ui_layer_update_coord(mixer, layer->channel, 293 layer->overlay, plane, zpos); 294 sun8i_ui_layer_update_alpha(mixer, layer->channel, 295 layer->overlay, plane); 296 sun8i_ui_layer_update_formats(mixer, layer->channel, 297 layer->overlay, plane); 298 sun8i_ui_layer_update_buffer(mixer, layer->channel, 299 layer->overlay, plane); 300 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, 301 true, zpos, old_zpos); 302 } 303 304 static const struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = { 305 .atomic_check = sun8i_ui_layer_atomic_check, 306 .atomic_disable = sun8i_ui_layer_atomic_disable, 307 .atomic_update = sun8i_ui_layer_atomic_update, 308 }; 309 310 static const struct drm_plane_funcs sun8i_ui_layer_funcs = { 311 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 312 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 313 .destroy = drm_plane_cleanup, 314 .disable_plane = drm_atomic_helper_disable_plane, 315 .reset = drm_atomic_helper_plane_reset, 316 .update_plane = drm_atomic_helper_update_plane, 317 }; 318 319 static const u32 sun8i_ui_layer_formats[] = { 320 DRM_FORMAT_ABGR1555, 321 DRM_FORMAT_ABGR4444, 322 DRM_FORMAT_ABGR8888, 323 DRM_FORMAT_ARGB1555, 324 DRM_FORMAT_ARGB4444, 325 DRM_FORMAT_ARGB8888, 326 DRM_FORMAT_BGR565, 327 DRM_FORMAT_BGR888, 328 DRM_FORMAT_BGRA5551, 329 DRM_FORMAT_BGRA4444, 330 DRM_FORMAT_BGRA8888, 331 DRM_FORMAT_BGRX8888, 332 DRM_FORMAT_RGB565, 333 DRM_FORMAT_RGB888, 334 DRM_FORMAT_RGBA4444, 335 DRM_FORMAT_RGBA5551, 336 DRM_FORMAT_RGBA8888, 337 DRM_FORMAT_RGBX8888, 338 DRM_FORMAT_XBGR8888, 339 DRM_FORMAT_XRGB8888, 340 }; 341 342 static const uint64_t sun8i_layer_modifiers[] = { 343 DRM_FORMAT_MOD_LINEAR, 344 DRM_FORMAT_MOD_INVALID 345 }; 346 347 struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm, 348 struct sun8i_mixer *mixer, 349 int index) 350 { 351 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; 352 int channel = mixer->cfg->vi_num + index; 353 struct sun8i_ui_layer *layer; 354 unsigned int plane_cnt; 355 int ret; 356 357 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); 358 if (!layer) 359 return ERR_PTR(-ENOMEM); 360 361 if (index == 0) 362 type = DRM_PLANE_TYPE_PRIMARY; 363 364 /* possible crtcs are set later */ 365 ret = drm_universal_plane_init(drm, &layer->plane, 0, 366 &sun8i_ui_layer_funcs, 367 sun8i_ui_layer_formats, 368 ARRAY_SIZE(sun8i_ui_layer_formats), 369 sun8i_layer_modifiers, type, NULL); 370 if (ret) { 371 dev_err(drm->dev, "Couldn't initialize layer\n"); 372 return ERR_PTR(ret); 373 } 374 375 plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num; 376 377 ret = drm_plane_create_alpha_property(&layer->plane); 378 if (ret) { 379 dev_err(drm->dev, "Couldn't add alpha property\n"); 380 return ERR_PTR(ret); 381 } 382 383 ret = drm_plane_create_zpos_property(&layer->plane, channel, 384 0, plane_cnt - 1); 385 if (ret) { 386 dev_err(drm->dev, "Couldn't add zpos property\n"); 387 return ERR_PTR(ret); 388 } 389 390 drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs); 391 layer->mixer = mixer; 392 layer->channel = channel; 393 layer->overlay = 0; 394 395 return layer; 396 } 397