1 /* 2 * Copyright (C) Icenowy Zheng <icenowy@aosc.io> 3 * 4 * Based on sun4i_layer.h, which is: 5 * Copyright (C) 2015 Free Electrons 6 * Copyright (C) 2015 NextThing Co 7 * 8 * Maxime Ripard <maxime.ripard@free-electrons.com> 9 * 10 * This program is free software; you can redistribute it and/or 11 * modify it under the terms of the GNU General Public License as 12 * published by the Free Software Foundation; either version 2 of 13 * the License, or (at your option) any later version. 14 */ 15 16 #include <drm/drm_atomic.h> 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_fb_cma_helper.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_plane_helper.h> 23 #include <drm/drmP.h> 24 25 #include "sun8i_ui_layer.h" 26 #include "sun8i_mixer.h" 27 #include "sun8i_ui_scaler.h" 28 29 static void sun8i_ui_layer_enable(struct sun8i_mixer *mixer, int channel, 30 int overlay, bool enable, unsigned int zpos, 31 unsigned int old_zpos) 32 { 33 u32 val, bld_base, ch_base; 34 35 bld_base = sun8i_blender_base(mixer); 36 ch_base = sun8i_channel_base(mixer, channel); 37 38 DRM_DEBUG_DRIVER("%sabling channel %d overlay %d\n", 39 enable ? "En" : "Dis", channel, overlay); 40 41 if (enable) 42 val = SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN; 43 else 44 val = 0; 45 46 regmap_update_bits(mixer->engine.regs, 47 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), 48 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_EN, val); 49 50 if (!enable || zpos != old_zpos) { 51 regmap_update_bits(mixer->engine.regs, 52 SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), 53 SUN8I_MIXER_BLEND_PIPE_CTL_EN(old_zpos), 54 0); 55 56 regmap_update_bits(mixer->engine.regs, 57 SUN8I_MIXER_BLEND_ROUTE(bld_base), 58 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(old_zpos), 59 0); 60 } 61 62 if (enable) { 63 val = SUN8I_MIXER_BLEND_PIPE_CTL_EN(zpos); 64 65 regmap_update_bits(mixer->engine.regs, 66 SUN8I_MIXER_BLEND_PIPE_CTL(bld_base), 67 val, val); 68 69 val = channel << SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(zpos); 70 71 regmap_update_bits(mixer->engine.regs, 72 SUN8I_MIXER_BLEND_ROUTE(bld_base), 73 SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(zpos), 74 val); 75 } 76 } 77 78 static int sun8i_ui_layer_update_coord(struct sun8i_mixer *mixer, int channel, 79 int overlay, struct drm_plane *plane, 80 unsigned int zpos) 81 { 82 struct drm_plane_state *state = plane->state; 83 u32 src_w, src_h, dst_w, dst_h; 84 u32 bld_base, ch_base; 85 u32 outsize, insize; 86 u32 hphase, vphase; 87 88 DRM_DEBUG_DRIVER("Updating UI channel %d overlay %d\n", 89 channel, overlay); 90 91 bld_base = sun8i_blender_base(mixer); 92 ch_base = sun8i_channel_base(mixer, channel); 93 94 src_w = drm_rect_width(&state->src) >> 16; 95 src_h = drm_rect_height(&state->src) >> 16; 96 dst_w = drm_rect_width(&state->dst); 97 dst_h = drm_rect_height(&state->dst); 98 99 hphase = state->src.x1 & 0xffff; 100 vphase = state->src.y1 & 0xffff; 101 102 insize = SUN8I_MIXER_SIZE(src_w, src_h); 103 outsize = SUN8I_MIXER_SIZE(dst_w, dst_h); 104 105 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 106 bool interlaced = false; 107 u32 val; 108 109 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", 110 dst_w, dst_h); 111 regmap_write(mixer->engine.regs, 112 SUN8I_MIXER_GLOBAL_SIZE, 113 outsize); 114 regmap_write(mixer->engine.regs, 115 SUN8I_MIXER_BLEND_OUTSIZE(bld_base), outsize); 116 117 if (state->crtc) 118 interlaced = state->crtc->state->adjusted_mode.flags 119 & DRM_MODE_FLAG_INTERLACE; 120 121 if (interlaced) 122 val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; 123 else 124 val = 0; 125 126 regmap_update_bits(mixer->engine.regs, 127 SUN8I_MIXER_BLEND_OUTCTL(bld_base), 128 SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, 129 val); 130 131 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", 132 interlaced ? "on" : "off"); 133 } 134 135 /* Set height and width */ 136 DRM_DEBUG_DRIVER("Layer source offset X: %d Y: %d\n", 137 state->src.x1 >> 16, state->src.y1 >> 16); 138 DRM_DEBUG_DRIVER("Layer source size W: %d H: %d\n", src_w, src_h); 139 regmap_write(mixer->engine.regs, 140 SUN8I_MIXER_CHAN_UI_LAYER_SIZE(ch_base, overlay), 141 insize); 142 regmap_write(mixer->engine.regs, 143 SUN8I_MIXER_CHAN_UI_OVL_SIZE(ch_base), 144 insize); 145 146 if (insize != outsize || hphase || vphase) { 147 u32 hscale, vscale; 148 149 DRM_DEBUG_DRIVER("HW scaling is enabled\n"); 150 151 hscale = state->src_w / state->crtc_w; 152 vscale = state->src_h / state->crtc_h; 153 154 sun8i_ui_scaler_setup(mixer, channel, src_w, src_h, dst_w, 155 dst_h, hscale, vscale, hphase, vphase); 156 sun8i_ui_scaler_enable(mixer, channel, true); 157 } else { 158 DRM_DEBUG_DRIVER("HW scaling is not needed\n"); 159 sun8i_ui_scaler_enable(mixer, channel, false); 160 } 161 162 /* Set base coordinates */ 163 DRM_DEBUG_DRIVER("Layer destination coordinates X: %d Y: %d\n", 164 state->dst.x1, state->dst.y1); 165 DRM_DEBUG_DRIVER("Layer destination size W: %d H: %d\n", dst_w, dst_h); 166 regmap_write(mixer->engine.regs, 167 SUN8I_MIXER_BLEND_ATTR_COORD(bld_base, zpos), 168 SUN8I_MIXER_COORD(state->dst.x1, state->dst.y1)); 169 regmap_write(mixer->engine.regs, 170 SUN8I_MIXER_BLEND_ATTR_INSIZE(bld_base, zpos), 171 outsize); 172 173 return 0; 174 } 175 176 static int sun8i_ui_layer_update_formats(struct sun8i_mixer *mixer, int channel, 177 int overlay, struct drm_plane *plane) 178 { 179 struct drm_plane_state *state = plane->state; 180 const struct de2_fmt_info *fmt_info; 181 u32 val, ch_base; 182 183 ch_base = sun8i_channel_base(mixer, channel); 184 185 fmt_info = sun8i_mixer_format_info(state->fb->format->format); 186 if (!fmt_info || !fmt_info->rgb) { 187 DRM_DEBUG_DRIVER("Invalid format\n"); 188 return -EINVAL; 189 } 190 191 val = fmt_info->de2_fmt << SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_OFFSET; 192 regmap_update_bits(mixer->engine.regs, 193 SUN8I_MIXER_CHAN_UI_LAYER_ATTR(ch_base, overlay), 194 SUN8I_MIXER_CHAN_UI_LAYER_ATTR_FBFMT_MASK, val); 195 196 return 0; 197 } 198 199 static int sun8i_ui_layer_update_buffer(struct sun8i_mixer *mixer, int channel, 200 int overlay, struct drm_plane *plane) 201 { 202 struct drm_plane_state *state = plane->state; 203 struct drm_framebuffer *fb = state->fb; 204 struct drm_gem_cma_object *gem; 205 dma_addr_t paddr; 206 u32 ch_base; 207 int bpp; 208 209 ch_base = sun8i_channel_base(mixer, channel); 210 211 /* Get the physical address of the buffer in memory */ 212 gem = drm_fb_cma_get_gem_obj(fb, 0); 213 214 DRM_DEBUG_DRIVER("Using GEM @ %pad\n", &gem->paddr); 215 216 /* Compute the start of the displayed memory */ 217 bpp = fb->format->cpp[0]; 218 paddr = gem->paddr + fb->offsets[0]; 219 220 /* Fixup framebuffer address for src coordinates */ 221 paddr += (state->src.x1 >> 16) * bpp; 222 paddr += (state->src.y1 >> 16) * fb->pitches[0]; 223 224 /* Set the line width */ 225 DRM_DEBUG_DRIVER("Layer line width: %d bytes\n", fb->pitches[0]); 226 regmap_write(mixer->engine.regs, 227 SUN8I_MIXER_CHAN_UI_LAYER_PITCH(ch_base, overlay), 228 fb->pitches[0]); 229 230 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); 231 232 regmap_write(mixer->engine.regs, 233 SUN8I_MIXER_CHAN_UI_LAYER_TOP_LADDR(ch_base, overlay), 234 lower_32_bits(paddr)); 235 236 return 0; 237 } 238 239 static int sun8i_ui_layer_atomic_check(struct drm_plane *plane, 240 struct drm_plane_state *state) 241 { 242 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); 243 struct drm_crtc *crtc = state->crtc; 244 struct drm_crtc_state *crtc_state; 245 int min_scale, max_scale; 246 247 if (!crtc) 248 return 0; 249 250 crtc_state = drm_atomic_get_existing_crtc_state(state->state, crtc); 251 if (WARN_ON(!crtc_state)) 252 return -EINVAL; 253 254 min_scale = DRM_PLANE_HELPER_NO_SCALING; 255 max_scale = DRM_PLANE_HELPER_NO_SCALING; 256 257 if (layer->mixer->cfg->scaler_mask & BIT(layer->channel)) { 258 min_scale = SUN8I_UI_SCALER_SCALE_MIN; 259 max_scale = SUN8I_UI_SCALER_SCALE_MAX; 260 } 261 262 return drm_atomic_helper_check_plane_state(state, crtc_state, 263 min_scale, max_scale, 264 true, true); 265 } 266 267 static void sun8i_ui_layer_atomic_disable(struct drm_plane *plane, 268 struct drm_plane_state *old_state) 269 { 270 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); 271 unsigned int old_zpos = old_state->normalized_zpos; 272 struct sun8i_mixer *mixer = layer->mixer; 273 274 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, false, 0, 275 old_zpos); 276 } 277 278 static void sun8i_ui_layer_atomic_update(struct drm_plane *plane, 279 struct drm_plane_state *old_state) 280 { 281 struct sun8i_ui_layer *layer = plane_to_sun8i_ui_layer(plane); 282 unsigned int zpos = plane->state->normalized_zpos; 283 unsigned int old_zpos = old_state->normalized_zpos; 284 struct sun8i_mixer *mixer = layer->mixer; 285 286 if (!plane->state->visible) { 287 sun8i_ui_layer_enable(mixer, layer->channel, 288 layer->overlay, false, 0, old_zpos); 289 return; 290 } 291 292 sun8i_ui_layer_update_coord(mixer, layer->channel, 293 layer->overlay, plane, zpos); 294 sun8i_ui_layer_update_formats(mixer, layer->channel, 295 layer->overlay, plane); 296 sun8i_ui_layer_update_buffer(mixer, layer->channel, 297 layer->overlay, plane); 298 sun8i_ui_layer_enable(mixer, layer->channel, layer->overlay, 299 true, zpos, old_zpos); 300 } 301 302 static struct drm_plane_helper_funcs sun8i_ui_layer_helper_funcs = { 303 .atomic_check = sun8i_ui_layer_atomic_check, 304 .atomic_disable = sun8i_ui_layer_atomic_disable, 305 .atomic_update = sun8i_ui_layer_atomic_update, 306 }; 307 308 static const struct drm_plane_funcs sun8i_ui_layer_funcs = { 309 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 310 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 311 .destroy = drm_plane_cleanup, 312 .disable_plane = drm_atomic_helper_disable_plane, 313 .reset = drm_atomic_helper_plane_reset, 314 .update_plane = drm_atomic_helper_update_plane, 315 }; 316 317 static const u32 sun8i_ui_layer_formats[] = { 318 DRM_FORMAT_ABGR1555, 319 DRM_FORMAT_ABGR4444, 320 DRM_FORMAT_ABGR8888, 321 DRM_FORMAT_ARGB1555, 322 DRM_FORMAT_ARGB4444, 323 DRM_FORMAT_ARGB8888, 324 DRM_FORMAT_BGR565, 325 DRM_FORMAT_BGR888, 326 DRM_FORMAT_BGRA5551, 327 DRM_FORMAT_BGRA4444, 328 DRM_FORMAT_BGRA8888, 329 DRM_FORMAT_BGRX8888, 330 DRM_FORMAT_RGB565, 331 DRM_FORMAT_RGB888, 332 DRM_FORMAT_RGBA4444, 333 DRM_FORMAT_RGBA5551, 334 DRM_FORMAT_RGBA8888, 335 DRM_FORMAT_RGBX8888, 336 DRM_FORMAT_XBGR8888, 337 DRM_FORMAT_XRGB8888, 338 }; 339 340 struct sun8i_ui_layer *sun8i_ui_layer_init_one(struct drm_device *drm, 341 struct sun8i_mixer *mixer, 342 int index) 343 { 344 enum drm_plane_type type = DRM_PLANE_TYPE_OVERLAY; 345 int channel = mixer->cfg->vi_num + index; 346 struct sun8i_ui_layer *layer; 347 unsigned int plane_cnt; 348 int ret; 349 350 layer = devm_kzalloc(drm->dev, sizeof(*layer), GFP_KERNEL); 351 if (!layer) 352 return ERR_PTR(-ENOMEM); 353 354 if (index == 0) 355 type = DRM_PLANE_TYPE_PRIMARY; 356 357 /* possible crtcs are set later */ 358 ret = drm_universal_plane_init(drm, &layer->plane, 0, 359 &sun8i_ui_layer_funcs, 360 sun8i_ui_layer_formats, 361 ARRAY_SIZE(sun8i_ui_layer_formats), 362 NULL, type, NULL); 363 if (ret) { 364 dev_err(drm->dev, "Couldn't initialize layer\n"); 365 return ERR_PTR(ret); 366 } 367 368 plane_cnt = mixer->cfg->ui_num + mixer->cfg->vi_num; 369 370 ret = drm_plane_create_zpos_property(&layer->plane, channel, 371 0, plane_cnt - 1); 372 if (ret) { 373 dev_err(drm->dev, "Couldn't add zpos property\n"); 374 return ERR_PTR(ret); 375 } 376 377 drm_plane_helper_add(&layer->plane, &sun8i_ui_layer_helper_funcs); 378 layer->mixer = mixer; 379 layer->channel = channel; 380 layer->overlay = 0; 381 382 return layer; 383 } 384