1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
3 
4 
5 #include <linux/bitfield.h>
6 #include <linux/component.h>
7 #include <linux/device.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of_device.h>
11 #include <linux/of_graph.h>
12 #include <linux/platform_device.h>
13 
14 #include <dt-bindings/clock/sun8i-tcon-top.h>
15 
16 #include "sun8i_tcon_top.h"
17 
18 struct sun8i_tcon_top_quirks {
19 	bool has_tcon_tv1;
20 	bool has_dsi;
21 };
22 
23 static bool sun8i_tcon_top_node_is_tcon_top(struct device_node *node)
24 {
25 	return !!of_match_node(sun8i_tcon_top_of_table, node);
26 }
27 
28 int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon)
29 {
30 	struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
31 	unsigned long flags;
32 	u32 val;
33 
34 	if (!sun8i_tcon_top_node_is_tcon_top(dev->of_node)) {
35 		dev_err(dev, "Device is not TCON TOP!\n");
36 		return -EINVAL;
37 	}
38 
39 	if (tcon < 2 || tcon > 3) {
40 		dev_err(dev, "TCON index must be 2 or 3!\n");
41 		return -EINVAL;
42 	}
43 
44 	spin_lock_irqsave(&tcon_top->reg_lock, flags);
45 
46 	val = readl(tcon_top->regs + TCON_TOP_GATE_SRC_REG);
47 	val &= ~TCON_TOP_HDMI_SRC_MSK;
48 	val |= FIELD_PREP(TCON_TOP_HDMI_SRC_MSK, tcon - 1);
49 	writel(val, tcon_top->regs + TCON_TOP_GATE_SRC_REG);
50 
51 	spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
52 
53 	return 0;
54 }
55 EXPORT_SYMBOL(sun8i_tcon_top_set_hdmi_src);
56 
57 int sun8i_tcon_top_de_config(struct device *dev, int mixer, int tcon)
58 {
59 	struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
60 	unsigned long flags;
61 	u32 reg;
62 
63 	if (!sun8i_tcon_top_node_is_tcon_top(dev->of_node)) {
64 		dev_err(dev, "Device is not TCON TOP!\n");
65 		return -EINVAL;
66 	}
67 
68 	if (mixer > 1) {
69 		dev_err(dev, "Mixer index is too high!\n");
70 		return -EINVAL;
71 	}
72 
73 	if (tcon > 3) {
74 		dev_err(dev, "TCON index is too high!\n");
75 		return -EINVAL;
76 	}
77 
78 	spin_lock_irqsave(&tcon_top->reg_lock, flags);
79 
80 	reg = readl(tcon_top->regs + TCON_TOP_PORT_SEL_REG);
81 	if (mixer == 0) {
82 		reg &= ~TCON_TOP_PORT_DE0_MSK;
83 		reg |= FIELD_PREP(TCON_TOP_PORT_DE0_MSK, tcon);
84 	} else {
85 		reg &= ~TCON_TOP_PORT_DE1_MSK;
86 		reg |= FIELD_PREP(TCON_TOP_PORT_DE1_MSK, tcon);
87 	}
88 	writel(reg, tcon_top->regs + TCON_TOP_PORT_SEL_REG);
89 
90 	spin_unlock_irqrestore(&tcon_top->reg_lock, flags);
91 
92 	return 0;
93 }
94 EXPORT_SYMBOL(sun8i_tcon_top_de_config);
95 
96 
97 static struct clk_hw *sun8i_tcon_top_register_gate(struct device *dev,
98 						   const char *parent,
99 						   void __iomem *regs,
100 						   spinlock_t *lock,
101 						   u8 bit, int name_index)
102 {
103 	const char *clk_name, *parent_name;
104 	int ret, index;
105 
106 	index = of_property_match_string(dev->of_node, "clock-names", parent);
107 	if (index < 0)
108 		return ERR_PTR(index);
109 
110 	parent_name = of_clk_get_parent_name(dev->of_node, index);
111 
112 	ret = of_property_read_string_index(dev->of_node,
113 					    "clock-output-names", name_index,
114 					    &clk_name);
115 	if (ret)
116 		return ERR_PTR(ret);
117 
118 	return clk_hw_register_gate(dev, clk_name, parent_name,
119 				    CLK_SET_RATE_PARENT,
120 				    regs + TCON_TOP_GATE_SRC_REG,
121 				    bit, 0, lock);
122 };
123 
124 static int sun8i_tcon_top_bind(struct device *dev, struct device *master,
125 			       void *data)
126 {
127 	struct platform_device *pdev = to_platform_device(dev);
128 	struct clk_hw_onecell_data *clk_data;
129 	struct sun8i_tcon_top *tcon_top;
130 	const struct sun8i_tcon_top_quirks *quirks;
131 	void __iomem *regs;
132 	int ret, i;
133 
134 	quirks = of_device_get_match_data(&pdev->dev);
135 
136 	tcon_top = devm_kzalloc(dev, sizeof(*tcon_top), GFP_KERNEL);
137 	if (!tcon_top)
138 		return -ENOMEM;
139 
140 	clk_data = devm_kzalloc(dev, struct_size(clk_data, hws, CLK_NUM),
141 				GFP_KERNEL);
142 	if (!clk_data)
143 		return -ENOMEM;
144 	tcon_top->clk_data = clk_data;
145 
146 	spin_lock_init(&tcon_top->reg_lock);
147 
148 	tcon_top->rst = devm_reset_control_get(dev, NULL);
149 	if (IS_ERR(tcon_top->rst)) {
150 		dev_err(dev, "Couldn't get our reset line\n");
151 		return PTR_ERR(tcon_top->rst);
152 	}
153 
154 	tcon_top->bus = devm_clk_get(dev, "bus");
155 	if (IS_ERR(tcon_top->bus)) {
156 		dev_err(dev, "Couldn't get the bus clock\n");
157 		return PTR_ERR(tcon_top->bus);
158 	}
159 
160 	regs = devm_platform_ioremap_resource(pdev, 0);
161 	tcon_top->regs = regs;
162 	if (IS_ERR(regs))
163 		return PTR_ERR(regs);
164 
165 	ret = reset_control_deassert(tcon_top->rst);
166 	if (ret) {
167 		dev_err(dev, "Could not deassert ctrl reset control\n");
168 		return ret;
169 	}
170 
171 	ret = clk_prepare_enable(tcon_top->bus);
172 	if (ret) {
173 		dev_err(dev, "Could not enable bus clock\n");
174 		goto err_assert_reset;
175 	}
176 
177 	/*
178 	 * At least on H6, some registers have some bits set by default
179 	 * which may cause issues. Clear them here.
180 	 */
181 	writel(0, regs + TCON_TOP_PORT_SEL_REG);
182 	writel(0, regs + TCON_TOP_GATE_SRC_REG);
183 
184 	/*
185 	 * TCON TOP has two muxes, which select parent clock for each TCON TV
186 	 * channel clock. Parent could be either TCON TV or TVE clock. For now
187 	 * we leave this fixed to TCON TV, since TVE driver for R40 is not yet
188 	 * implemented. Once it is, graph needs to be traversed to determine
189 	 * if TVE is active on each TCON TV. If it is, mux should be switched
190 	 * to TVE clock parent.
191 	 */
192 	i = 0;
193 	clk_data->hws[CLK_TCON_TOP_TV0] =
194 		sun8i_tcon_top_register_gate(dev, "tcon-tv0", regs,
195 					     &tcon_top->reg_lock,
196 					     TCON_TOP_TCON_TV0_GATE, i++);
197 
198 	if (quirks->has_tcon_tv1)
199 		clk_data->hws[CLK_TCON_TOP_TV1] =
200 			sun8i_tcon_top_register_gate(dev, "tcon-tv1", regs,
201 						     &tcon_top->reg_lock,
202 						     TCON_TOP_TCON_TV1_GATE, i++);
203 
204 	if (quirks->has_dsi)
205 		clk_data->hws[CLK_TCON_TOP_DSI] =
206 			sun8i_tcon_top_register_gate(dev, "dsi", regs,
207 						     &tcon_top->reg_lock,
208 						     TCON_TOP_TCON_DSI_GATE, i++);
209 
210 	for (i = 0; i < CLK_NUM; i++)
211 		if (IS_ERR(clk_data->hws[i])) {
212 			ret = PTR_ERR(clk_data->hws[i]);
213 			goto err_unregister_gates;
214 		}
215 
216 	clk_data->num = CLK_NUM;
217 
218 	ret = of_clk_add_hw_provider(dev->of_node, of_clk_hw_onecell_get,
219 				     clk_data);
220 	if (ret)
221 		goto err_unregister_gates;
222 
223 	dev_set_drvdata(dev, tcon_top);
224 
225 	return 0;
226 
227 err_unregister_gates:
228 	for (i = 0; i < CLK_NUM; i++)
229 		if (!IS_ERR_OR_NULL(clk_data->hws[i]))
230 			clk_hw_unregister_gate(clk_data->hws[i]);
231 	clk_disable_unprepare(tcon_top->bus);
232 err_assert_reset:
233 	reset_control_assert(tcon_top->rst);
234 
235 	return ret;
236 }
237 
238 static void sun8i_tcon_top_unbind(struct device *dev, struct device *master,
239 				  void *data)
240 {
241 	struct sun8i_tcon_top *tcon_top = dev_get_drvdata(dev);
242 	struct clk_hw_onecell_data *clk_data = tcon_top->clk_data;
243 	int i;
244 
245 	of_clk_del_provider(dev->of_node);
246 	for (i = 0; i < CLK_NUM; i++)
247 		if (clk_data->hws[i])
248 			clk_hw_unregister_gate(clk_data->hws[i]);
249 
250 	clk_disable_unprepare(tcon_top->bus);
251 	reset_control_assert(tcon_top->rst);
252 }
253 
254 static const struct component_ops sun8i_tcon_top_ops = {
255 	.bind	= sun8i_tcon_top_bind,
256 	.unbind	= sun8i_tcon_top_unbind,
257 };
258 
259 static int sun8i_tcon_top_probe(struct platform_device *pdev)
260 {
261 	return component_add(&pdev->dev, &sun8i_tcon_top_ops);
262 }
263 
264 static int sun8i_tcon_top_remove(struct platform_device *pdev)
265 {
266 	component_del(&pdev->dev, &sun8i_tcon_top_ops);
267 
268 	return 0;
269 }
270 
271 static const struct sun8i_tcon_top_quirks sun8i_r40_tcon_top_quirks = {
272 	.has_tcon_tv1	= true,
273 	.has_dsi	= true,
274 };
275 
276 static const struct sun8i_tcon_top_quirks sun20i_d1_tcon_top_quirks = {
277 	.has_dsi	= true,
278 };
279 
280 static const struct sun8i_tcon_top_quirks sun50i_h6_tcon_top_quirks = {
281 	/* Nothing special */
282 };
283 
284 /* sun4i_drv uses this list to check if a device node is a TCON TOP */
285 const struct of_device_id sun8i_tcon_top_of_table[] = {
286 	{
287 		.compatible = "allwinner,sun8i-r40-tcon-top",
288 		.data = &sun8i_r40_tcon_top_quirks
289 	},
290 	{
291 		.compatible = "allwinner,sun20i-d1-tcon-top",
292 		.data = &sun20i_d1_tcon_top_quirks
293 	},
294 	{
295 		.compatible = "allwinner,sun50i-h6-tcon-top",
296 		.data = &sun50i_h6_tcon_top_quirks
297 	},
298 	{ /* sentinel */ }
299 };
300 MODULE_DEVICE_TABLE(of, sun8i_tcon_top_of_table);
301 EXPORT_SYMBOL(sun8i_tcon_top_of_table);
302 
303 static struct platform_driver sun8i_tcon_top_platform_driver = {
304 	.probe		= sun8i_tcon_top_probe,
305 	.remove		= sun8i_tcon_top_remove,
306 	.driver		= {
307 		.name		= "sun8i-tcon-top",
308 		.of_match_table	= sun8i_tcon_top_of_table,
309 	},
310 };
311 module_platform_driver(sun8i_tcon_top_platform_driver);
312 
313 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
314 MODULE_DESCRIPTION("Allwinner R40 TCON TOP driver");
315 MODULE_LICENSE("GPL");
316