1 /*
2  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
3  *
4  * This program is free software; you can redistribute it and/or
5  * modify it under the terms of the GNU General Public License as
6  * published by the Free Software Foundation; either version 2 of
7  * the License, or (at your option) any later version.
8  */
9 
10 #ifndef _SUN8I_MIXER_H_
11 #define _SUN8I_MIXER_H_
12 
13 #include <linux/clk.h>
14 #include <linux/regmap.h>
15 #include <linux/reset.h>
16 
17 #include "sun8i_csc.h"
18 #include "sunxi_engine.h"
19 
20 #define SUN8I_MIXER_SIZE(w, h)			(((h) - 1) << 16 | ((w) - 1))
21 #define SUN8I_MIXER_COORD(x, y)			((y) << 16 | (x))
22 
23 #define SUN8I_MIXER_GLOBAL_CTL			0x0
24 #define SUN8I_MIXER_GLOBAL_STATUS		0x4
25 #define SUN8I_MIXER_GLOBAL_DBUFF		0x8
26 #define SUN8I_MIXER_GLOBAL_SIZE			0xc
27 
28 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN		BIT(0)
29 
30 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE		BIT(0)
31 
32 #define SUN8I_MIXER_BLEND_PIPE_CTL		0x1000
33 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(x)	(0x1004 + 0x10 * (x) + 0x0)
34 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(x)	(0x1004 + 0x10 * (x) + 0x4)
35 #define SUN8I_MIXER_BLEND_ATTR_COORD(x)		(0x1004 + 0x10 * (x) + 0x8)
36 #define SUN8I_MIXER_BLEND_ROUTE			0x1080
37 #define SUN8I_MIXER_BLEND_PREMULTIPLY		0x1084
38 #define SUN8I_MIXER_BLEND_BKCOLOR		0x1088
39 #define SUN8I_MIXER_BLEND_OUTSIZE		0x108c
40 #define SUN8I_MIXER_BLEND_MODE(x)		(0x1090 + 0x04 * (x))
41 #define SUN8I_MIXER_BLEND_CK_CTL		0x10b0
42 #define SUN8I_MIXER_BLEND_CK_CFG		0x10b4
43 #define SUN8I_MIXER_BLEND_CK_MAX(x)		(0x10c0 + 0x04 * (x))
44 #define SUN8I_MIXER_BLEND_CK_MIN(x)		(0x10e0 + 0x04 * (x))
45 #define SUN8I_MIXER_BLEND_OUTCTL		0x10fc
46 
47 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK	GENMASK(12, 8)
48 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe)	BIT(8 + pipe)
49 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe)	BIT(pipe)
50 /* colors are always in AARRGGBB format */
51 #define SUN8I_MIXER_BLEND_COLOR_BLACK		0xff000000
52 /* The following numbers are some still unknown magic numbers */
53 #define SUN8I_MIXER_BLEND_MODE_DEF		0x03010301
54 
55 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n)	(0xf << ((n) << 2))
56 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n)	((n) << 2)
57 
58 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED	BIT(1)
59 
60 #define SUN8I_MIXER_FBFMT_ARGB8888	0
61 #define SUN8I_MIXER_FBFMT_ABGR8888	1
62 #define SUN8I_MIXER_FBFMT_RGBA8888	2
63 #define SUN8I_MIXER_FBFMT_BGRA8888	3
64 #define SUN8I_MIXER_FBFMT_XRGB8888	4
65 #define SUN8I_MIXER_FBFMT_XBGR8888	5
66 #define SUN8I_MIXER_FBFMT_RGBX8888	6
67 #define SUN8I_MIXER_FBFMT_BGRX8888	7
68 #define SUN8I_MIXER_FBFMT_RGB888	8
69 #define SUN8I_MIXER_FBFMT_BGR888	9
70 #define SUN8I_MIXER_FBFMT_RGB565	10
71 #define SUN8I_MIXER_FBFMT_BGR565	11
72 #define SUN8I_MIXER_FBFMT_ARGB4444	12
73 #define SUN8I_MIXER_FBFMT_ABGR4444	13
74 #define SUN8I_MIXER_FBFMT_RGBA4444	14
75 #define SUN8I_MIXER_FBFMT_BGRA4444	15
76 #define SUN8I_MIXER_FBFMT_ARGB1555	16
77 #define SUN8I_MIXER_FBFMT_ABGR1555	17
78 #define SUN8I_MIXER_FBFMT_RGBA5551	18
79 #define SUN8I_MIXER_FBFMT_BGRA5551	19
80 
81 #define SUN8I_MIXER_FBFMT_YUYV		0
82 #define SUN8I_MIXER_FBFMT_UYVY		1
83 #define SUN8I_MIXER_FBFMT_YVYU		2
84 #define SUN8I_MIXER_FBFMT_VYUY		3
85 #define SUN8I_MIXER_FBFMT_NV16		4
86 #define SUN8I_MIXER_FBFMT_NV61		5
87 #define SUN8I_MIXER_FBFMT_YUV422	6
88 /* format 7 doesn't exist */
89 #define SUN8I_MIXER_FBFMT_NV12		8
90 #define SUN8I_MIXER_FBFMT_NV21		9
91 #define SUN8I_MIXER_FBFMT_YUV420	10
92 /* format 11 doesn't exist */
93 /* format 12 is semi-planar YUV411 UVUV */
94 /* format 13 is semi-planar YUV411 VUVU */
95 #define SUN8I_MIXER_FBFMT_YUV411	14
96 
97 /*
98  * These sub-engines are still unknown now, the EN registers are here only to
99  * be used to disable these sub-engines.
100  */
101 #define SUN8I_MIXER_FCE_EN			0xa0000
102 #define SUN8I_MIXER_BWS_EN			0xa2000
103 #define SUN8I_MIXER_LTI_EN			0xa4000
104 #define SUN8I_MIXER_PEAK_EN			0xa6000
105 #define SUN8I_MIXER_ASE_EN			0xa8000
106 #define SUN8I_MIXER_FCC_EN			0xaa000
107 #define SUN8I_MIXER_DCSC_EN			0xb0000
108 
109 struct de2_fmt_info {
110 	u32			drm_fmt;
111 	u32			de2_fmt;
112 	bool			rgb;
113 	enum sun8i_csc_mode	csc;
114 };
115 
116 /**
117  * struct sun8i_mixer_cfg - mixer HW configuration
118  * @vi_num: number of VI channels
119  * @ui_num: number of UI channels
120  * @scaler_mask: bitmask which tells which channel supports scaling
121  *	First, scaler supports for VI channels is defined and after that, scaler
122  *	support for UI channels. For example, if mixer has 2 VI channels without
123  *	scaler and 2 UI channels with scaler, bitmask would be 0xC.
124  * @ccsc: select set of CCSC base addresses
125  *	Set value to 0 if this is first mixer or second mixer with VEP support.
126  *	Set value to 1 if this is second mixer without VEP support. Other values
127  *	are invalid.
128  * @mod_rate: module clock rate that needs to be set in order to have
129  *	a functional block.
130  */
131 struct sun8i_mixer_cfg {
132 	int		vi_num;
133 	int		ui_num;
134 	int		scaler_mask;
135 	int		ccsc;
136 	unsigned long	mod_rate;
137 };
138 
139 struct sun8i_mixer {
140 	struct sunxi_engine		engine;
141 
142 	const struct sun8i_mixer_cfg	*cfg;
143 
144 	struct reset_control		*reset;
145 
146 	struct clk			*bus_clk;
147 	struct clk			*mod_clk;
148 };
149 
150 static inline struct sun8i_mixer *
151 engine_to_sun8i_mixer(struct sunxi_engine *engine)
152 {
153 	return container_of(engine, struct sun8i_mixer, engine);
154 }
155 
156 const struct de2_fmt_info *sun8i_mixer_format_info(u32 format);
157 #endif /* _SUN8I_MIXER_H_ */
158