1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io> 4 * 5 * Based on sun4i_backend.c, which is: 6 * Copyright (C) 2015 Free Electrons 7 * Copyright (C) 2015 NextThing Co 8 */ 9 10 #include <linux/component.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/module.h> 13 #include <linux/of_device.h> 14 #include <linux/of_graph.h> 15 #include <linux/reset.h> 16 17 #include <drm/drm_atomic_helper.h> 18 #include <drm/drm_crtc.h> 19 #include <drm/drm_framebuffer.h> 20 #include <drm/drm_gem_dma_helper.h> 21 #include <drm/drm_probe_helper.h> 22 23 #include "sun4i_drv.h" 24 #include "sun8i_mixer.h" 25 #include "sun8i_ui_layer.h" 26 #include "sun8i_vi_layer.h" 27 #include "sunxi_engine.h" 28 29 struct de2_fmt_info { 30 u32 drm_fmt; 31 u32 de2_fmt; 32 }; 33 34 static const struct de2_fmt_info de2_formats[] = { 35 { 36 .drm_fmt = DRM_FORMAT_ARGB8888, 37 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB8888, 38 }, 39 { 40 .drm_fmt = DRM_FORMAT_ABGR8888, 41 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR8888, 42 }, 43 { 44 .drm_fmt = DRM_FORMAT_RGBA8888, 45 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA8888, 46 }, 47 { 48 .drm_fmt = DRM_FORMAT_BGRA8888, 49 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA8888, 50 }, 51 { 52 .drm_fmt = DRM_FORMAT_XRGB8888, 53 .de2_fmt = SUN8I_MIXER_FBFMT_XRGB8888, 54 }, 55 { 56 .drm_fmt = DRM_FORMAT_XBGR8888, 57 .de2_fmt = SUN8I_MIXER_FBFMT_XBGR8888, 58 }, 59 { 60 .drm_fmt = DRM_FORMAT_RGBX8888, 61 .de2_fmt = SUN8I_MIXER_FBFMT_RGBX8888, 62 }, 63 { 64 .drm_fmt = DRM_FORMAT_BGRX8888, 65 .de2_fmt = SUN8I_MIXER_FBFMT_BGRX8888, 66 }, 67 { 68 .drm_fmt = DRM_FORMAT_RGB888, 69 .de2_fmt = SUN8I_MIXER_FBFMT_RGB888, 70 }, 71 { 72 .drm_fmt = DRM_FORMAT_BGR888, 73 .de2_fmt = SUN8I_MIXER_FBFMT_BGR888, 74 }, 75 { 76 .drm_fmt = DRM_FORMAT_RGB565, 77 .de2_fmt = SUN8I_MIXER_FBFMT_RGB565, 78 }, 79 { 80 .drm_fmt = DRM_FORMAT_BGR565, 81 .de2_fmt = SUN8I_MIXER_FBFMT_BGR565, 82 }, 83 { 84 .drm_fmt = DRM_FORMAT_ARGB4444, 85 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444, 86 }, 87 { 88 /* for DE2 VI layer which ignores alpha */ 89 .drm_fmt = DRM_FORMAT_XRGB4444, 90 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB4444, 91 }, 92 { 93 .drm_fmt = DRM_FORMAT_ABGR4444, 94 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444, 95 }, 96 { 97 /* for DE2 VI layer which ignores alpha */ 98 .drm_fmt = DRM_FORMAT_XBGR4444, 99 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR4444, 100 }, 101 { 102 .drm_fmt = DRM_FORMAT_RGBA4444, 103 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444, 104 }, 105 { 106 /* for DE2 VI layer which ignores alpha */ 107 .drm_fmt = DRM_FORMAT_RGBX4444, 108 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA4444, 109 }, 110 { 111 .drm_fmt = DRM_FORMAT_BGRA4444, 112 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444, 113 }, 114 { 115 /* for DE2 VI layer which ignores alpha */ 116 .drm_fmt = DRM_FORMAT_BGRX4444, 117 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA4444, 118 }, 119 { 120 .drm_fmt = DRM_FORMAT_ARGB1555, 121 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555, 122 }, 123 { 124 /* for DE2 VI layer which ignores alpha */ 125 .drm_fmt = DRM_FORMAT_XRGB1555, 126 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB1555, 127 }, 128 { 129 .drm_fmt = DRM_FORMAT_ABGR1555, 130 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555, 131 }, 132 { 133 /* for DE2 VI layer which ignores alpha */ 134 .drm_fmt = DRM_FORMAT_XBGR1555, 135 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR1555, 136 }, 137 { 138 .drm_fmt = DRM_FORMAT_RGBA5551, 139 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551, 140 }, 141 { 142 /* for DE2 VI layer which ignores alpha */ 143 .drm_fmt = DRM_FORMAT_RGBX5551, 144 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA5551, 145 }, 146 { 147 .drm_fmt = DRM_FORMAT_BGRA5551, 148 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551, 149 }, 150 { 151 /* for DE2 VI layer which ignores alpha */ 152 .drm_fmt = DRM_FORMAT_BGRX5551, 153 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA5551, 154 }, 155 { 156 .drm_fmt = DRM_FORMAT_ARGB2101010, 157 .de2_fmt = SUN8I_MIXER_FBFMT_ARGB2101010, 158 }, 159 { 160 .drm_fmt = DRM_FORMAT_ABGR2101010, 161 .de2_fmt = SUN8I_MIXER_FBFMT_ABGR2101010, 162 }, 163 { 164 .drm_fmt = DRM_FORMAT_RGBA1010102, 165 .de2_fmt = SUN8I_MIXER_FBFMT_RGBA1010102, 166 }, 167 { 168 .drm_fmt = DRM_FORMAT_BGRA1010102, 169 .de2_fmt = SUN8I_MIXER_FBFMT_BGRA1010102, 170 }, 171 { 172 .drm_fmt = DRM_FORMAT_UYVY, 173 .de2_fmt = SUN8I_MIXER_FBFMT_UYVY, 174 }, 175 { 176 .drm_fmt = DRM_FORMAT_VYUY, 177 .de2_fmt = SUN8I_MIXER_FBFMT_VYUY, 178 }, 179 { 180 .drm_fmt = DRM_FORMAT_YUYV, 181 .de2_fmt = SUN8I_MIXER_FBFMT_YUYV, 182 }, 183 { 184 .drm_fmt = DRM_FORMAT_YVYU, 185 .de2_fmt = SUN8I_MIXER_FBFMT_YVYU, 186 }, 187 { 188 .drm_fmt = DRM_FORMAT_NV16, 189 .de2_fmt = SUN8I_MIXER_FBFMT_NV16, 190 }, 191 { 192 .drm_fmt = DRM_FORMAT_NV61, 193 .de2_fmt = SUN8I_MIXER_FBFMT_NV61, 194 }, 195 { 196 .drm_fmt = DRM_FORMAT_NV12, 197 .de2_fmt = SUN8I_MIXER_FBFMT_NV12, 198 }, 199 { 200 .drm_fmt = DRM_FORMAT_NV21, 201 .de2_fmt = SUN8I_MIXER_FBFMT_NV21, 202 }, 203 { 204 .drm_fmt = DRM_FORMAT_YUV422, 205 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422, 206 }, 207 { 208 .drm_fmt = DRM_FORMAT_YUV420, 209 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420, 210 }, 211 { 212 .drm_fmt = DRM_FORMAT_YUV411, 213 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411, 214 }, 215 { 216 .drm_fmt = DRM_FORMAT_YVU422, 217 .de2_fmt = SUN8I_MIXER_FBFMT_YUV422, 218 }, 219 { 220 .drm_fmt = DRM_FORMAT_YVU420, 221 .de2_fmt = SUN8I_MIXER_FBFMT_YUV420, 222 }, 223 { 224 .drm_fmt = DRM_FORMAT_YVU411, 225 .de2_fmt = SUN8I_MIXER_FBFMT_YUV411, 226 }, 227 { 228 .drm_fmt = DRM_FORMAT_P010, 229 .de2_fmt = SUN8I_MIXER_FBFMT_P010_YUV, 230 }, 231 { 232 .drm_fmt = DRM_FORMAT_P210, 233 .de2_fmt = SUN8I_MIXER_FBFMT_P210_YUV, 234 }, 235 }; 236 237 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format) 238 { 239 unsigned int i; 240 241 for (i = 0; i < ARRAY_SIZE(de2_formats); ++i) 242 if (de2_formats[i].drm_fmt == format) { 243 *hw_format = de2_formats[i].de2_fmt; 244 return 0; 245 } 246 247 return -EINVAL; 248 } 249 250 static void sun8i_mixer_commit(struct sunxi_engine *engine) 251 { 252 DRM_DEBUG_DRIVER("Committing changes\n"); 253 254 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_DBUFF, 255 SUN8I_MIXER_GLOBAL_DBUFF_ENABLE); 256 } 257 258 static struct drm_plane **sun8i_layers_init(struct drm_device *drm, 259 struct sunxi_engine *engine) 260 { 261 struct drm_plane **planes; 262 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); 263 int i; 264 265 planes = devm_kcalloc(drm->dev, 266 mixer->cfg->vi_num + mixer->cfg->ui_num + 1, 267 sizeof(*planes), GFP_KERNEL); 268 if (!planes) 269 return ERR_PTR(-ENOMEM); 270 271 for (i = 0; i < mixer->cfg->vi_num; i++) { 272 struct sun8i_vi_layer *layer; 273 274 layer = sun8i_vi_layer_init_one(drm, mixer, i); 275 if (IS_ERR(layer)) { 276 dev_err(drm->dev, 277 "Couldn't initialize overlay plane\n"); 278 return ERR_CAST(layer); 279 } 280 281 planes[i] = &layer->plane; 282 } 283 284 for (i = 0; i < mixer->cfg->ui_num; i++) { 285 struct sun8i_ui_layer *layer; 286 287 layer = sun8i_ui_layer_init_one(drm, mixer, i); 288 if (IS_ERR(layer)) { 289 dev_err(drm->dev, "Couldn't initialize %s plane\n", 290 i ? "overlay" : "primary"); 291 return ERR_CAST(layer); 292 } 293 294 planes[mixer->cfg->vi_num + i] = &layer->plane; 295 } 296 297 return planes; 298 } 299 300 static void sun8i_mixer_mode_set(struct sunxi_engine *engine, 301 const struct drm_display_mode *mode) 302 { 303 struct sun8i_mixer *mixer = engine_to_sun8i_mixer(engine); 304 u32 bld_base, size, val; 305 bool interlaced; 306 307 bld_base = sun8i_blender_base(mixer); 308 interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE); 309 size = SUN8I_MIXER_SIZE(mode->hdisplay, mode->vdisplay); 310 311 DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n", 312 mode->hdisplay, mode->vdisplay); 313 314 regmap_write(engine->regs, SUN8I_MIXER_GLOBAL_SIZE, size); 315 regmap_write(engine->regs, SUN8I_MIXER_BLEND_OUTSIZE(bld_base), size); 316 317 if (interlaced) 318 val = SUN8I_MIXER_BLEND_OUTCTL_INTERLACED; 319 else 320 val = 0; 321 322 regmap_update_bits(engine->regs, SUN8I_MIXER_BLEND_OUTCTL(bld_base), 323 SUN8I_MIXER_BLEND_OUTCTL_INTERLACED, val); 324 325 DRM_DEBUG_DRIVER("Switching display mixer interlaced mode %s\n", 326 interlaced ? "on" : "off"); 327 } 328 329 static const struct sunxi_engine_ops sun8i_engine_ops = { 330 .commit = sun8i_mixer_commit, 331 .layers_init = sun8i_layers_init, 332 .mode_set = sun8i_mixer_mode_set, 333 }; 334 335 static const struct regmap_config sun8i_mixer_regmap_config = { 336 .reg_bits = 32, 337 .val_bits = 32, 338 .reg_stride = 4, 339 .max_register = 0xffffc, /* guessed */ 340 }; 341 342 static int sun8i_mixer_of_get_id(struct device_node *node) 343 { 344 struct device_node *ep, *remote; 345 struct of_endpoint of_ep; 346 347 /* Output port is 1, and we want the first endpoint. */ 348 ep = of_graph_get_endpoint_by_regs(node, 1, -1); 349 if (!ep) 350 return -EINVAL; 351 352 remote = of_graph_get_remote_endpoint(ep); 353 of_node_put(ep); 354 if (!remote) 355 return -EINVAL; 356 357 of_graph_parse_endpoint(remote, &of_ep); 358 of_node_put(remote); 359 return of_ep.id; 360 } 361 362 static int sun8i_mixer_bind(struct device *dev, struct device *master, 363 void *data) 364 { 365 struct platform_device *pdev = to_platform_device(dev); 366 struct drm_device *drm = data; 367 struct sun4i_drv *drv = drm->dev_private; 368 struct sun8i_mixer *mixer; 369 void __iomem *regs; 370 unsigned int base; 371 int plane_cnt; 372 int i, ret; 373 374 /* 375 * The mixer uses single 32-bit register to store memory 376 * addresses, so that it cannot deal with 64-bit memory 377 * addresses. 378 * Restrict the DMA mask so that the mixer won't be 379 * allocated some memory that is too high. 380 */ 381 ret = dma_set_mask(dev, DMA_BIT_MASK(32)); 382 if (ret) { 383 dev_err(dev, "Cannot do 32-bit DMA.\n"); 384 return ret; 385 } 386 387 mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL); 388 if (!mixer) 389 return -ENOMEM; 390 dev_set_drvdata(dev, mixer); 391 mixer->engine.ops = &sun8i_engine_ops; 392 mixer->engine.node = dev->of_node; 393 394 if (of_property_present(dev->of_node, "iommus")) { 395 /* 396 * This assume we have the same DMA constraints for 397 * all our the mixers in our pipeline. This sounds 398 * bad, but it has always been the case for us, and 399 * DRM doesn't do per-device allocation either, so we 400 * would need to fix DRM first... 401 */ 402 ret = of_dma_configure(drm->dev, dev->of_node, true); 403 if (ret) 404 return ret; 405 } 406 407 /* 408 * While this function can fail, we shouldn't do anything 409 * if this happens. Some early DE2 DT entries don't provide 410 * mixer id but work nevertheless because matching between 411 * TCON and mixer is done by comparing node pointers (old 412 * way) instead comparing ids. If this function fails and 413 * id is needed, it will fail during id matching anyway. 414 */ 415 mixer->engine.id = sun8i_mixer_of_get_id(dev->of_node); 416 417 mixer->cfg = of_device_get_match_data(dev); 418 if (!mixer->cfg) 419 return -EINVAL; 420 421 regs = devm_platform_ioremap_resource(pdev, 0); 422 if (IS_ERR(regs)) 423 return PTR_ERR(regs); 424 425 mixer->engine.regs = devm_regmap_init_mmio(dev, regs, 426 &sun8i_mixer_regmap_config); 427 if (IS_ERR(mixer->engine.regs)) { 428 dev_err(dev, "Couldn't create the mixer regmap\n"); 429 return PTR_ERR(mixer->engine.regs); 430 } 431 432 mixer->reset = devm_reset_control_get(dev, NULL); 433 if (IS_ERR(mixer->reset)) { 434 dev_err(dev, "Couldn't get our reset line\n"); 435 return PTR_ERR(mixer->reset); 436 } 437 438 ret = reset_control_deassert(mixer->reset); 439 if (ret) { 440 dev_err(dev, "Couldn't deassert our reset line\n"); 441 return ret; 442 } 443 444 mixer->bus_clk = devm_clk_get(dev, "bus"); 445 if (IS_ERR(mixer->bus_clk)) { 446 dev_err(dev, "Couldn't get the mixer bus clock\n"); 447 ret = PTR_ERR(mixer->bus_clk); 448 goto err_assert_reset; 449 } 450 clk_prepare_enable(mixer->bus_clk); 451 452 mixer->mod_clk = devm_clk_get(dev, "mod"); 453 if (IS_ERR(mixer->mod_clk)) { 454 dev_err(dev, "Couldn't get the mixer module clock\n"); 455 ret = PTR_ERR(mixer->mod_clk); 456 goto err_disable_bus_clk; 457 } 458 459 /* 460 * It seems that we need to enforce that rate for whatever 461 * reason for the mixer to be functional. Make sure it's the 462 * case. 463 */ 464 if (mixer->cfg->mod_rate) 465 clk_set_rate(mixer->mod_clk, mixer->cfg->mod_rate); 466 467 clk_prepare_enable(mixer->mod_clk); 468 469 list_add_tail(&mixer->engine.list, &drv->engine_list); 470 471 base = sun8i_blender_base(mixer); 472 473 /* Reset registers and disable unused sub-engines */ 474 if (mixer->cfg->is_de3) { 475 for (i = 0; i < DE3_MIXER_UNIT_SIZE; i += 4) 476 regmap_write(mixer->engine.regs, i, 0); 477 478 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCE_EN, 0); 479 regmap_write(mixer->engine.regs, SUN50I_MIXER_PEAK_EN, 0); 480 regmap_write(mixer->engine.regs, SUN50I_MIXER_LCTI_EN, 0); 481 regmap_write(mixer->engine.regs, SUN50I_MIXER_BLS_EN, 0); 482 regmap_write(mixer->engine.regs, SUN50I_MIXER_FCC_EN, 0); 483 regmap_write(mixer->engine.regs, SUN50I_MIXER_DNS_EN, 0); 484 regmap_write(mixer->engine.regs, SUN50I_MIXER_DRC_EN, 0); 485 regmap_write(mixer->engine.regs, SUN50I_MIXER_FMT_EN, 0); 486 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC0_EN, 0); 487 regmap_write(mixer->engine.regs, SUN50I_MIXER_CDC1_EN, 0); 488 } else { 489 for (i = 0; i < DE2_MIXER_UNIT_SIZE; i += 4) 490 regmap_write(mixer->engine.regs, i, 0); 491 492 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCE_EN, 0); 493 regmap_write(mixer->engine.regs, SUN8I_MIXER_BWS_EN, 0); 494 regmap_write(mixer->engine.regs, SUN8I_MIXER_LTI_EN, 0); 495 regmap_write(mixer->engine.regs, SUN8I_MIXER_PEAK_EN, 0); 496 regmap_write(mixer->engine.regs, SUN8I_MIXER_ASE_EN, 0); 497 regmap_write(mixer->engine.regs, SUN8I_MIXER_FCC_EN, 0); 498 regmap_write(mixer->engine.regs, SUN8I_MIXER_DCSC_EN, 0); 499 } 500 501 /* Enable the mixer */ 502 regmap_write(mixer->engine.regs, SUN8I_MIXER_GLOBAL_CTL, 503 SUN8I_MIXER_GLOBAL_CTL_RT_EN); 504 505 /* Set background color to black */ 506 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_BKCOLOR(base), 507 SUN8I_MIXER_BLEND_COLOR_BLACK); 508 509 /* 510 * Set fill color of bottom plane to black. Generally not needed 511 * except when VI plane is at bottom (zpos = 0) and enabled. 512 */ 513 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), 514 SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(0)); 515 regmap_write(mixer->engine.regs, SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, 0), 516 SUN8I_MIXER_BLEND_COLOR_BLACK); 517 518 plane_cnt = mixer->cfg->vi_num + mixer->cfg->ui_num; 519 for (i = 0; i < plane_cnt; i++) 520 regmap_write(mixer->engine.regs, 521 SUN8I_MIXER_BLEND_MODE(base, i), 522 SUN8I_MIXER_BLEND_MODE_DEF); 523 524 regmap_update_bits(mixer->engine.regs, SUN8I_MIXER_BLEND_PIPE_CTL(base), 525 SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK, 0); 526 527 return 0; 528 529 err_disable_bus_clk: 530 clk_disable_unprepare(mixer->bus_clk); 531 err_assert_reset: 532 reset_control_assert(mixer->reset); 533 return ret; 534 } 535 536 static void sun8i_mixer_unbind(struct device *dev, struct device *master, 537 void *data) 538 { 539 struct sun8i_mixer *mixer = dev_get_drvdata(dev); 540 541 list_del(&mixer->engine.list); 542 543 clk_disable_unprepare(mixer->mod_clk); 544 clk_disable_unprepare(mixer->bus_clk); 545 reset_control_assert(mixer->reset); 546 } 547 548 static const struct component_ops sun8i_mixer_ops = { 549 .bind = sun8i_mixer_bind, 550 .unbind = sun8i_mixer_unbind, 551 }; 552 553 static int sun8i_mixer_probe(struct platform_device *pdev) 554 { 555 return component_add(&pdev->dev, &sun8i_mixer_ops); 556 } 557 558 static int sun8i_mixer_remove(struct platform_device *pdev) 559 { 560 component_del(&pdev->dev, &sun8i_mixer_ops); 561 562 return 0; 563 } 564 565 static const struct sun8i_mixer_cfg sun8i_a83t_mixer0_cfg = { 566 .ccsc = CCSC_MIXER0_LAYOUT, 567 .scaler_mask = 0xf, 568 .scanline_yuv = 2048, 569 .ui_num = 3, 570 .vi_num = 1, 571 }; 572 573 static const struct sun8i_mixer_cfg sun8i_a83t_mixer1_cfg = { 574 .ccsc = CCSC_MIXER1_LAYOUT, 575 .scaler_mask = 0x3, 576 .scanline_yuv = 2048, 577 .ui_num = 1, 578 .vi_num = 1, 579 }; 580 581 static const struct sun8i_mixer_cfg sun8i_h3_mixer0_cfg = { 582 .ccsc = CCSC_MIXER0_LAYOUT, 583 .mod_rate = 432000000, 584 .scaler_mask = 0xf, 585 .scanline_yuv = 2048, 586 .ui_num = 3, 587 .vi_num = 1, 588 }; 589 590 static const struct sun8i_mixer_cfg sun8i_r40_mixer0_cfg = { 591 .ccsc = CCSC_MIXER0_LAYOUT, 592 .mod_rate = 297000000, 593 .scaler_mask = 0xf, 594 .scanline_yuv = 2048, 595 .ui_num = 3, 596 .vi_num = 1, 597 }; 598 599 static const struct sun8i_mixer_cfg sun8i_r40_mixer1_cfg = { 600 .ccsc = CCSC_MIXER1_LAYOUT, 601 .mod_rate = 297000000, 602 .scaler_mask = 0x3, 603 .scanline_yuv = 2048, 604 .ui_num = 1, 605 .vi_num = 1, 606 }; 607 608 static const struct sun8i_mixer_cfg sun8i_v3s_mixer_cfg = { 609 .vi_num = 2, 610 .ui_num = 1, 611 .scaler_mask = 0x3, 612 .scanline_yuv = 2048, 613 .ccsc = CCSC_MIXER0_LAYOUT, 614 .mod_rate = 150000000, 615 }; 616 617 static const struct sun8i_mixer_cfg sun20i_d1_mixer0_cfg = { 618 .ccsc = CCSC_D1_MIXER0_LAYOUT, 619 .mod_rate = 297000000, 620 .scaler_mask = 0x3, 621 .scanline_yuv = 2048, 622 .ui_num = 1, 623 .vi_num = 1, 624 }; 625 626 static const struct sun8i_mixer_cfg sun20i_d1_mixer1_cfg = { 627 .ccsc = CCSC_MIXER1_LAYOUT, 628 .mod_rate = 297000000, 629 .scaler_mask = 0x1, 630 .scanline_yuv = 1024, 631 .ui_num = 0, 632 .vi_num = 1, 633 }; 634 635 static const struct sun8i_mixer_cfg sun50i_a64_mixer0_cfg = { 636 .ccsc = CCSC_MIXER0_LAYOUT, 637 .mod_rate = 297000000, 638 .scaler_mask = 0xf, 639 .scanline_yuv = 4096, 640 .ui_num = 3, 641 .vi_num = 1, 642 }; 643 644 static const struct sun8i_mixer_cfg sun50i_a64_mixer1_cfg = { 645 .ccsc = CCSC_MIXER1_LAYOUT, 646 .mod_rate = 297000000, 647 .scaler_mask = 0x3, 648 .scanline_yuv = 2048, 649 .ui_num = 1, 650 .vi_num = 1, 651 }; 652 653 static const struct sun8i_mixer_cfg sun50i_h6_mixer0_cfg = { 654 .ccsc = CCSC_MIXER0_LAYOUT, 655 .is_de3 = true, 656 .mod_rate = 600000000, 657 .scaler_mask = 0xf, 658 .scanline_yuv = 4096, 659 .ui_num = 3, 660 .vi_num = 1, 661 }; 662 663 static const struct of_device_id sun8i_mixer_of_table[] = { 664 { 665 .compatible = "allwinner,sun8i-a83t-de2-mixer-0", 666 .data = &sun8i_a83t_mixer0_cfg, 667 }, 668 { 669 .compatible = "allwinner,sun8i-a83t-de2-mixer-1", 670 .data = &sun8i_a83t_mixer1_cfg, 671 }, 672 { 673 .compatible = "allwinner,sun8i-h3-de2-mixer-0", 674 .data = &sun8i_h3_mixer0_cfg, 675 }, 676 { 677 .compatible = "allwinner,sun8i-r40-de2-mixer-0", 678 .data = &sun8i_r40_mixer0_cfg, 679 }, 680 { 681 .compatible = "allwinner,sun8i-r40-de2-mixer-1", 682 .data = &sun8i_r40_mixer1_cfg, 683 }, 684 { 685 .compatible = "allwinner,sun8i-v3s-de2-mixer", 686 .data = &sun8i_v3s_mixer_cfg, 687 }, 688 { 689 .compatible = "allwinner,sun20i-d1-de2-mixer-0", 690 .data = &sun20i_d1_mixer0_cfg, 691 }, 692 { 693 .compatible = "allwinner,sun20i-d1-de2-mixer-1", 694 .data = &sun20i_d1_mixer1_cfg, 695 }, 696 { 697 .compatible = "allwinner,sun50i-a64-de2-mixer-0", 698 .data = &sun50i_a64_mixer0_cfg, 699 }, 700 { 701 .compatible = "allwinner,sun50i-a64-de2-mixer-1", 702 .data = &sun50i_a64_mixer1_cfg, 703 }, 704 { 705 .compatible = "allwinner,sun50i-h6-de3-mixer-0", 706 .data = &sun50i_h6_mixer0_cfg, 707 }, 708 { } 709 }; 710 MODULE_DEVICE_TABLE(of, sun8i_mixer_of_table); 711 712 static struct platform_driver sun8i_mixer_platform_driver = { 713 .probe = sun8i_mixer_probe, 714 .remove = sun8i_mixer_remove, 715 .driver = { 716 .name = "sun8i-mixer", 717 .of_match_table = sun8i_mixer_of_table, 718 }, 719 }; 720 module_platform_driver(sun8i_mixer_platform_driver); 721 722 MODULE_AUTHOR("Icenowy Zheng <icenowy@aosc.io>"); 723 MODULE_DESCRIPTION("Allwinner DE2 Mixer driver"); 724 MODULE_LICENSE("GPL"); 725