1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> 4 */ 5 6 #include <linux/delay.h> 7 #include <linux/of_address.h> 8 9 #include "sun8i_dw_hdmi.h" 10 11 /* 12 * Address can be actually any value. Here is set to same value as 13 * it is set in BSP driver. 14 */ 15 #define I2C_ADDR 0x69 16 17 static const struct dw_hdmi_mpll_config sun50i_h6_mpll_cfg[] = { 18 { 19 30666000, { 20 { 0x00b3, 0x0000 }, 21 { 0x2153, 0x0000 }, 22 { 0x40f3, 0x0000 }, 23 }, 24 }, { 25 36800000, { 26 { 0x00b3, 0x0000 }, 27 { 0x2153, 0x0000 }, 28 { 0x40a2, 0x0001 }, 29 }, 30 }, { 31 46000000, { 32 { 0x00b3, 0x0000 }, 33 { 0x2142, 0x0001 }, 34 { 0x40a2, 0x0001 }, 35 }, 36 }, { 37 61333000, { 38 { 0x0072, 0x0001 }, 39 { 0x2142, 0x0001 }, 40 { 0x40a2, 0x0001 }, 41 }, 42 }, { 43 73600000, { 44 { 0x0072, 0x0001 }, 45 { 0x2142, 0x0001 }, 46 { 0x4061, 0x0002 }, 47 }, 48 }, { 49 92000000, { 50 { 0x0072, 0x0001 }, 51 { 0x2145, 0x0002 }, 52 { 0x4061, 0x0002 }, 53 }, 54 }, { 55 122666000, { 56 { 0x0051, 0x0002 }, 57 { 0x2145, 0x0002 }, 58 { 0x4061, 0x0002 }, 59 }, 60 }, { 61 147200000, { 62 { 0x0051, 0x0002 }, 63 { 0x2145, 0x0002 }, 64 { 0x4064, 0x0003 }, 65 }, 66 }, { 67 184000000, { 68 { 0x0051, 0x0002 }, 69 { 0x214c, 0x0003 }, 70 { 0x4064, 0x0003 }, 71 }, 72 }, { 73 226666000, { 74 { 0x0040, 0x0003 }, 75 { 0x214c, 0x0003 }, 76 { 0x4064, 0x0003 }, 77 }, 78 }, { 79 272000000, { 80 { 0x0040, 0x0003 }, 81 { 0x214c, 0x0003 }, 82 { 0x5a64, 0x0003 }, 83 }, 84 }, { 85 340000000, { 86 { 0x0040, 0x0003 }, 87 { 0x3b4c, 0x0003 }, 88 { 0x5a64, 0x0003 }, 89 }, 90 }, { 91 594000000, { 92 { 0x1a40, 0x0003 }, 93 { 0x3b4c, 0x0003 }, 94 { 0x5a64, 0x0003 }, 95 }, 96 }, { 97 ~0UL, { 98 { 0x0000, 0x0000 }, 99 { 0x0000, 0x0000 }, 100 { 0x0000, 0x0000 }, 101 }, 102 } 103 }; 104 105 static const struct dw_hdmi_curr_ctrl sun50i_h6_cur_ctr[] = { 106 /* pixelclk bpp8 bpp10 bpp12 */ 107 { 25175000, { 0x0000, 0x0000, 0x0000 }, }, 108 { 27000000, { 0x0012, 0x0000, 0x0000 }, }, 109 { 59400000, { 0x0008, 0x0008, 0x0008 }, }, 110 { 72000000, { 0x0008, 0x0008, 0x001b }, }, 111 { 74250000, { 0x0013, 0x0013, 0x0013 }, }, 112 { 90000000, { 0x0008, 0x001a, 0x001b }, }, 113 { 118800000, { 0x001b, 0x001a, 0x001b }, }, 114 { 144000000, { 0x001b, 0x001a, 0x0034 }, }, 115 { 180000000, { 0x001b, 0x0033, 0x0034 }, }, 116 { 216000000, { 0x0036, 0x0033, 0x0034 }, }, 117 { 237600000, { 0x0036, 0x0033, 0x001b }, }, 118 { 288000000, { 0x0036, 0x001b, 0x001b }, }, 119 { 297000000, { 0x0019, 0x001b, 0x0019 }, }, 120 { 330000000, { 0x0036, 0x001b, 0x001b }, }, 121 { 594000000, { 0x003f, 0x001b, 0x001b }, }, 122 { ~0UL, { 0x0000, 0x0000, 0x0000 }, } 123 }; 124 125 static const struct dw_hdmi_phy_config sun50i_h6_phy_config[] = { 126 /*pixelclk symbol term vlev*/ 127 { 74250000, 0x8009, 0x0004, 0x0232}, 128 { 148500000, 0x8029, 0x0004, 0x0273}, 129 { 594000000, 0x8039, 0x0004, 0x014a}, 130 { ~0UL, 0x0000, 0x0000, 0x0000} 131 }; 132 133 static int sun8i_hdmi_phy_config_a83t(struct dw_hdmi *hdmi, 134 struct sun8i_hdmi_phy *phy, 135 unsigned int clk_rate) 136 { 137 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, 138 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 139 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN); 140 141 /* power down */ 142 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 143 dw_hdmi_phy_gen2_pddq(hdmi, 1); 144 145 dw_hdmi_phy_reset(hdmi); 146 147 dw_hdmi_phy_gen2_pddq(hdmi, 0); 148 149 dw_hdmi_phy_i2c_set_addr(hdmi, I2C_ADDR); 150 151 /* 152 * Values are taken from BSP HDMI driver. Although AW didn't 153 * release any documentation, explanation of this values can 154 * be found in i.MX 6Dual/6Quad Reference Manual. 155 */ 156 if (clk_rate <= 27000000) { 157 dw_hdmi_phy_i2c_write(hdmi, 0x01e0, 0x06); 158 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x15); 159 dw_hdmi_phy_i2c_write(hdmi, 0x08da, 0x10); 160 dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19); 161 dw_hdmi_phy_i2c_write(hdmi, 0x0318, 0x0e); 162 dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09); 163 } else if (clk_rate <= 74250000) { 164 dw_hdmi_phy_i2c_write(hdmi, 0x0540, 0x06); 165 dw_hdmi_phy_i2c_write(hdmi, 0x0005, 0x15); 166 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10); 167 dw_hdmi_phy_i2c_write(hdmi, 0x0007, 0x19); 168 dw_hdmi_phy_i2c_write(hdmi, 0x02b5, 0x0e); 169 dw_hdmi_phy_i2c_write(hdmi, 0x8009, 0x09); 170 } else if (clk_rate <= 148500000) { 171 dw_hdmi_phy_i2c_write(hdmi, 0x04a0, 0x06); 172 dw_hdmi_phy_i2c_write(hdmi, 0x000a, 0x15); 173 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10); 174 dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19); 175 dw_hdmi_phy_i2c_write(hdmi, 0x0021, 0x0e); 176 dw_hdmi_phy_i2c_write(hdmi, 0x8029, 0x09); 177 } else { 178 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x06); 179 dw_hdmi_phy_i2c_write(hdmi, 0x000f, 0x15); 180 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x10); 181 dw_hdmi_phy_i2c_write(hdmi, 0x0002, 0x19); 182 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x0e); 183 dw_hdmi_phy_i2c_write(hdmi, 0x802b, 0x09); 184 } 185 186 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x1e); 187 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x13); 188 dw_hdmi_phy_i2c_write(hdmi, 0x0000, 0x17); 189 190 dw_hdmi_phy_gen2_txpwron(hdmi, 1); 191 192 return 0; 193 } 194 195 static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi, 196 struct sun8i_hdmi_phy *phy, 197 unsigned int clk_rate) 198 { 199 u32 pll_cfg1_init; 200 u32 pll_cfg2_init; 201 u32 ana_cfg1_end; 202 u32 ana_cfg2_init; 203 u32 ana_cfg3_init; 204 u32 b_offset = 0; 205 u32 val; 206 207 /* bandwidth / frequency independent settings */ 208 209 pll_cfg1_init = SUN8I_HDMI_PHY_PLL_CFG1_LDO2_EN | 210 SUN8I_HDMI_PHY_PLL_CFG1_LDO1_EN | 211 SUN8I_HDMI_PHY_PLL_CFG1_LDO_VSET(7) | 212 SUN8I_HDMI_PHY_PLL_CFG1_UNKNOWN(1) | 213 SUN8I_HDMI_PHY_PLL_CFG1_PLLDBEN | 214 SUN8I_HDMI_PHY_PLL_CFG1_CS | 215 SUN8I_HDMI_PHY_PLL_CFG1_CP_S(2) | 216 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63) | 217 SUN8I_HDMI_PHY_PLL_CFG1_BWS; 218 219 pll_cfg2_init = SUN8I_HDMI_PHY_PLL_CFG2_SV_H | 220 SUN8I_HDMI_PHY_PLL_CFG2_VCOGAIN_EN | 221 SUN8I_HDMI_PHY_PLL_CFG2_SDIV2; 222 223 ana_cfg1_end = SUN8I_HDMI_PHY_ANA_CFG1_REG_SVBH(1) | 224 SUN8I_HDMI_PHY_ANA_CFG1_AMP_OPT | 225 SUN8I_HDMI_PHY_ANA_CFG1_EMP_OPT | 226 SUN8I_HDMI_PHY_ANA_CFG1_AMPCK_OPT | 227 SUN8I_HDMI_PHY_ANA_CFG1_EMPCK_OPT | 228 SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL | 229 SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG | 230 SUN8I_HDMI_PHY_ANA_CFG1_REG_SCKTMDS | 231 SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN | 232 SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK | 233 SUN8I_HDMI_PHY_ANA_CFG1_TXEN_ALL | 234 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK | 235 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | 236 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | 237 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | 238 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2 | 239 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | 240 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | 241 SUN8I_HDMI_PHY_ANA_CFG1_CKEN | 242 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN | 243 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS | 244 SUN8I_HDMI_PHY_ANA_CFG1_ENBI; 245 246 ana_cfg2_init = SUN8I_HDMI_PHY_ANA_CFG2_M_EN | 247 SUN8I_HDMI_PHY_ANA_CFG2_REG_DENCK | 248 SUN8I_HDMI_PHY_ANA_CFG2_REG_DEN | 249 SUN8I_HDMI_PHY_ANA_CFG2_REG_CKSS(1) | 250 SUN8I_HDMI_PHY_ANA_CFG2_REG_CSMPS(1); 251 252 ana_cfg3_init = SUN8I_HDMI_PHY_ANA_CFG3_REG_WIRE(0x3e0) | 253 SUN8I_HDMI_PHY_ANA_CFG3_SDAEN | 254 SUN8I_HDMI_PHY_ANA_CFG3_SCLEN; 255 256 /* bandwidth / frequency dependent settings */ 257 if (clk_rate <= 27000000) { 258 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | 259 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); 260 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | 261 SUN8I_HDMI_PHY_PLL_CFG2_S(4); 262 ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW; 263 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) | 264 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); 265 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(3) | 266 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(5); 267 } else if (clk_rate <= 74250000) { 268 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | 269 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); 270 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | 271 SUN8I_HDMI_PHY_PLL_CFG2_S(5); 272 ana_cfg1_end |= SUN8I_HDMI_PHY_ANA_CFG1_REG_CALSW; 273 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4) | 274 SUN8I_HDMI_PHY_ANA_CFG2_REG_RESDI(phy->rcal); 275 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(5) | 276 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(7); 277 } else if (clk_rate <= 148500000) { 278 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_HV_IS_33 | 279 SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(32); 280 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(4) | 281 SUN8I_HDMI_PHY_PLL_CFG2_S(6); 282 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK | 283 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | 284 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(2); 285 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(7) | 286 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(9); 287 } else { 288 b_offset = 2; 289 pll_cfg1_init |= SUN8I_HDMI_PHY_PLL_CFG1_CNT_INT(63); 290 pll_cfg2_init |= SUN8I_HDMI_PHY_PLL_CFG2_VCO_S(6) | 291 SUN8I_HDMI_PHY_PLL_CFG2_S(7); 292 ana_cfg2_init |= SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSWCK | 293 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW | 294 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4); 295 ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) | 296 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13); 297 } 298 299 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 300 SUN8I_HDMI_PHY_ANA_CFG1_TXEN_MASK, 0); 301 302 /* 303 * NOTE: We have to be careful not to overwrite PHY parent 304 * clock selection bit and clock divider. 305 */ 306 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 307 (u32)~SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 308 pll_cfg1_init); 309 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, 310 (u32)~SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK, 311 pll_cfg2_init); 312 usleep_range(10000, 15000); 313 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG3_REG, 314 SUN8I_HDMI_PHY_PLL_CFG3_SOUT_DIV2); 315 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 316 SUN8I_HDMI_PHY_PLL_CFG1_PLLEN, 317 SUN8I_HDMI_PHY_PLL_CFG1_PLLEN); 318 msleep(100); 319 320 /* get B value */ 321 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); 322 val = (val & SUN8I_HDMI_PHY_ANA_STS_B_OUT_MSK) >> 323 SUN8I_HDMI_PHY_ANA_STS_B_OUT_SHIFT; 324 val = min(val + b_offset, (u32)0x3f); 325 326 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 327 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 | 328 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD, 329 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD1 | 330 SUN8I_HDMI_PHY_PLL_CFG1_REG_OD); 331 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 332 SUN8I_HDMI_PHY_PLL_CFG1_B_IN_MSK, 333 val << SUN8I_HDMI_PHY_PLL_CFG1_B_IN_SHIFT); 334 msleep(100); 335 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, ana_cfg1_end); 336 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG2_REG, ana_cfg2_init); 337 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, ana_cfg3_init); 338 339 return 0; 340 } 341 342 static int sun8i_hdmi_phy_config(struct dw_hdmi *hdmi, void *data, 343 struct drm_display_mode *mode) 344 { 345 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; 346 u32 val = 0; 347 348 if (mode->flags & DRM_MODE_FLAG_NHSYNC) 349 val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NHSYNC; 350 351 if (mode->flags & DRM_MODE_FLAG_NVSYNC) 352 val |= SUN8I_HDMI_PHY_DBG_CTRL_POL_NVSYNC; 353 354 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, 355 SUN8I_HDMI_PHY_DBG_CTRL_POL_MASK, val); 356 357 if (phy->variant->has_phy_clk) 358 clk_set_rate(phy->clk_phy, mode->crtc_clock * 1000); 359 360 return phy->variant->phy_config(hdmi, phy, mode->crtc_clock * 1000); 361 }; 362 363 static void sun8i_hdmi_phy_disable_a83t(struct dw_hdmi *hdmi, 364 struct sun8i_hdmi_phy *phy) 365 { 366 dw_hdmi_phy_gen2_txpwron(hdmi, 0); 367 dw_hdmi_phy_gen2_pddq(hdmi, 1); 368 369 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, 370 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 0); 371 } 372 373 static void sun8i_hdmi_phy_disable_h3(struct dw_hdmi *hdmi, 374 struct sun8i_hdmi_phy *phy) 375 { 376 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 377 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN | 378 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS | 379 SUN8I_HDMI_PHY_ANA_CFG1_ENBI); 380 regmap_write(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 0); 381 } 382 383 static void sun8i_hdmi_phy_disable(struct dw_hdmi *hdmi, void *data) 384 { 385 struct sun8i_hdmi_phy *phy = (struct sun8i_hdmi_phy *)data; 386 387 phy->variant->phy_disable(hdmi, phy); 388 } 389 390 static const struct dw_hdmi_phy_ops sun8i_hdmi_phy_ops = { 391 .init = &sun8i_hdmi_phy_config, 392 .disable = &sun8i_hdmi_phy_disable, 393 .read_hpd = &dw_hdmi_phy_read_hpd, 394 .update_hpd = &dw_hdmi_phy_update_hpd, 395 .setup_hpd = &dw_hdmi_phy_setup_hpd, 396 }; 397 398 static void sun8i_hdmi_phy_unlock(struct sun8i_hdmi_phy *phy) 399 { 400 /* enable read access to HDMI controller */ 401 regmap_write(phy->regs, SUN8I_HDMI_PHY_READ_EN_REG, 402 SUN8I_HDMI_PHY_READ_EN_MAGIC); 403 404 /* unscramble register offsets */ 405 regmap_write(phy->regs, SUN8I_HDMI_PHY_UNSCRAMBLE_REG, 406 SUN8I_HDMI_PHY_UNSCRAMBLE_MAGIC); 407 } 408 409 static void sun50i_hdmi_phy_init_h6(struct sun8i_hdmi_phy *phy) 410 { 411 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, 412 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN, 413 SUN8I_HDMI_PHY_REXT_CTRL_REXT_EN); 414 415 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_REXT_CTRL_REG, 416 0xffff0000, 0x80c00000); 417 } 418 419 static void sun8i_hdmi_phy_init_a83t(struct sun8i_hdmi_phy *phy) 420 { 421 sun8i_hdmi_phy_unlock(phy); 422 423 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, 424 SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK, 425 SUN8I_HDMI_PHY_DBG_CTRL_PX_LOCK); 426 427 /* 428 * Set PHY I2C address. It must match to the address set by 429 * dw_hdmi_phy_set_slave_addr(). 430 */ 431 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_DBG_CTRL_REG, 432 SUN8I_HDMI_PHY_DBG_CTRL_ADDR_MASK, 433 SUN8I_HDMI_PHY_DBG_CTRL_ADDR(I2C_ADDR)); 434 } 435 436 static void sun8i_hdmi_phy_init_h3(struct sun8i_hdmi_phy *phy) 437 { 438 unsigned int val; 439 440 sun8i_hdmi_phy_unlock(phy); 441 442 regmap_write(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 0); 443 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 444 SUN8I_HDMI_PHY_ANA_CFG1_ENBI, 445 SUN8I_HDMI_PHY_ANA_CFG1_ENBI); 446 udelay(5); 447 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 448 SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN, 449 SUN8I_HDMI_PHY_ANA_CFG1_TMDSCLK_EN); 450 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 451 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS, 452 SUN8I_HDMI_PHY_ANA_CFG1_ENVBS); 453 usleep_range(10, 20); 454 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 455 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN, 456 SUN8I_HDMI_PHY_ANA_CFG1_LDOEN); 457 udelay(5); 458 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 459 SUN8I_HDMI_PHY_ANA_CFG1_CKEN, 460 SUN8I_HDMI_PHY_ANA_CFG1_CKEN); 461 usleep_range(40, 100); 462 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 463 SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL, 464 SUN8I_HDMI_PHY_ANA_CFG1_ENRCAL); 465 usleep_range(100, 200); 466 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 467 SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG, 468 SUN8I_HDMI_PHY_ANA_CFG1_ENCALOG); 469 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 470 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | 471 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | 472 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2, 473 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS0 | 474 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS1 | 475 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDS2); 476 477 /* wait for calibration to finish */ 478 regmap_read_poll_timeout(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, val, 479 (val & SUN8I_HDMI_PHY_ANA_STS_RCALEND2D), 480 100, 2000); 481 482 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 483 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK, 484 SUN8I_HDMI_PHY_ANA_CFG1_ENP2S_TMDSCLK); 485 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG, 486 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | 487 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | 488 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | 489 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK, 490 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS0 | 491 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS1 | 492 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDS2 | 493 SUN8I_HDMI_PHY_ANA_CFG1_BIASEN_TMDSCLK); 494 495 /* enable DDC communication */ 496 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG3_REG, 497 SUN8I_HDMI_PHY_ANA_CFG3_SCLEN | 498 SUN8I_HDMI_PHY_ANA_CFG3_SDAEN, 499 SUN8I_HDMI_PHY_ANA_CFG3_SCLEN | 500 SUN8I_HDMI_PHY_ANA_CFG3_SDAEN); 501 502 /* reset PHY PLL clock parent */ 503 regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, 504 SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK, 0); 505 506 /* set HW control of CEC pins */ 507 regmap_write(phy->regs, SUN8I_HDMI_PHY_CEC_REG, 0); 508 509 /* read calibration data */ 510 regmap_read(phy->regs, SUN8I_HDMI_PHY_ANA_STS_REG, &val); 511 phy->rcal = (val & SUN8I_HDMI_PHY_ANA_STS_RCAL_MASK) >> 2; 512 } 513 514 void sun8i_hdmi_phy_init(struct sun8i_hdmi_phy *phy) 515 { 516 phy->variant->phy_init(phy); 517 } 518 519 void sun8i_hdmi_phy_set_ops(struct sun8i_hdmi_phy *phy, 520 struct dw_hdmi_plat_data *plat_data) 521 { 522 struct sun8i_hdmi_phy_variant *variant = phy->variant; 523 524 if (variant->is_custom_phy) { 525 plat_data->phy_ops = &sun8i_hdmi_phy_ops; 526 plat_data->phy_name = "sun8i_dw_hdmi_phy"; 527 plat_data->phy_data = phy; 528 } else { 529 plat_data->mpll_cfg = variant->mpll_cfg; 530 plat_data->cur_ctr = variant->cur_ctr; 531 plat_data->phy_config = variant->phy_cfg; 532 } 533 } 534 535 static struct regmap_config sun8i_hdmi_phy_regmap_config = { 536 .reg_bits = 32, 537 .val_bits = 32, 538 .reg_stride = 4, 539 .max_register = SUN8I_HDMI_PHY_CEC_REG, 540 .name = "phy" 541 }; 542 543 static const struct sun8i_hdmi_phy_variant sun8i_a83t_hdmi_phy = { 544 .is_custom_phy = true, 545 .phy_init = &sun8i_hdmi_phy_init_a83t, 546 .phy_disable = &sun8i_hdmi_phy_disable_a83t, 547 .phy_config = &sun8i_hdmi_phy_config_a83t, 548 }; 549 550 static const struct sun8i_hdmi_phy_variant sun8i_h3_hdmi_phy = { 551 .has_phy_clk = true, 552 .is_custom_phy = true, 553 .phy_init = &sun8i_hdmi_phy_init_h3, 554 .phy_disable = &sun8i_hdmi_phy_disable_h3, 555 .phy_config = &sun8i_hdmi_phy_config_h3, 556 }; 557 558 static const struct sun8i_hdmi_phy_variant sun8i_r40_hdmi_phy = { 559 .has_phy_clk = true, 560 .has_second_pll = true, 561 .is_custom_phy = true, 562 .phy_init = &sun8i_hdmi_phy_init_h3, 563 .phy_disable = &sun8i_hdmi_phy_disable_h3, 564 .phy_config = &sun8i_hdmi_phy_config_h3, 565 }; 566 567 static const struct sun8i_hdmi_phy_variant sun50i_a64_hdmi_phy = { 568 .has_phy_clk = true, 569 .is_custom_phy = true, 570 .phy_init = &sun8i_hdmi_phy_init_h3, 571 .phy_disable = &sun8i_hdmi_phy_disable_h3, 572 .phy_config = &sun8i_hdmi_phy_config_h3, 573 }; 574 575 static const struct sun8i_hdmi_phy_variant sun50i_h6_hdmi_phy = { 576 .cur_ctr = sun50i_h6_cur_ctr, 577 .mpll_cfg = sun50i_h6_mpll_cfg, 578 .phy_cfg = sun50i_h6_phy_config, 579 .phy_init = &sun50i_hdmi_phy_init_h6, 580 }; 581 582 static const struct of_device_id sun8i_hdmi_phy_of_table[] = { 583 { 584 .compatible = "allwinner,sun8i-a83t-hdmi-phy", 585 .data = &sun8i_a83t_hdmi_phy, 586 }, 587 { 588 .compatible = "allwinner,sun8i-h3-hdmi-phy", 589 .data = &sun8i_h3_hdmi_phy, 590 }, 591 { 592 .compatible = "allwinner,sun8i-r40-hdmi-phy", 593 .data = &sun8i_r40_hdmi_phy, 594 }, 595 { 596 .compatible = "allwinner,sun50i-a64-hdmi-phy", 597 .data = &sun50i_a64_hdmi_phy, 598 }, 599 { 600 .compatible = "allwinner,sun50i-h6-hdmi-phy", 601 .data = &sun50i_h6_hdmi_phy, 602 }, 603 { /* sentinel */ } 604 }; 605 606 int sun8i_hdmi_phy_probe(struct sun8i_dw_hdmi *hdmi, struct device_node *node) 607 { 608 const struct of_device_id *match; 609 struct device *dev = hdmi->dev; 610 struct sun8i_hdmi_phy *phy; 611 struct resource res; 612 void __iomem *regs; 613 int ret; 614 615 match = of_match_node(sun8i_hdmi_phy_of_table, node); 616 if (!match) { 617 dev_err(dev, "Incompatible HDMI PHY\n"); 618 return -EINVAL; 619 } 620 621 phy = devm_kzalloc(dev, sizeof(*phy), GFP_KERNEL); 622 if (!phy) 623 return -ENOMEM; 624 625 phy->variant = (struct sun8i_hdmi_phy_variant *)match->data; 626 627 ret = of_address_to_resource(node, 0, &res); 628 if (ret) { 629 dev_err(dev, "phy: Couldn't get our resources\n"); 630 return ret; 631 } 632 633 regs = devm_ioremap_resource(dev, &res); 634 if (IS_ERR(regs)) { 635 dev_err(dev, "Couldn't map the HDMI PHY registers\n"); 636 return PTR_ERR(regs); 637 } 638 639 phy->regs = devm_regmap_init_mmio(dev, regs, 640 &sun8i_hdmi_phy_regmap_config); 641 if (IS_ERR(phy->regs)) { 642 dev_err(dev, "Couldn't create the HDMI PHY regmap\n"); 643 return PTR_ERR(phy->regs); 644 } 645 646 phy->clk_bus = of_clk_get_by_name(node, "bus"); 647 if (IS_ERR(phy->clk_bus)) { 648 dev_err(dev, "Could not get bus clock\n"); 649 return PTR_ERR(phy->clk_bus); 650 } 651 652 phy->clk_mod = of_clk_get_by_name(node, "mod"); 653 if (IS_ERR(phy->clk_mod)) { 654 dev_err(dev, "Could not get mod clock\n"); 655 ret = PTR_ERR(phy->clk_mod); 656 goto err_put_clk_bus; 657 } 658 659 if (phy->variant->has_phy_clk) { 660 phy->clk_pll0 = of_clk_get_by_name(node, "pll-0"); 661 if (IS_ERR(phy->clk_pll0)) { 662 dev_err(dev, "Could not get pll-0 clock\n"); 663 ret = PTR_ERR(phy->clk_pll0); 664 goto err_put_clk_mod; 665 } 666 667 if (phy->variant->has_second_pll) { 668 phy->clk_pll1 = of_clk_get_by_name(node, "pll-1"); 669 if (IS_ERR(phy->clk_pll1)) { 670 dev_err(dev, "Could not get pll-1 clock\n"); 671 ret = PTR_ERR(phy->clk_pll1); 672 goto err_put_clk_pll0; 673 } 674 } 675 676 ret = sun8i_phy_clk_create(phy, dev, 677 phy->variant->has_second_pll); 678 if (ret) { 679 dev_err(dev, "Couldn't create the PHY clock\n"); 680 goto err_put_clk_pll1; 681 } 682 683 clk_prepare_enable(phy->clk_phy); 684 } 685 686 phy->rst_phy = of_reset_control_get_shared(node, "phy"); 687 if (IS_ERR(phy->rst_phy)) { 688 dev_err(dev, "Could not get phy reset control\n"); 689 ret = PTR_ERR(phy->rst_phy); 690 goto err_disable_clk_phy; 691 } 692 693 ret = reset_control_deassert(phy->rst_phy); 694 if (ret) { 695 dev_err(dev, "Cannot deassert phy reset control: %d\n", ret); 696 goto err_put_rst_phy; 697 } 698 699 ret = clk_prepare_enable(phy->clk_bus); 700 if (ret) { 701 dev_err(dev, "Cannot enable bus clock: %d\n", ret); 702 goto err_deassert_rst_phy; 703 } 704 705 ret = clk_prepare_enable(phy->clk_mod); 706 if (ret) { 707 dev_err(dev, "Cannot enable mod clock: %d\n", ret); 708 goto err_disable_clk_bus; 709 } 710 711 hdmi->phy = phy; 712 713 return 0; 714 715 err_disable_clk_bus: 716 clk_disable_unprepare(phy->clk_bus); 717 err_deassert_rst_phy: 718 reset_control_assert(phy->rst_phy); 719 err_put_rst_phy: 720 reset_control_put(phy->rst_phy); 721 err_disable_clk_phy: 722 clk_disable_unprepare(phy->clk_phy); 723 err_put_clk_pll1: 724 clk_put(phy->clk_pll1); 725 err_put_clk_pll0: 726 clk_put(phy->clk_pll0); 727 err_put_clk_mod: 728 clk_put(phy->clk_mod); 729 err_put_clk_bus: 730 clk_put(phy->clk_bus); 731 732 return ret; 733 } 734 735 void sun8i_hdmi_phy_remove(struct sun8i_dw_hdmi *hdmi) 736 { 737 struct sun8i_hdmi_phy *phy = hdmi->phy; 738 739 clk_disable_unprepare(phy->clk_mod); 740 clk_disable_unprepare(phy->clk_bus); 741 clk_disable_unprepare(phy->clk_phy); 742 743 reset_control_assert(phy->rst_phy); 744 745 reset_control_put(phy->rst_phy); 746 747 clk_put(phy->clk_pll0); 748 clk_put(phy->clk_pll1); 749 clk_put(phy->clk_mod); 750 clk_put(phy->clk_bus); 751 } 752