1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> 4 */ 5 6 #include <linux/component.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 11 #include <drm/drm_crtc_helper.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_simple_kms_helper.h> 14 15 #include "sun8i_dw_hdmi.h" 16 #include "sun8i_tcon_top.h" 17 18 static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder, 19 struct drm_display_mode *mode, 20 struct drm_display_mode *adj_mode) 21 { 22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); 23 24 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); 25 } 26 27 static const struct drm_encoder_helper_funcs 28 sun8i_dw_hdmi_encoder_helper_funcs = { 29 .mode_set = sun8i_dw_hdmi_encoder_mode_set, 30 }; 31 32 static enum drm_mode_status 33 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, 34 const struct drm_display_info *info, 35 const struct drm_display_mode *mode) 36 { 37 if (mode->clock > 297000) 38 return MODE_CLOCK_HIGH; 39 40 return MODE_OK; 41 } 42 43 static enum drm_mode_status 44 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, 45 const struct drm_display_info *info, 46 const struct drm_display_mode *mode) 47 { 48 /* 49 * Controller support maximum of 594 MHz, which correlates to 50 * 4K@60Hz 4:4:4 or RGB. 51 */ 52 if (mode->clock > 594000) 53 return MODE_CLOCK_HIGH; 54 55 return MODE_OK; 56 } 57 58 static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node) 59 { 60 return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 61 !!of_match_node(sun8i_tcon_top_of_table, node); 62 } 63 64 static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, 65 struct device_node *node) 66 { 67 struct device_node *port, *ep, *remote, *remote_port; 68 u32 crtcs = 0; 69 70 remote = of_graph_get_remote_node(node, 0, -1); 71 if (!remote) 72 return 0; 73 74 if (sun8i_dw_hdmi_node_is_tcon_top(remote)) { 75 port = of_graph_get_port_by_id(remote, 4); 76 if (!port) 77 goto crtcs_exit; 78 79 for_each_child_of_node(port, ep) { 80 remote_port = of_graph_get_remote_port(ep); 81 if (remote_port) { 82 crtcs |= drm_of_crtc_port_mask(drm, remote_port); 83 of_node_put(remote_port); 84 } 85 } 86 } else { 87 crtcs = drm_of_find_possible_crtcs(drm, node); 88 } 89 90 crtcs_exit: 91 of_node_put(remote); 92 93 return crtcs; 94 } 95 96 static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev, 97 struct platform_device **pdev_out) 98 { 99 struct platform_device *pdev; 100 struct device_node *remote; 101 102 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 103 if (!remote) 104 return -ENODEV; 105 106 if (!of_device_is_compatible(remote, "hdmi-connector")) { 107 of_node_put(remote); 108 return -ENODEV; 109 } 110 111 pdev = of_find_device_by_node(remote); 112 of_node_put(remote); 113 if (!pdev) 114 return -ENODEV; 115 116 *pdev_out = pdev; 117 return 0; 118 } 119 120 static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, 121 void *data) 122 { 123 struct platform_device *pdev = to_platform_device(dev), *connector_pdev; 124 struct dw_hdmi_plat_data *plat_data; 125 struct drm_device *drm = data; 126 struct device_node *phy_node; 127 struct drm_encoder *encoder; 128 struct sun8i_dw_hdmi *hdmi; 129 int ret; 130 131 if (!pdev->dev.of_node) 132 return -ENODEV; 133 134 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 135 if (!hdmi) 136 return -ENOMEM; 137 138 plat_data = &hdmi->plat_data; 139 hdmi->dev = &pdev->dev; 140 encoder = &hdmi->encoder; 141 142 hdmi->quirks = of_device_get_match_data(dev); 143 144 encoder->possible_crtcs = 145 sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node); 146 /* 147 * If we failed to find the CRTC(s) which this encoder is 148 * supposed to be connected to, it's because the CRTC has 149 * not been registered yet. Defer probing, and hope that 150 * the required CRTC is added later. 151 */ 152 if (encoder->possible_crtcs == 0) 153 return -EPROBE_DEFER; 154 155 hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl"); 156 if (IS_ERR(hdmi->rst_ctrl)) 157 return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl), 158 "Could not get ctrl reset control\n"); 159 160 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); 161 if (IS_ERR(hdmi->clk_tmds)) 162 return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds), 163 "Couldn't get the tmds clock\n"); 164 165 hdmi->regulator = devm_regulator_get(dev, "hvcc"); 166 if (IS_ERR(hdmi->regulator)) 167 return dev_err_probe(dev, PTR_ERR(hdmi->regulator), 168 "Couldn't get regulator\n"); 169 170 ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev); 171 if (!ret) { 172 hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev, 173 "ddc-en", GPIOD_OUT_HIGH); 174 platform_device_put(connector_pdev); 175 176 if (IS_ERR(hdmi->ddc_en)) { 177 dev_err(dev, "Couldn't get ddc-en gpio\n"); 178 return PTR_ERR(hdmi->ddc_en); 179 } 180 } 181 182 ret = regulator_enable(hdmi->regulator); 183 if (ret) { 184 dev_err(dev, "Failed to enable regulator\n"); 185 goto err_unref_ddc_en; 186 } 187 188 gpiod_set_value(hdmi->ddc_en, 1); 189 190 ret = reset_control_deassert(hdmi->rst_ctrl); 191 if (ret) { 192 dev_err(dev, "Could not deassert ctrl reset control\n"); 193 goto err_disable_ddc_en; 194 } 195 196 ret = clk_prepare_enable(hdmi->clk_tmds); 197 if (ret) { 198 dev_err(dev, "Could not enable tmds clock\n"); 199 goto err_assert_ctrl_reset; 200 } 201 202 phy_node = of_parse_phandle(dev->of_node, "phys", 0); 203 if (!phy_node) { 204 dev_err(dev, "Can't found PHY phandle\n"); 205 ret = -EINVAL; 206 goto err_disable_clk_tmds; 207 } 208 209 ret = sun8i_hdmi_phy_get(hdmi, phy_node); 210 of_node_put(phy_node); 211 if (ret) { 212 dev_err(dev, "Couldn't get the HDMI PHY\n"); 213 goto err_disable_clk_tmds; 214 } 215 216 drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs); 217 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 218 219 sun8i_hdmi_phy_init(hdmi->phy); 220 221 plat_data->mode_valid = hdmi->quirks->mode_valid; 222 plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe; 223 sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data); 224 225 platform_set_drvdata(pdev, hdmi); 226 227 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); 228 229 /* 230 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), 231 * which would have called the encoder cleanup. Do it manually. 232 */ 233 if (IS_ERR(hdmi->hdmi)) { 234 ret = PTR_ERR(hdmi->hdmi); 235 goto cleanup_encoder; 236 } 237 238 return 0; 239 240 cleanup_encoder: 241 drm_encoder_cleanup(encoder); 242 err_disable_clk_tmds: 243 clk_disable_unprepare(hdmi->clk_tmds); 244 err_assert_ctrl_reset: 245 reset_control_assert(hdmi->rst_ctrl); 246 err_disable_ddc_en: 247 gpiod_set_value(hdmi->ddc_en, 0); 248 regulator_disable(hdmi->regulator); 249 err_unref_ddc_en: 250 if (hdmi->ddc_en) 251 gpiod_put(hdmi->ddc_en); 252 253 return ret; 254 } 255 256 static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, 257 void *data) 258 { 259 struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev); 260 261 dw_hdmi_unbind(hdmi->hdmi); 262 clk_disable_unprepare(hdmi->clk_tmds); 263 reset_control_assert(hdmi->rst_ctrl); 264 gpiod_set_value(hdmi->ddc_en, 0); 265 regulator_disable(hdmi->regulator); 266 267 if (hdmi->ddc_en) 268 gpiod_put(hdmi->ddc_en); 269 } 270 271 static const struct component_ops sun8i_dw_hdmi_ops = { 272 .bind = sun8i_dw_hdmi_bind, 273 .unbind = sun8i_dw_hdmi_unbind, 274 }; 275 276 static int sun8i_dw_hdmi_probe(struct platform_device *pdev) 277 { 278 return component_add(&pdev->dev, &sun8i_dw_hdmi_ops); 279 } 280 281 static int sun8i_dw_hdmi_remove(struct platform_device *pdev) 282 { 283 component_del(&pdev->dev, &sun8i_dw_hdmi_ops); 284 285 return 0; 286 } 287 288 static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = { 289 .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, 290 }; 291 292 static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { 293 .mode_valid = sun8i_dw_hdmi_mode_valid_h6, 294 .use_drm_infoframe = true, 295 }; 296 297 static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = { 298 { 299 .compatible = "allwinner,sun8i-a83t-dw-hdmi", 300 .data = &sun8i_a83t_quirks, 301 }, 302 { 303 .compatible = "allwinner,sun50i-h6-dw-hdmi", 304 .data = &sun50i_h6_quirks, 305 }, 306 { /* sentinel */ }, 307 }; 308 MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids); 309 310 static struct platform_driver sun8i_dw_hdmi_pltfm_driver = { 311 .probe = sun8i_dw_hdmi_probe, 312 .remove = sun8i_dw_hdmi_remove, 313 .driver = { 314 .name = "sun8i-dw-hdmi", 315 .of_match_table = sun8i_dw_hdmi_dt_ids, 316 }, 317 }; 318 319 static int __init sun8i_dw_hdmi_init(void) 320 { 321 int ret; 322 323 ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver); 324 if (ret) 325 return ret; 326 327 ret = platform_driver_register(&sun8i_hdmi_phy_driver); 328 if (ret) { 329 platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver); 330 return ret; 331 } 332 333 return ret; 334 } 335 336 static void __exit sun8i_dw_hdmi_exit(void) 337 { 338 platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver); 339 platform_driver_unregister(&sun8i_hdmi_phy_driver); 340 } 341 342 module_init(sun8i_dw_hdmi_init); 343 module_exit(sun8i_dw_hdmi_exit); 344 345 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>"); 346 MODULE_DESCRIPTION("Allwinner DW HDMI bridge"); 347 MODULE_LICENSE("GPL"); 348