1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> 4 */ 5 6 #include <linux/component.h> 7 #include <linux/module.h> 8 #include <linux/of_device.h> 9 #include <linux/platform_device.h> 10 11 #include <drm/drm_crtc_helper.h> 12 #include <drm/drm_of.h> 13 #include <drm/drm_simple_kms_helper.h> 14 15 #include "sun8i_dw_hdmi.h" 16 #include "sun8i_tcon_top.h" 17 18 static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder, 19 struct drm_display_mode *mode, 20 struct drm_display_mode *adj_mode) 21 { 22 struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder); 23 24 if (hdmi->quirks->set_rate) 25 clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000); 26 } 27 28 static const struct drm_encoder_helper_funcs 29 sun8i_dw_hdmi_encoder_helper_funcs = { 30 .mode_set = sun8i_dw_hdmi_encoder_mode_set, 31 }; 32 33 static enum drm_mode_status 34 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data, 35 const struct drm_display_info *info, 36 const struct drm_display_mode *mode) 37 { 38 if (mode->clock > 297000) 39 return MODE_CLOCK_HIGH; 40 41 return MODE_OK; 42 } 43 44 static enum drm_mode_status 45 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data, 46 const struct drm_display_info *info, 47 const struct drm_display_mode *mode) 48 { 49 /* 50 * Controller support maximum of 594 MHz, which correlates to 51 * 4K@60Hz 4:4:4 or RGB. However, for frequencies greater than 52 * 340 MHz scrambling has to be enabled. Because scrambling is 53 * not yet implemented, just limit to 340 MHz for now. 54 */ 55 if (mode->clock > 340000) 56 return MODE_CLOCK_HIGH; 57 58 return MODE_OK; 59 } 60 61 static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node) 62 { 63 return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 64 !!of_match_node(sun8i_tcon_top_of_table, node); 65 } 66 67 static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm, 68 struct device_node *node) 69 { 70 struct device_node *port, *ep, *remote, *remote_port; 71 u32 crtcs = 0; 72 73 remote = of_graph_get_remote_node(node, 0, -1); 74 if (!remote) 75 return 0; 76 77 if (sun8i_dw_hdmi_node_is_tcon_top(remote)) { 78 port = of_graph_get_port_by_id(remote, 4); 79 if (!port) 80 goto crtcs_exit; 81 82 for_each_child_of_node(port, ep) { 83 remote_port = of_graph_get_remote_port(ep); 84 if (remote_port) { 85 crtcs |= drm_of_crtc_port_mask(drm, remote_port); 86 of_node_put(remote_port); 87 } 88 } 89 } else { 90 crtcs = drm_of_find_possible_crtcs(drm, node); 91 } 92 93 crtcs_exit: 94 of_node_put(remote); 95 96 return crtcs; 97 } 98 99 static int sun8i_dw_hdmi_find_connector_pdev(struct device *dev, 100 struct platform_device **pdev_out) 101 { 102 struct platform_device *pdev; 103 struct device_node *remote; 104 105 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 106 if (!remote) 107 return -ENODEV; 108 109 if (!of_device_is_compatible(remote, "hdmi-connector")) { 110 of_node_put(remote); 111 return -ENODEV; 112 } 113 114 pdev = of_find_device_by_node(remote); 115 of_node_put(remote); 116 if (!pdev) 117 return -ENODEV; 118 119 *pdev_out = pdev; 120 return 0; 121 } 122 123 static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master, 124 void *data) 125 { 126 struct platform_device *pdev = to_platform_device(dev), *connector_pdev; 127 struct dw_hdmi_plat_data *plat_data; 128 struct drm_device *drm = data; 129 struct device_node *phy_node; 130 struct drm_encoder *encoder; 131 struct sun8i_dw_hdmi *hdmi; 132 int ret; 133 134 if (!pdev->dev.of_node) 135 return -ENODEV; 136 137 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL); 138 if (!hdmi) 139 return -ENOMEM; 140 141 plat_data = &hdmi->plat_data; 142 hdmi->dev = &pdev->dev; 143 encoder = &hdmi->encoder; 144 145 hdmi->quirks = of_device_get_match_data(dev); 146 147 encoder->possible_crtcs = 148 sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node); 149 /* 150 * If we failed to find the CRTC(s) which this encoder is 151 * supposed to be connected to, it's because the CRTC has 152 * not been registered yet. Defer probing, and hope that 153 * the required CRTC is added later. 154 */ 155 if (encoder->possible_crtcs == 0) 156 return -EPROBE_DEFER; 157 158 hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl"); 159 if (IS_ERR(hdmi->rst_ctrl)) { 160 dev_err(dev, "Could not get ctrl reset control\n"); 161 return PTR_ERR(hdmi->rst_ctrl); 162 } 163 164 hdmi->clk_tmds = devm_clk_get(dev, "tmds"); 165 if (IS_ERR(hdmi->clk_tmds)) { 166 dev_err(dev, "Couldn't get the tmds clock\n"); 167 return PTR_ERR(hdmi->clk_tmds); 168 } 169 170 hdmi->regulator = devm_regulator_get(dev, "hvcc"); 171 if (IS_ERR(hdmi->regulator)) { 172 dev_err(dev, "Couldn't get regulator\n"); 173 return PTR_ERR(hdmi->regulator); 174 } 175 176 ret = sun8i_dw_hdmi_find_connector_pdev(dev, &connector_pdev); 177 if (!ret) { 178 hdmi->ddc_en = gpiod_get_optional(&connector_pdev->dev, 179 "ddc-en", GPIOD_OUT_HIGH); 180 platform_device_put(connector_pdev); 181 182 if (IS_ERR(hdmi->ddc_en)) { 183 dev_err(dev, "Couldn't get ddc-en gpio\n"); 184 return PTR_ERR(hdmi->ddc_en); 185 } 186 } 187 188 ret = regulator_enable(hdmi->regulator); 189 if (ret) { 190 dev_err(dev, "Failed to enable regulator\n"); 191 goto err_unref_ddc_en; 192 } 193 194 gpiod_set_value(hdmi->ddc_en, 1); 195 196 ret = reset_control_deassert(hdmi->rst_ctrl); 197 if (ret) { 198 dev_err(dev, "Could not deassert ctrl reset control\n"); 199 goto err_disable_ddc_en; 200 } 201 202 ret = clk_prepare_enable(hdmi->clk_tmds); 203 if (ret) { 204 dev_err(dev, "Could not enable tmds clock\n"); 205 goto err_assert_ctrl_reset; 206 } 207 208 phy_node = of_parse_phandle(dev->of_node, "phys", 0); 209 if (!phy_node) { 210 dev_err(dev, "Can't found PHY phandle\n"); 211 goto err_disable_clk_tmds; 212 } 213 214 ret = sun8i_hdmi_phy_probe(hdmi, phy_node); 215 of_node_put(phy_node); 216 if (ret) { 217 dev_err(dev, "Couldn't get the HDMI PHY\n"); 218 goto err_disable_clk_tmds; 219 } 220 221 drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs); 222 drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS); 223 224 sun8i_hdmi_phy_init(hdmi->phy); 225 226 plat_data->mode_valid = hdmi->quirks->mode_valid; 227 plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe; 228 sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data); 229 230 platform_set_drvdata(pdev, hdmi); 231 232 hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data); 233 234 /* 235 * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(), 236 * which would have called the encoder cleanup. Do it manually. 237 */ 238 if (IS_ERR(hdmi->hdmi)) { 239 ret = PTR_ERR(hdmi->hdmi); 240 goto cleanup_encoder; 241 } 242 243 return 0; 244 245 cleanup_encoder: 246 drm_encoder_cleanup(encoder); 247 sun8i_hdmi_phy_remove(hdmi); 248 err_disable_clk_tmds: 249 clk_disable_unprepare(hdmi->clk_tmds); 250 err_assert_ctrl_reset: 251 reset_control_assert(hdmi->rst_ctrl); 252 err_disable_ddc_en: 253 gpiod_set_value(hdmi->ddc_en, 0); 254 regulator_disable(hdmi->regulator); 255 err_unref_ddc_en: 256 if (hdmi->ddc_en) 257 gpiod_put(hdmi->ddc_en); 258 259 return ret; 260 } 261 262 static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master, 263 void *data) 264 { 265 struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev); 266 267 dw_hdmi_unbind(hdmi->hdmi); 268 sun8i_hdmi_phy_remove(hdmi); 269 clk_disable_unprepare(hdmi->clk_tmds); 270 reset_control_assert(hdmi->rst_ctrl); 271 gpiod_set_value(hdmi->ddc_en, 0); 272 regulator_disable(hdmi->regulator); 273 274 if (hdmi->ddc_en) 275 gpiod_put(hdmi->ddc_en); 276 } 277 278 static const struct component_ops sun8i_dw_hdmi_ops = { 279 .bind = sun8i_dw_hdmi_bind, 280 .unbind = sun8i_dw_hdmi_unbind, 281 }; 282 283 static int sun8i_dw_hdmi_probe(struct platform_device *pdev) 284 { 285 return component_add(&pdev->dev, &sun8i_dw_hdmi_ops); 286 } 287 288 static int sun8i_dw_hdmi_remove(struct platform_device *pdev) 289 { 290 component_del(&pdev->dev, &sun8i_dw_hdmi_ops); 291 292 return 0; 293 } 294 295 static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = { 296 .mode_valid = sun8i_dw_hdmi_mode_valid_a83t, 297 .set_rate = true, 298 }; 299 300 static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = { 301 .mode_valid = sun8i_dw_hdmi_mode_valid_h6, 302 .use_drm_infoframe = true, 303 }; 304 305 static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = { 306 { 307 .compatible = "allwinner,sun8i-a83t-dw-hdmi", 308 .data = &sun8i_a83t_quirks, 309 }, 310 { 311 .compatible = "allwinner,sun50i-h6-dw-hdmi", 312 .data = &sun50i_h6_quirks, 313 }, 314 { /* sentinel */ }, 315 }; 316 MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids); 317 318 static struct platform_driver sun8i_dw_hdmi_pltfm_driver = { 319 .probe = sun8i_dw_hdmi_probe, 320 .remove = sun8i_dw_hdmi_remove, 321 .driver = { 322 .name = "sun8i-dw-hdmi", 323 .of_match_table = sun8i_dw_hdmi_dt_ids, 324 }, 325 }; 326 module_platform_driver(sun8i_dw_hdmi_pltfm_driver); 327 328 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>"); 329 MODULE_DESCRIPTION("Allwinner DW HDMI bridge"); 330 MODULE_LICENSE("GPL"); 331