1 /* 2 * Copyright (C) Jernej Skrabec <jernej.skrabec@siol.net> 3 * 4 * This program is free software; you can redistribute it and/or 5 * modify it under the terms of the GNU General Public License as 6 * published by the Free Software Foundation; either version 2 of 7 * the License, or (at your option) any later version. 8 */ 9 10 #include <drm/drmP.h> 11 12 #include "sun8i_csc.h" 13 #include "sun8i_mixer.h" 14 15 static const u32 ccsc_base[2][2] = { 16 {CCSC00_OFFSET, CCSC01_OFFSET}, 17 {CCSC10_OFFSET, CCSC11_OFFSET}, 18 }; 19 20 /* 21 * Factors are in two's complement format, 10 bits for fractinal part. 22 * First tree values in each line are multiplication factor and last 23 * value is constant, which is added at the end. 24 */ 25 static const u32 yuv2rgb[] = { 26 0x000004A8, 0x00000000, 0x00000662, 0xFFFC845A, 27 0x000004A8, 0xFFFFFE6F, 0xFFFFFCBF, 0x00021DF4, 28 0x000004A8, 0x00000813, 0x00000000, 0xFFFBAC4A, 29 }; 30 31 static const u32 yvu2rgb[] = { 32 0x000004A8, 0x00000662, 0x00000000, 0xFFFC845A, 33 0x000004A8, 0xFFFFFCBF, 0xFFFFFE6F, 0x00021DF4, 34 0x000004A8, 0x00000000, 0x00000813, 0xFFFBAC4A, 35 }; 36 37 /* 38 * DE3 has a bit different CSC units. Factors are in two's complement format. 39 * First three factors in a row are multiplication factors which have 17 bits 40 * for fractional part. Fourth value in a row is comprised of two factors. 41 * Upper 16 bits represents difference, which is subtracted from the input 42 * value before multiplication and lower 16 bits represents constant, which 43 * is addes at the end. 44 * 45 * x' = c00 * (x + d0) + c01 * (y + d1) + c02 * (z + d2) + const0 46 * y' = c10 * (x + d0) + c11 * (y + d1) + c12 * (z + d2) + const1 47 * z' = c20 * (x + d0) + c21 * (y + d1) + c22 * (z + d2) + const2 48 * 49 * Please note that above formula is true only for Blender CSC. Other DE3 CSC 50 * units takes only positive value for difference. From what can be deducted 51 * from BSP driver code, those units probably automatically assume that 52 * difference has to be subtracted. 53 * 54 * Layout of factors in table: 55 * c00 c01 c02 [d0 const0] 56 * c10 c11 c12 [d1 const1] 57 * c20 c21 c22 [d2 const2] 58 */ 59 60 static const u32 yuv2rgb_de3[] = { 61 0x0002542a, 0x00000000, 0x0003312a, 0xffc00000, 62 0x0002542a, 0xffff376b, 0xfffe5fc3, 0xfe000000, 63 0x0002542a, 0x000408d3, 0x00000000, 0xfe000000, 64 }; 65 66 static const u32 yvu2rgb_de3[] = { 67 0x0002542a, 0x0003312a, 0x00000000, 0xffc00000, 68 0x0002542a, 0xfffe5fc3, 0xffff376b, 0xfe000000, 69 0x0002542a, 0x00000000, 0x000408d3, 0xfe000000, 70 }; 71 72 static void sun8i_csc_set_coefficients(struct regmap *map, u32 base, 73 enum sun8i_csc_mode mode) 74 { 75 const u32 *table; 76 int i, data; 77 78 switch (mode) { 79 case SUN8I_CSC_MODE_YUV2RGB: 80 table = yuv2rgb; 81 break; 82 case SUN8I_CSC_MODE_YVU2RGB: 83 table = yvu2rgb; 84 break; 85 default: 86 DRM_WARN("Wrong CSC mode specified.\n"); 87 return; 88 } 89 90 for (i = 0; i < 12; i++) { 91 data = table[i]; 92 /* For some reason, 0x200 must be added to constant parts */ 93 if (((i + 1) & 3) == 0) 94 data += 0x200; 95 regmap_write(map, SUN8I_CSC_COEFF(base, i), data); 96 } 97 } 98 99 static void sun8i_de3_ccsc_set_coefficients(struct regmap *map, int layer, 100 enum sun8i_csc_mode mode) 101 { 102 const u32 *table; 103 u32 base_reg; 104 105 switch (mode) { 106 case SUN8I_CSC_MODE_YUV2RGB: 107 table = yuv2rgb_de3; 108 break; 109 case SUN8I_CSC_MODE_YVU2RGB: 110 table = yvu2rgb_de3; 111 break; 112 default: 113 DRM_WARN("Wrong CSC mode specified.\n"); 114 return; 115 } 116 117 base_reg = SUN50I_MIXER_BLEND_CSC_COEFF(DE3_BLD_BASE, layer, 0, 0); 118 regmap_bulk_write(map, base_reg, table, 12); 119 } 120 121 static void sun8i_csc_enable(struct regmap *map, u32 base, bool enable) 122 { 123 u32 val; 124 125 if (enable) 126 val = SUN8I_CSC_CTRL_EN; 127 else 128 val = 0; 129 130 regmap_update_bits(map, SUN8I_CSC_CTRL(base), SUN8I_CSC_CTRL_EN, val); 131 } 132 133 static void sun8i_de3_ccsc_enable(struct regmap *map, int layer, bool enable) 134 { 135 u32 val, mask; 136 137 mask = SUN50I_MIXER_BLEND_CSC_CTL_EN(layer); 138 139 if (enable) 140 val = mask; 141 else 142 val = 0; 143 144 regmap_update_bits(map, SUN50I_MIXER_BLEND_CSC_CTL(DE3_BLD_BASE), 145 mask, val); 146 } 147 148 void sun8i_csc_set_ccsc_coefficients(struct sun8i_mixer *mixer, int layer, 149 enum sun8i_csc_mode mode) 150 { 151 u32 base; 152 153 if (mixer->cfg->is_de3) { 154 sun8i_de3_ccsc_set_coefficients(mixer->engine.regs, 155 layer, mode); 156 return; 157 } 158 159 base = ccsc_base[mixer->cfg->ccsc][layer]; 160 161 sun8i_csc_set_coefficients(mixer->engine.regs, base, mode); 162 } 163 164 void sun8i_csc_enable_ccsc(struct sun8i_mixer *mixer, int layer, bool enable) 165 { 166 u32 base; 167 168 if (mixer->cfg->is_de3) { 169 sun8i_de3_ccsc_enable(mixer->engine.regs, layer, enable); 170 return; 171 } 172 173 base = ccsc_base[mixer->cfg->ccsc][layer]; 174 175 sun8i_csc_enable(mixer->engine.regs, base, enable); 176 } 177