1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (c) 2016 Allwinnertech Co., Ltd. 4 * Copyright (C) 2017-2018 Bootlin 5 * 6 * Maxime Ripard <maxime.ripard@bootlin.com> 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/component.h> 11 #include <linux/crc-ccitt.h> 12 #include <linux/of_address.h> 13 #include <linux/pm_runtime.h> 14 #include <linux/regmap.h> 15 #include <linux/reset.h> 16 #include <linux/slab.h> 17 18 #include <linux/phy/phy.h> 19 #include <linux/phy/phy-mipi-dphy.h> 20 21 #include <drm/drmP.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_mipi_dsi.h> 24 #include <drm/drm_panel.h> 25 #include <drm/drm_probe_helper.h> 26 27 #include "sun4i_crtc.h" 28 #include "sun4i_drv.h" 29 #include "sun4i_tcon.h" 30 #include "sun6i_mipi_dsi.h" 31 32 #include <video/mipi_display.h> 33 34 #define SUN6I_DSI_CTL_REG 0x000 35 #define SUN6I_DSI_CTL_EN BIT(0) 36 37 #define SUN6I_DSI_BASIC_CTL_REG 0x00c 38 #define SUN6I_DSI_BASIC_CTL_TRAIL_INV(n) (((n) & 0xf) << 4) 39 #define SUN6I_DSI_BASIC_CTL_TRAIL_FILL BIT(3) 40 #define SUN6I_DSI_BASIC_CTL_HBP_DIS BIT(2) 41 #define SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS BIT(1) 42 #define SUN6I_DSI_BASIC_CTL_VIDEO_BURST BIT(0) 43 44 #define SUN6I_DSI_BASIC_CTL0_REG 0x010 45 #define SUN6I_DSI_BASIC_CTL0_HS_EOTP_EN BIT(18) 46 #define SUN6I_DSI_BASIC_CTL0_CRC_EN BIT(17) 47 #define SUN6I_DSI_BASIC_CTL0_ECC_EN BIT(16) 48 #define SUN6I_DSI_BASIC_CTL0_INST_ST BIT(0) 49 50 #define SUN6I_DSI_BASIC_CTL1_REG 0x014 51 #define SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(n) (((n) & 0x1fff) << 4) 52 #define SUN6I_DSI_BASIC_CTL1_VIDEO_FILL BIT(2) 53 #define SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION BIT(1) 54 #define SUN6I_DSI_BASIC_CTL1_VIDEO_MODE BIT(0) 55 56 #define SUN6I_DSI_BASIC_SIZE0_REG 0x018 57 #define SUN6I_DSI_BASIC_SIZE0_VBP(n) (((n) & 0xfff) << 16) 58 #define SUN6I_DSI_BASIC_SIZE0_VSA(n) ((n) & 0xfff) 59 60 #define SUN6I_DSI_BASIC_SIZE1_REG 0x01c 61 #define SUN6I_DSI_BASIC_SIZE1_VT(n) (((n) & 0xfff) << 16) 62 #define SUN6I_DSI_BASIC_SIZE1_VACT(n) ((n) & 0xfff) 63 64 #define SUN6I_DSI_INST_FUNC_REG(n) (0x020 + (n) * 0x04) 65 #define SUN6I_DSI_INST_FUNC_INST_MODE(n) (((n) & 0xf) << 28) 66 #define SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(n) (((n) & 0xf) << 24) 67 #define SUN6I_DSI_INST_FUNC_TRANS_PACKET(n) (((n) & 0xf) << 20) 68 #define SUN6I_DSI_INST_FUNC_LANE_CEN BIT(4) 69 #define SUN6I_DSI_INST_FUNC_LANE_DEN(n) ((n) & 0xf) 70 71 #define SUN6I_DSI_INST_LOOP_SEL_REG 0x040 72 73 #define SUN6I_DSI_INST_LOOP_NUM_REG(n) (0x044 + (n) * 0x10) 74 #define SUN6I_DSI_INST_LOOP_NUM_N1(n) (((n) & 0xfff) << 16) 75 #define SUN6I_DSI_INST_LOOP_NUM_N0(n) ((n) & 0xfff) 76 77 #define SUN6I_DSI_INST_JUMP_SEL_REG 0x048 78 79 #define SUN6I_DSI_INST_JUMP_CFG_REG(n) (0x04c + (n) * 0x04) 80 #define SUN6I_DSI_INST_JUMP_CFG_TO(n) (((n) & 0xf) << 20) 81 #define SUN6I_DSI_INST_JUMP_CFG_POINT(n) (((n) & 0xf) << 16) 82 #define SUN6I_DSI_INST_JUMP_CFG_NUM(n) ((n) & 0xffff) 83 84 #define SUN6I_DSI_TRANS_START_REG 0x060 85 86 #define SUN6I_DSI_TRANS_ZERO_REG 0x078 87 88 #define SUN6I_DSI_TCON_DRQ_REG 0x07c 89 #define SUN6I_DSI_TCON_DRQ_ENABLE_MODE BIT(28) 90 #define SUN6I_DSI_TCON_DRQ_SET(n) ((n) & 0x3ff) 91 92 #define SUN6I_DSI_PIXEL_CTL0_REG 0x080 93 #define SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE BIT(16) 94 #define SUN6I_DSI_PIXEL_CTL0_FORMAT(n) ((n) & 0xf) 95 96 #define SUN6I_DSI_PIXEL_CTL1_REG 0x084 97 98 #define SUN6I_DSI_PIXEL_PH_REG 0x090 99 #define SUN6I_DSI_PIXEL_PH_ECC(n) (((n) & 0xff) << 24) 100 #define SUN6I_DSI_PIXEL_PH_WC(n) (((n) & 0xffff) << 8) 101 #define SUN6I_DSI_PIXEL_PH_VC(n) (((n) & 3) << 6) 102 #define SUN6I_DSI_PIXEL_PH_DT(n) ((n) & 0x3f) 103 104 #define SUN6I_DSI_PIXEL_PF0_REG 0x098 105 #define SUN6I_DSI_PIXEL_PF0_CRC_FORCE(n) ((n) & 0xffff) 106 107 #define SUN6I_DSI_PIXEL_PF1_REG 0x09c 108 #define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(n) (((n) & 0xffff) << 16) 109 #define SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(n) ((n) & 0xffff) 110 111 #define SUN6I_DSI_SYNC_HSS_REG 0x0b0 112 113 #define SUN6I_DSI_SYNC_HSE_REG 0x0b4 114 115 #define SUN6I_DSI_SYNC_VSS_REG 0x0b8 116 117 #define SUN6I_DSI_SYNC_VSE_REG 0x0bc 118 119 #define SUN6I_DSI_BLK_HSA0_REG 0x0c0 120 121 #define SUN6I_DSI_BLK_HSA1_REG 0x0c4 122 #define SUN6I_DSI_BLK_PF(n) (((n) & 0xffff) << 16) 123 #define SUN6I_DSI_BLK_PD(n) ((n) & 0xff) 124 125 #define SUN6I_DSI_BLK_HBP0_REG 0x0c8 126 127 #define SUN6I_DSI_BLK_HBP1_REG 0x0cc 128 129 #define SUN6I_DSI_BLK_HFP0_REG 0x0d0 130 131 #define SUN6I_DSI_BLK_HFP1_REG 0x0d4 132 133 #define SUN6I_DSI_BLK_HBLK0_REG 0x0e0 134 135 #define SUN6I_DSI_BLK_HBLK1_REG 0x0e4 136 137 #define SUN6I_DSI_BLK_VBLK0_REG 0x0e8 138 139 #define SUN6I_DSI_BLK_VBLK1_REG 0x0ec 140 141 #define SUN6I_DSI_BURST_LINE_REG 0x0f0 142 #define SUN6I_DSI_BURST_LINE_SYNC_POINT(n) (((n) & 0xffff) << 16) 143 #define SUN6I_DSI_BURST_LINE_NUM(n) ((n) & 0xffff) 144 145 #define SUN6I_DSI_BURST_DRQ_REG 0x0f4 146 #define SUN6I_DSI_BURST_DRQ_EDGE1(n) (((n) & 0xffff) << 16) 147 #define SUN6I_DSI_BURST_DRQ_EDGE0(n) ((n) & 0xffff) 148 149 #define SUN6I_DSI_CMD_CTL_REG 0x200 150 #define SUN6I_DSI_CMD_CTL_RX_OVERFLOW BIT(26) 151 #define SUN6I_DSI_CMD_CTL_RX_FLAG BIT(25) 152 #define SUN6I_DSI_CMD_CTL_TX_FLAG BIT(9) 153 154 #define SUN6I_DSI_CMD_RX_REG(n) (0x240 + (n) * 0x04) 155 156 #define SUN6I_DSI_DEBUG_DATA_REG 0x2f8 157 158 #define SUN6I_DSI_CMD_TX_REG(n) (0x300 + (n) * 0x04) 159 160 #define SUN6I_DSI_SYNC_POINT 40 161 162 enum sun6i_dsi_start_inst { 163 DSI_START_LPRX, 164 DSI_START_LPTX, 165 DSI_START_HSC, 166 DSI_START_HSD, 167 }; 168 169 enum sun6i_dsi_inst_id { 170 DSI_INST_ID_LP11 = 0, 171 DSI_INST_ID_TBA, 172 DSI_INST_ID_HSC, 173 DSI_INST_ID_HSD, 174 DSI_INST_ID_LPDT, 175 DSI_INST_ID_HSCEXIT, 176 DSI_INST_ID_NOP, 177 DSI_INST_ID_DLY, 178 DSI_INST_ID_END = 15, 179 }; 180 181 enum sun6i_dsi_inst_mode { 182 DSI_INST_MODE_STOP = 0, 183 DSI_INST_MODE_TBA, 184 DSI_INST_MODE_HS, 185 DSI_INST_MODE_ESCAPE, 186 DSI_INST_MODE_HSCEXIT, 187 DSI_INST_MODE_NOP, 188 }; 189 190 enum sun6i_dsi_inst_escape { 191 DSI_INST_ESCA_LPDT = 0, 192 DSI_INST_ESCA_ULPS, 193 DSI_INST_ESCA_UN1, 194 DSI_INST_ESCA_UN2, 195 DSI_INST_ESCA_RESET, 196 DSI_INST_ESCA_UN3, 197 DSI_INST_ESCA_UN4, 198 DSI_INST_ESCA_UN5, 199 }; 200 201 enum sun6i_dsi_inst_packet { 202 DSI_INST_PACK_PIXEL = 0, 203 DSI_INST_PACK_COMMAND, 204 }; 205 206 static const u32 sun6i_dsi_ecc_array[] = { 207 [0] = (BIT(0) | BIT(1) | BIT(2) | BIT(4) | BIT(5) | BIT(7) | BIT(10) | 208 BIT(11) | BIT(13) | BIT(16) | BIT(20) | BIT(21) | BIT(22) | 209 BIT(23)), 210 [1] = (BIT(0) | BIT(1) | BIT(3) | BIT(4) | BIT(6) | BIT(8) | BIT(10) | 211 BIT(12) | BIT(14) | BIT(17) | BIT(20) | BIT(21) | BIT(22) | 212 BIT(23)), 213 [2] = (BIT(0) | BIT(2) | BIT(3) | BIT(5) | BIT(6) | BIT(9) | BIT(11) | 214 BIT(12) | BIT(15) | BIT(18) | BIT(20) | BIT(21) | BIT(22)), 215 [3] = (BIT(1) | BIT(2) | BIT(3) | BIT(7) | BIT(8) | BIT(9) | BIT(13) | 216 BIT(14) | BIT(15) | BIT(19) | BIT(20) | BIT(21) | BIT(23)), 217 [4] = (BIT(4) | BIT(5) | BIT(6) | BIT(7) | BIT(8) | BIT(9) | BIT(16) | 218 BIT(17) | BIT(18) | BIT(19) | BIT(20) | BIT(22) | BIT(23)), 219 [5] = (BIT(10) | BIT(11) | BIT(12) | BIT(13) | BIT(14) | BIT(15) | 220 BIT(16) | BIT(17) | BIT(18) | BIT(19) | BIT(21) | BIT(22) | 221 BIT(23)), 222 }; 223 224 static u32 sun6i_dsi_ecc_compute(unsigned int data) 225 { 226 int i; 227 u8 ecc = 0; 228 229 for (i = 0; i < ARRAY_SIZE(sun6i_dsi_ecc_array); i++) { 230 u32 field = sun6i_dsi_ecc_array[i]; 231 bool init = false; 232 u8 val = 0; 233 int j; 234 235 for (j = 0; j < 24; j++) { 236 if (!(BIT(j) & field)) 237 continue; 238 239 if (!init) { 240 val = (BIT(j) & data) ? 1 : 0; 241 init = true; 242 } else { 243 val ^= (BIT(j) & data) ? 1 : 0; 244 } 245 } 246 247 ecc |= val << i; 248 } 249 250 return ecc; 251 } 252 253 static u16 sun6i_dsi_crc_compute(u8 const *buffer, size_t len) 254 { 255 return crc_ccitt(0xffff, buffer, len); 256 } 257 258 static u16 sun6i_dsi_crc_repeat(u8 pd, u8 *buffer, size_t len) 259 { 260 memset(buffer, pd, len); 261 262 return sun6i_dsi_crc_compute(buffer, len); 263 } 264 265 static u32 sun6i_dsi_build_sync_pkt(u8 dt, u8 vc, u8 d0, u8 d1) 266 { 267 u32 val = dt & 0x3f; 268 269 val |= (vc & 3) << 6; 270 val |= (d0 & 0xff) << 8; 271 val |= (d1 & 0xff) << 16; 272 val |= sun6i_dsi_ecc_compute(val) << 24; 273 274 return val; 275 } 276 277 static u32 sun6i_dsi_build_blk0_pkt(u8 vc, u16 wc) 278 { 279 return sun6i_dsi_build_sync_pkt(MIPI_DSI_BLANKING_PACKET, vc, 280 wc & 0xff, wc >> 8); 281 } 282 283 static u32 sun6i_dsi_build_blk1_pkt(u16 pd, u8 *buffer, size_t len) 284 { 285 u32 val = SUN6I_DSI_BLK_PD(pd); 286 287 return val | SUN6I_DSI_BLK_PF(sun6i_dsi_crc_repeat(pd, buffer, len)); 288 } 289 290 static void sun6i_dsi_inst_abort(struct sun6i_dsi *dsi) 291 { 292 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, 293 SUN6I_DSI_BASIC_CTL0_INST_ST, 0); 294 } 295 296 static void sun6i_dsi_inst_commit(struct sun6i_dsi *dsi) 297 { 298 regmap_update_bits(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, 299 SUN6I_DSI_BASIC_CTL0_INST_ST, 300 SUN6I_DSI_BASIC_CTL0_INST_ST); 301 } 302 303 static int sun6i_dsi_inst_wait_for_completion(struct sun6i_dsi *dsi) 304 { 305 u32 val; 306 307 return regmap_read_poll_timeout(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, 308 val, 309 !(val & SUN6I_DSI_BASIC_CTL0_INST_ST), 310 100, 5000); 311 } 312 313 static void sun6i_dsi_inst_setup(struct sun6i_dsi *dsi, 314 enum sun6i_dsi_inst_id id, 315 enum sun6i_dsi_inst_mode mode, 316 bool clock, u8 data, 317 enum sun6i_dsi_inst_packet packet, 318 enum sun6i_dsi_inst_escape escape) 319 { 320 regmap_write(dsi->regs, SUN6I_DSI_INST_FUNC_REG(id), 321 SUN6I_DSI_INST_FUNC_INST_MODE(mode) | 322 SUN6I_DSI_INST_FUNC_ESCAPE_ENTRY(escape) | 323 SUN6I_DSI_INST_FUNC_TRANS_PACKET(packet) | 324 (clock ? SUN6I_DSI_INST_FUNC_LANE_CEN : 0) | 325 SUN6I_DSI_INST_FUNC_LANE_DEN(data)); 326 } 327 328 static void sun6i_dsi_inst_init(struct sun6i_dsi *dsi, 329 struct mipi_dsi_device *device) 330 { 331 u8 lanes_mask = GENMASK(device->lanes - 1, 0); 332 333 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LP11, DSI_INST_MODE_STOP, 334 true, lanes_mask, 0, 0); 335 336 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_TBA, DSI_INST_MODE_TBA, 337 false, 1, 0, 0); 338 339 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSC, DSI_INST_MODE_HS, 340 true, 0, DSI_INST_PACK_PIXEL, 0); 341 342 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSD, DSI_INST_MODE_HS, 343 false, lanes_mask, DSI_INST_PACK_PIXEL, 0); 344 345 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_LPDT, DSI_INST_MODE_ESCAPE, 346 false, 1, DSI_INST_PACK_COMMAND, 347 DSI_INST_ESCA_LPDT); 348 349 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_HSCEXIT, DSI_INST_MODE_HSCEXIT, 350 true, 0, 0, 0); 351 352 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_NOP, DSI_INST_MODE_STOP, 353 false, lanes_mask, 0, 0); 354 355 sun6i_dsi_inst_setup(dsi, DSI_INST_ID_DLY, DSI_INST_MODE_NOP, 356 true, lanes_mask, 0, 0); 357 358 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_CFG_REG(0), 359 SUN6I_DSI_INST_JUMP_CFG_POINT(DSI_INST_ID_NOP) | 360 SUN6I_DSI_INST_JUMP_CFG_TO(DSI_INST_ID_HSCEXIT) | 361 SUN6I_DSI_INST_JUMP_CFG_NUM(1)); 362 }; 363 364 static u16 sun6i_dsi_get_video_start_delay(struct sun6i_dsi *dsi, 365 struct drm_display_mode *mode) 366 { 367 u16 start = clamp(mode->vtotal - mode->vdisplay - 10, 8, 100); 368 u16 delay = mode->vtotal - (mode->vsync_end - mode->vdisplay) + start; 369 370 if (delay > mode->vtotal) 371 delay = delay % mode->vtotal; 372 373 return max_t(u16, delay, 1); 374 } 375 376 static u16 sun6i_dsi_get_line_num(struct sun6i_dsi *dsi, 377 struct drm_display_mode *mode) 378 { 379 struct mipi_dsi_device *device = dsi->device; 380 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8; 381 382 return mode->htotal * Bpp / device->lanes; 383 } 384 385 static u16 sun6i_dsi_get_drq_edge0(struct sun6i_dsi *dsi, 386 struct drm_display_mode *mode, 387 u16 line_num, u16 edge1) 388 { 389 u16 edge0 = edge1; 390 391 edge0 += (mode->hdisplay + 40) * SUN6I_DSI_TCON_DIV / 8; 392 393 if (edge0 > line_num) 394 return edge0 - line_num; 395 396 return 1; 397 } 398 399 static u16 sun6i_dsi_get_drq_edge1(struct sun6i_dsi *dsi, 400 struct drm_display_mode *mode, 401 u16 line_num) 402 { 403 struct mipi_dsi_device *device = dsi->device; 404 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8; 405 unsigned int hbp = mode->htotal - mode->hsync_end; 406 u16 edge1; 407 408 edge1 = SUN6I_DSI_SYNC_POINT; 409 edge1 += (mode->hdisplay + hbp + 20) * Bpp / device->lanes; 410 411 if (edge1 > line_num) 412 return line_num; 413 414 return edge1; 415 } 416 417 static void sun6i_dsi_setup_burst(struct sun6i_dsi *dsi, 418 struct drm_display_mode *mode) 419 { 420 struct mipi_dsi_device *device = dsi->device; 421 u32 val = 0; 422 423 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 424 u16 line_num = sun6i_dsi_get_line_num(dsi, mode); 425 u16 edge0, edge1; 426 427 edge1 = sun6i_dsi_get_drq_edge1(dsi, mode, line_num); 428 edge0 = sun6i_dsi_get_drq_edge0(dsi, mode, line_num, edge1); 429 430 regmap_write(dsi->regs, SUN6I_DSI_BURST_DRQ_REG, 431 SUN6I_DSI_BURST_DRQ_EDGE0(edge0) | 432 SUN6I_DSI_BURST_DRQ_EDGE1(edge1)); 433 434 regmap_write(dsi->regs, SUN6I_DSI_BURST_LINE_REG, 435 SUN6I_DSI_BURST_LINE_NUM(line_num) | 436 SUN6I_DSI_BURST_LINE_SYNC_POINT(SUN6I_DSI_SYNC_POINT)); 437 438 val = SUN6I_DSI_TCON_DRQ_ENABLE_MODE; 439 } else if ((mode->hsync_end - mode->hdisplay) > 20) { 440 /* Maaaaaagic */ 441 u16 drq = (mode->hsync_end - mode->hdisplay) - 20; 442 443 drq *= mipi_dsi_pixel_format_to_bpp(device->format); 444 drq /= 32; 445 446 val = (SUN6I_DSI_TCON_DRQ_ENABLE_MODE | 447 SUN6I_DSI_TCON_DRQ_SET(drq)); 448 } 449 450 regmap_write(dsi->regs, SUN6I_DSI_TCON_DRQ_REG, val); 451 } 452 453 static void sun6i_dsi_setup_inst_loop(struct sun6i_dsi *dsi, 454 struct drm_display_mode *mode) 455 { 456 struct mipi_dsi_device *device = dsi->device; 457 u16 delay = 50 - 1; 458 459 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 460 delay = (mode->htotal - mode->hdisplay) * 150; 461 delay /= (mode->clock / 1000) * 8; 462 delay -= 50; 463 } 464 465 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_SEL_REG, 466 2 << (4 * DSI_INST_ID_LP11) | 467 3 << (4 * DSI_INST_ID_DLY)); 468 469 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(0), 470 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) | 471 SUN6I_DSI_INST_LOOP_NUM_N1(delay)); 472 regmap_write(dsi->regs, SUN6I_DSI_INST_LOOP_NUM_REG(1), 473 SUN6I_DSI_INST_LOOP_NUM_N0(50 - 1) | 474 SUN6I_DSI_INST_LOOP_NUM_N1(delay)); 475 } 476 477 static void sun6i_dsi_setup_format(struct sun6i_dsi *dsi, 478 struct drm_display_mode *mode) 479 { 480 struct mipi_dsi_device *device = dsi->device; 481 u32 val = SUN6I_DSI_PIXEL_PH_VC(device->channel); 482 u8 dt, fmt; 483 u16 wc; 484 485 /* 486 * TODO: The format defines are only valid in video mode and 487 * change in command mode. 488 */ 489 switch (device->format) { 490 case MIPI_DSI_FMT_RGB888: 491 dt = MIPI_DSI_PACKED_PIXEL_STREAM_24; 492 fmt = 8; 493 break; 494 case MIPI_DSI_FMT_RGB666: 495 dt = MIPI_DSI_PIXEL_STREAM_3BYTE_18; 496 fmt = 9; 497 break; 498 case MIPI_DSI_FMT_RGB666_PACKED: 499 dt = MIPI_DSI_PACKED_PIXEL_STREAM_18; 500 fmt = 10; 501 break; 502 case MIPI_DSI_FMT_RGB565: 503 dt = MIPI_DSI_PACKED_PIXEL_STREAM_16; 504 fmt = 11; 505 break; 506 default: 507 return; 508 } 509 val |= SUN6I_DSI_PIXEL_PH_DT(dt); 510 511 wc = mode->hdisplay * mipi_dsi_pixel_format_to_bpp(device->format) / 8; 512 val |= SUN6I_DSI_PIXEL_PH_WC(wc); 513 val |= SUN6I_DSI_PIXEL_PH_ECC(sun6i_dsi_ecc_compute(val)); 514 515 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PH_REG, val); 516 517 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF0_REG, 518 SUN6I_DSI_PIXEL_PF0_CRC_FORCE(0xffff)); 519 520 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_PF1_REG, 521 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINE0(0xffff) | 522 SUN6I_DSI_PIXEL_PF1_CRC_INIT_LINEN(0xffff)); 523 524 regmap_write(dsi->regs, SUN6I_DSI_PIXEL_CTL0_REG, 525 SUN6I_DSI_PIXEL_CTL0_PD_PLUG_DISABLE | 526 SUN6I_DSI_PIXEL_CTL0_FORMAT(fmt)); 527 } 528 529 static void sun6i_dsi_setup_timings(struct sun6i_dsi *dsi, 530 struct drm_display_mode *mode) 531 { 532 struct mipi_dsi_device *device = dsi->device; 533 unsigned int Bpp = mipi_dsi_pixel_format_to_bpp(device->format) / 8; 534 u16 hbp = 0, hfp = 0, hsa = 0, hblk = 0, vblk = 0; 535 u32 basic_ctl = 0; 536 size_t bytes; 537 u8 *buffer; 538 539 /* Do all timing calculations up front to allocate buffer space */ 540 541 if (device->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) { 542 hblk = mode->hdisplay * Bpp; 543 basic_ctl = SUN6I_DSI_BASIC_CTL_VIDEO_BURST | 544 SUN6I_DSI_BASIC_CTL_HSA_HSE_DIS | 545 SUN6I_DSI_BASIC_CTL_HBP_DIS; 546 547 if (device->lanes == 4) 548 basic_ctl |= SUN6I_DSI_BASIC_CTL_TRAIL_FILL | 549 SUN6I_DSI_BASIC_CTL_TRAIL_INV(0xc); 550 } else { 551 /* 552 * A sync period is composed of a blanking packet (4 553 * bytes + payload + 2 bytes) and a sync event packet 554 * (4 bytes). Its minimal size is therefore 10 bytes 555 */ 556 #define HSA_PACKET_OVERHEAD 10 557 hsa = max((unsigned int)HSA_PACKET_OVERHEAD, 558 (mode->hsync_end - mode->hsync_start) * Bpp - HSA_PACKET_OVERHEAD); 559 560 /* 561 * The backporch is set using a blanking packet (4 562 * bytes + payload + 2 bytes). Its minimal size is 563 * therefore 6 bytes 564 */ 565 #define HBP_PACKET_OVERHEAD 6 566 hbp = max((unsigned int)HBP_PACKET_OVERHEAD, 567 (mode->htotal - mode->hsync_end) * Bpp - HBP_PACKET_OVERHEAD); 568 569 /* 570 * The frontporch is set using a blanking packet (4 571 * bytes + payload + 2 bytes). Its minimal size is 572 * therefore 6 bytes 573 */ 574 #define HFP_PACKET_OVERHEAD 6 575 hfp = max((unsigned int)HFP_PACKET_OVERHEAD, 576 (mode->hsync_start - mode->hdisplay) * Bpp - HFP_PACKET_OVERHEAD); 577 578 /* 579 * The blanking is set using a sync event (4 bytes) 580 * and a blanking packet (4 bytes + payload + 2 581 * bytes). Its minimal size is therefore 10 bytes. 582 */ 583 #define HBLK_PACKET_OVERHEAD 10 584 hblk = max((unsigned int)HBLK_PACKET_OVERHEAD, 585 (mode->htotal - (mode->hsync_end - mode->hsync_start)) * Bpp - 586 HBLK_PACKET_OVERHEAD); 587 588 /* 589 * And I'm not entirely sure what vblk is about. The driver in 590 * Allwinner BSP is using a rather convoluted calculation 591 * there only for 4 lanes. However, using 0 (the !4 lanes 592 * case) even with a 4 lanes screen seems to work... 593 */ 594 vblk = 0; 595 } 596 597 /* How many bytes do we need to send all payloads? */ 598 bytes = max_t(size_t, max(max(hfp, hblk), max(hsa, hbp)), vblk); 599 buffer = kmalloc(bytes, GFP_KERNEL); 600 if (WARN_ON(!buffer)) 601 return; 602 603 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL_REG, basic_ctl); 604 605 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSS_REG, 606 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_START, 607 device->channel, 608 0, 0)); 609 610 regmap_write(dsi->regs, SUN6I_DSI_SYNC_HSE_REG, 611 sun6i_dsi_build_sync_pkt(MIPI_DSI_H_SYNC_END, 612 device->channel, 613 0, 0)); 614 615 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSS_REG, 616 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_START, 617 device->channel, 618 0, 0)); 619 620 regmap_write(dsi->regs, SUN6I_DSI_SYNC_VSE_REG, 621 sun6i_dsi_build_sync_pkt(MIPI_DSI_V_SYNC_END, 622 device->channel, 623 0, 0)); 624 625 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE0_REG, 626 SUN6I_DSI_BASIC_SIZE0_VSA(mode->vsync_end - 627 mode->vsync_start) | 628 SUN6I_DSI_BASIC_SIZE0_VBP(mode->vtotal - 629 mode->vsync_end)); 630 631 regmap_write(dsi->regs, SUN6I_DSI_BASIC_SIZE1_REG, 632 SUN6I_DSI_BASIC_SIZE1_VACT(mode->vdisplay) | 633 SUN6I_DSI_BASIC_SIZE1_VT(mode->vtotal)); 634 635 /* sync */ 636 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA0_REG, 637 sun6i_dsi_build_blk0_pkt(device->channel, hsa)); 638 regmap_write(dsi->regs, SUN6I_DSI_BLK_HSA1_REG, 639 sun6i_dsi_build_blk1_pkt(0, buffer, hsa)); 640 641 /* backporch */ 642 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP0_REG, 643 sun6i_dsi_build_blk0_pkt(device->channel, hbp)); 644 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBP1_REG, 645 sun6i_dsi_build_blk1_pkt(0, buffer, hbp)); 646 647 /* frontporch */ 648 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP0_REG, 649 sun6i_dsi_build_blk0_pkt(device->channel, hfp)); 650 regmap_write(dsi->regs, SUN6I_DSI_BLK_HFP1_REG, 651 sun6i_dsi_build_blk1_pkt(0, buffer, hfp)); 652 653 /* hblk */ 654 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK0_REG, 655 sun6i_dsi_build_blk0_pkt(device->channel, hblk)); 656 regmap_write(dsi->regs, SUN6I_DSI_BLK_HBLK1_REG, 657 sun6i_dsi_build_blk1_pkt(0, buffer, hblk)); 658 659 /* vblk */ 660 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK0_REG, 661 sun6i_dsi_build_blk0_pkt(device->channel, vblk)); 662 regmap_write(dsi->regs, SUN6I_DSI_BLK_VBLK1_REG, 663 sun6i_dsi_build_blk1_pkt(0, buffer, vblk)); 664 665 kfree(buffer); 666 } 667 668 static int sun6i_dsi_start(struct sun6i_dsi *dsi, 669 enum sun6i_dsi_start_inst func) 670 { 671 switch (func) { 672 case DSI_START_LPTX: 673 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG, 674 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) | 675 DSI_INST_ID_END << (4 * DSI_INST_ID_LPDT)); 676 break; 677 case DSI_START_LPRX: 678 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG, 679 DSI_INST_ID_LPDT << (4 * DSI_INST_ID_LP11) | 680 DSI_INST_ID_DLY << (4 * DSI_INST_ID_LPDT) | 681 DSI_INST_ID_TBA << (4 * DSI_INST_ID_DLY) | 682 DSI_INST_ID_END << (4 * DSI_INST_ID_TBA)); 683 break; 684 case DSI_START_HSC: 685 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG, 686 DSI_INST_ID_HSC << (4 * DSI_INST_ID_LP11) | 687 DSI_INST_ID_END << (4 * DSI_INST_ID_HSC)); 688 break; 689 case DSI_START_HSD: 690 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG, 691 DSI_INST_ID_NOP << (4 * DSI_INST_ID_LP11) | 692 DSI_INST_ID_HSD << (4 * DSI_INST_ID_NOP) | 693 DSI_INST_ID_DLY << (4 * DSI_INST_ID_HSD) | 694 DSI_INST_ID_NOP << (4 * DSI_INST_ID_DLY) | 695 DSI_INST_ID_END << (4 * DSI_INST_ID_HSCEXIT)); 696 break; 697 default: 698 regmap_write(dsi->regs, SUN6I_DSI_INST_JUMP_SEL_REG, 699 DSI_INST_ID_END << (4 * DSI_INST_ID_LP11)); 700 break; 701 } 702 703 sun6i_dsi_inst_abort(dsi); 704 sun6i_dsi_inst_commit(dsi); 705 706 if (func == DSI_START_HSC) 707 regmap_write_bits(dsi->regs, 708 SUN6I_DSI_INST_FUNC_REG(DSI_INST_ID_LP11), 709 SUN6I_DSI_INST_FUNC_LANE_CEN, 0); 710 711 return 0; 712 } 713 714 static void sun6i_dsi_encoder_enable(struct drm_encoder *encoder) 715 { 716 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 717 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); 718 struct mipi_dsi_device *device = dsi->device; 719 union phy_configure_opts opts = { 0 }; 720 struct phy_configure_opts_mipi_dphy *cfg = &opts.mipi_dphy; 721 u16 delay; 722 723 DRM_DEBUG_DRIVER("Enabling DSI output\n"); 724 725 pm_runtime_get_sync(dsi->dev); 726 727 delay = sun6i_dsi_get_video_start_delay(dsi, mode); 728 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL1_REG, 729 SUN6I_DSI_BASIC_CTL1_VIDEO_ST_DELAY(delay) | 730 SUN6I_DSI_BASIC_CTL1_VIDEO_FILL | 731 SUN6I_DSI_BASIC_CTL1_VIDEO_PRECISION | 732 SUN6I_DSI_BASIC_CTL1_VIDEO_MODE); 733 734 sun6i_dsi_setup_burst(dsi, mode); 735 sun6i_dsi_setup_inst_loop(dsi, mode); 736 sun6i_dsi_setup_format(dsi, mode); 737 sun6i_dsi_setup_timings(dsi, mode); 738 739 phy_init(dsi->dphy); 740 741 phy_mipi_dphy_get_default_config(mode->clock * 1000, 742 mipi_dsi_pixel_format_to_bpp(device->format), 743 device->lanes, cfg); 744 745 phy_set_mode(dsi->dphy, PHY_MODE_MIPI_DPHY); 746 phy_configure(dsi->dphy, &opts); 747 phy_power_on(dsi->dphy); 748 749 if (!IS_ERR(dsi->panel)) 750 drm_panel_prepare(dsi->panel); 751 752 /* 753 * FIXME: This should be moved after the switch to HS mode. 754 * 755 * Unfortunately, once in HS mode, it seems like we're not 756 * able to send DCS commands anymore, which would prevent any 757 * panel to send any DCS command as part as their enable 758 * method, which is quite common. 759 * 760 * I haven't seen any artifact due to that sub-optimal 761 * ordering on the panels I've tested it with, so I guess this 762 * will do for now, until that IP is better understood. 763 */ 764 if (!IS_ERR(dsi->panel)) 765 drm_panel_enable(dsi->panel); 766 767 sun6i_dsi_start(dsi, DSI_START_HSC); 768 769 udelay(1000); 770 771 sun6i_dsi_start(dsi, DSI_START_HSD); 772 } 773 774 static void sun6i_dsi_encoder_disable(struct drm_encoder *encoder) 775 { 776 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); 777 778 DRM_DEBUG_DRIVER("Disabling DSI output\n"); 779 780 if (!IS_ERR(dsi->panel)) { 781 drm_panel_disable(dsi->panel); 782 drm_panel_unprepare(dsi->panel); 783 } 784 785 phy_power_off(dsi->dphy); 786 phy_exit(dsi->dphy); 787 788 pm_runtime_put(dsi->dev); 789 } 790 791 static int sun6i_dsi_get_modes(struct drm_connector *connector) 792 { 793 struct sun6i_dsi *dsi = connector_to_sun6i_dsi(connector); 794 795 return drm_panel_get_modes(dsi->panel); 796 } 797 798 static struct drm_connector_helper_funcs sun6i_dsi_connector_helper_funcs = { 799 .get_modes = sun6i_dsi_get_modes, 800 }; 801 802 static enum drm_connector_status 803 sun6i_dsi_connector_detect(struct drm_connector *connector, bool force) 804 { 805 return connector_status_connected; 806 } 807 808 static const struct drm_connector_funcs sun6i_dsi_connector_funcs = { 809 .detect = sun6i_dsi_connector_detect, 810 .fill_modes = drm_helper_probe_single_connector_modes, 811 .destroy = drm_connector_cleanup, 812 .reset = drm_atomic_helper_connector_reset, 813 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 814 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 815 }; 816 817 static const struct drm_encoder_helper_funcs sun6i_dsi_enc_helper_funcs = { 818 .disable = sun6i_dsi_encoder_disable, 819 .enable = sun6i_dsi_encoder_enable, 820 }; 821 822 static const struct drm_encoder_funcs sun6i_dsi_enc_funcs = { 823 .destroy = drm_encoder_cleanup, 824 }; 825 826 static u32 sun6i_dsi_dcs_build_pkt_hdr(struct sun6i_dsi *dsi, 827 const struct mipi_dsi_msg *msg) 828 { 829 u32 pkt = msg->type; 830 831 if (msg->type == MIPI_DSI_DCS_LONG_WRITE) { 832 pkt |= ((msg->tx_len + 1) & 0xffff) << 8; 833 pkt |= (((msg->tx_len + 1) >> 8) & 0xffff) << 16; 834 } else { 835 pkt |= (((u8 *)msg->tx_buf)[0] << 8); 836 if (msg->tx_len > 1) 837 pkt |= (((u8 *)msg->tx_buf)[1] << 16); 838 } 839 840 pkt |= sun6i_dsi_ecc_compute(pkt) << 24; 841 842 return pkt; 843 } 844 845 static int sun6i_dsi_dcs_write_short(struct sun6i_dsi *dsi, 846 const struct mipi_dsi_msg *msg) 847 { 848 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0), 849 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg)); 850 regmap_write_bits(dsi->regs, SUN6I_DSI_CMD_CTL_REG, 851 0xff, (4 - 1)); 852 853 sun6i_dsi_start(dsi, DSI_START_LPTX); 854 855 return msg->tx_len; 856 } 857 858 static int sun6i_dsi_dcs_write_long(struct sun6i_dsi *dsi, 859 const struct mipi_dsi_msg *msg) 860 { 861 int ret, len = 0; 862 u8 *bounce; 863 u16 crc; 864 865 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0), 866 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg)); 867 868 bounce = kzalloc(msg->tx_len + sizeof(crc), GFP_KERNEL); 869 if (!bounce) 870 return -ENOMEM; 871 872 memcpy(bounce, msg->tx_buf, msg->tx_len); 873 len += msg->tx_len; 874 875 crc = sun6i_dsi_crc_compute(bounce, msg->tx_len); 876 memcpy((u8 *)bounce + msg->tx_len, &crc, sizeof(crc)); 877 len += sizeof(crc); 878 879 regmap_bulk_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(1), bounce, len); 880 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, len + 4 - 1); 881 kfree(bounce); 882 883 sun6i_dsi_start(dsi, DSI_START_LPTX); 884 885 ret = sun6i_dsi_inst_wait_for_completion(dsi); 886 if (ret < 0) { 887 sun6i_dsi_inst_abort(dsi); 888 return ret; 889 } 890 891 /* 892 * TODO: There's some bits (reg 0x200, bits 8/9) that 893 * apparently can be used to check whether the data have been 894 * sent, but I couldn't get it to work reliably. 895 */ 896 return msg->tx_len; 897 } 898 899 static int sun6i_dsi_dcs_read(struct sun6i_dsi *dsi, 900 const struct mipi_dsi_msg *msg) 901 { 902 u32 val; 903 int ret; 904 u8 byte0; 905 906 regmap_write(dsi->regs, SUN6I_DSI_CMD_TX_REG(0), 907 sun6i_dsi_dcs_build_pkt_hdr(dsi, msg)); 908 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, 909 (4 - 1)); 910 911 sun6i_dsi_start(dsi, DSI_START_LPRX); 912 913 ret = sun6i_dsi_inst_wait_for_completion(dsi); 914 if (ret < 0) { 915 sun6i_dsi_inst_abort(dsi); 916 return ret; 917 } 918 919 /* 920 * TODO: There's some bits (reg 0x200, bits 24/25) that 921 * apparently can be used to check whether the data have been 922 * received, but I couldn't get it to work reliably. 923 */ 924 regmap_read(dsi->regs, SUN6I_DSI_CMD_CTL_REG, &val); 925 if (val & SUN6I_DSI_CMD_CTL_RX_OVERFLOW) 926 return -EIO; 927 928 regmap_read(dsi->regs, SUN6I_DSI_CMD_RX_REG(0), &val); 929 byte0 = val & 0xff; 930 if (byte0 == MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT) 931 return -EIO; 932 933 ((u8 *)msg->rx_buf)[0] = (val >> 8); 934 935 return 1; 936 } 937 938 static int sun6i_dsi_attach(struct mipi_dsi_host *host, 939 struct mipi_dsi_device *device) 940 { 941 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host); 942 943 dsi->device = device; 944 dsi->panel = of_drm_find_panel(device->dev.of_node); 945 if (IS_ERR(dsi->panel)) 946 return PTR_ERR(dsi->panel); 947 948 dev_info(host->dev, "Attached device %s\n", device->name); 949 950 return 0; 951 } 952 953 static int sun6i_dsi_detach(struct mipi_dsi_host *host, 954 struct mipi_dsi_device *device) 955 { 956 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host); 957 958 dsi->panel = NULL; 959 dsi->device = NULL; 960 961 return 0; 962 } 963 964 static ssize_t sun6i_dsi_transfer(struct mipi_dsi_host *host, 965 const struct mipi_dsi_msg *msg) 966 { 967 struct sun6i_dsi *dsi = host_to_sun6i_dsi(host); 968 int ret; 969 970 ret = sun6i_dsi_inst_wait_for_completion(dsi); 971 if (ret < 0) 972 sun6i_dsi_inst_abort(dsi); 973 974 regmap_write(dsi->regs, SUN6I_DSI_CMD_CTL_REG, 975 SUN6I_DSI_CMD_CTL_RX_OVERFLOW | 976 SUN6I_DSI_CMD_CTL_RX_FLAG | 977 SUN6I_DSI_CMD_CTL_TX_FLAG); 978 979 switch (msg->type) { 980 case MIPI_DSI_DCS_SHORT_WRITE: 981 case MIPI_DSI_DCS_SHORT_WRITE_PARAM: 982 ret = sun6i_dsi_dcs_write_short(dsi, msg); 983 break; 984 985 case MIPI_DSI_DCS_LONG_WRITE: 986 ret = sun6i_dsi_dcs_write_long(dsi, msg); 987 break; 988 989 case MIPI_DSI_DCS_READ: 990 if (msg->rx_len == 1) { 991 ret = sun6i_dsi_dcs_read(dsi, msg); 992 break; 993 } 994 995 default: 996 ret = -EINVAL; 997 } 998 999 return ret; 1000 } 1001 1002 static const struct mipi_dsi_host_ops sun6i_dsi_host_ops = { 1003 .attach = sun6i_dsi_attach, 1004 .detach = sun6i_dsi_detach, 1005 .transfer = sun6i_dsi_transfer, 1006 }; 1007 1008 static const struct regmap_config sun6i_dsi_regmap_config = { 1009 .reg_bits = 32, 1010 .val_bits = 32, 1011 .reg_stride = 4, 1012 .max_register = SUN6I_DSI_CMD_TX_REG(255), 1013 .name = "mipi-dsi", 1014 }; 1015 1016 static int sun6i_dsi_bind(struct device *dev, struct device *master, 1017 void *data) 1018 { 1019 struct drm_device *drm = data; 1020 struct sun4i_drv *drv = drm->dev_private; 1021 struct sun6i_dsi *dsi = dev_get_drvdata(dev); 1022 int ret; 1023 1024 if (!dsi->panel) 1025 return -EPROBE_DEFER; 1026 1027 dsi->drv = drv; 1028 1029 drm_encoder_helper_add(&dsi->encoder, 1030 &sun6i_dsi_enc_helper_funcs); 1031 ret = drm_encoder_init(drm, 1032 &dsi->encoder, 1033 &sun6i_dsi_enc_funcs, 1034 DRM_MODE_ENCODER_DSI, 1035 NULL); 1036 if (ret) { 1037 dev_err(dsi->dev, "Couldn't initialise the DSI encoder\n"); 1038 return ret; 1039 } 1040 dsi->encoder.possible_crtcs = BIT(0); 1041 1042 drm_connector_helper_add(&dsi->connector, 1043 &sun6i_dsi_connector_helper_funcs); 1044 ret = drm_connector_init(drm, &dsi->connector, 1045 &sun6i_dsi_connector_funcs, 1046 DRM_MODE_CONNECTOR_DSI); 1047 if (ret) { 1048 dev_err(dsi->dev, 1049 "Couldn't initialise the DSI connector\n"); 1050 goto err_cleanup_connector; 1051 } 1052 1053 drm_connector_attach_encoder(&dsi->connector, &dsi->encoder); 1054 drm_panel_attach(dsi->panel, &dsi->connector); 1055 1056 return 0; 1057 1058 err_cleanup_connector: 1059 drm_encoder_cleanup(&dsi->encoder); 1060 return ret; 1061 } 1062 1063 static void sun6i_dsi_unbind(struct device *dev, struct device *master, 1064 void *data) 1065 { 1066 struct sun6i_dsi *dsi = dev_get_drvdata(dev); 1067 1068 drm_panel_detach(dsi->panel); 1069 } 1070 1071 static const struct component_ops sun6i_dsi_ops = { 1072 .bind = sun6i_dsi_bind, 1073 .unbind = sun6i_dsi_unbind, 1074 }; 1075 1076 static int sun6i_dsi_probe(struct platform_device *pdev) 1077 { 1078 struct device *dev = &pdev->dev; 1079 struct sun6i_dsi *dsi; 1080 struct resource *res; 1081 void __iomem *base; 1082 int ret; 1083 1084 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); 1085 if (!dsi) 1086 return -ENOMEM; 1087 dev_set_drvdata(dev, dsi); 1088 dsi->dev = dev; 1089 dsi->host.ops = &sun6i_dsi_host_ops; 1090 dsi->host.dev = dev; 1091 1092 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1093 base = devm_ioremap_resource(dev, res); 1094 if (IS_ERR(base)) { 1095 dev_err(dev, "Couldn't map the DSI encoder registers\n"); 1096 return PTR_ERR(base); 1097 } 1098 1099 dsi->regs = devm_regmap_init_mmio_clk(dev, "bus", base, 1100 &sun6i_dsi_regmap_config); 1101 if (IS_ERR(dsi->regs)) { 1102 dev_err(dev, "Couldn't create the DSI encoder regmap\n"); 1103 return PTR_ERR(dsi->regs); 1104 } 1105 1106 dsi->reset = devm_reset_control_get_shared(dev, NULL); 1107 if (IS_ERR(dsi->reset)) { 1108 dev_err(dev, "Couldn't get our reset line\n"); 1109 return PTR_ERR(dsi->reset); 1110 } 1111 1112 dsi->mod_clk = devm_clk_get(dev, "mod"); 1113 if (IS_ERR(dsi->mod_clk)) { 1114 dev_err(dev, "Couldn't get the DSI mod clock\n"); 1115 return PTR_ERR(dsi->mod_clk); 1116 } 1117 1118 /* 1119 * In order to operate properly, that clock seems to be always 1120 * set to 297MHz. 1121 */ 1122 clk_set_rate_exclusive(dsi->mod_clk, 297000000); 1123 1124 dsi->dphy = devm_phy_get(dev, "dphy"); 1125 if (IS_ERR(dsi->dphy)) { 1126 dev_err(dev, "Couldn't get the MIPI D-PHY\n"); 1127 ret = PTR_ERR(dsi->dphy); 1128 goto err_unprotect_clk; 1129 } 1130 1131 pm_runtime_enable(dev); 1132 1133 ret = mipi_dsi_host_register(&dsi->host); 1134 if (ret) { 1135 dev_err(dev, "Couldn't register MIPI-DSI host\n"); 1136 goto err_pm_disable; 1137 } 1138 1139 ret = component_add(&pdev->dev, &sun6i_dsi_ops); 1140 if (ret) { 1141 dev_err(dev, "Couldn't register our component\n"); 1142 goto err_remove_dsi_host; 1143 } 1144 1145 return 0; 1146 1147 err_remove_dsi_host: 1148 mipi_dsi_host_unregister(&dsi->host); 1149 err_pm_disable: 1150 pm_runtime_disable(dev); 1151 err_unprotect_clk: 1152 clk_rate_exclusive_put(dsi->mod_clk); 1153 return ret; 1154 } 1155 1156 static int sun6i_dsi_remove(struct platform_device *pdev) 1157 { 1158 struct device *dev = &pdev->dev; 1159 struct sun6i_dsi *dsi = dev_get_drvdata(dev); 1160 1161 component_del(&pdev->dev, &sun6i_dsi_ops); 1162 mipi_dsi_host_unregister(&dsi->host); 1163 pm_runtime_disable(dev); 1164 clk_rate_exclusive_put(dsi->mod_clk); 1165 1166 return 0; 1167 } 1168 1169 static int __maybe_unused sun6i_dsi_runtime_resume(struct device *dev) 1170 { 1171 struct sun6i_dsi *dsi = dev_get_drvdata(dev); 1172 1173 reset_control_deassert(dsi->reset); 1174 clk_prepare_enable(dsi->mod_clk); 1175 1176 /* 1177 * Enable the DSI block. 1178 * 1179 * Some part of it can only be done once we get a number of 1180 * lanes, see sun6i_dsi_inst_init 1181 */ 1182 regmap_write(dsi->regs, SUN6I_DSI_CTL_REG, SUN6I_DSI_CTL_EN); 1183 1184 regmap_write(dsi->regs, SUN6I_DSI_BASIC_CTL0_REG, 1185 SUN6I_DSI_BASIC_CTL0_ECC_EN | SUN6I_DSI_BASIC_CTL0_CRC_EN); 1186 1187 regmap_write(dsi->regs, SUN6I_DSI_TRANS_START_REG, 10); 1188 regmap_write(dsi->regs, SUN6I_DSI_TRANS_ZERO_REG, 0); 1189 1190 if (dsi->device) 1191 sun6i_dsi_inst_init(dsi, dsi->device); 1192 1193 regmap_write(dsi->regs, SUN6I_DSI_DEBUG_DATA_REG, 0xff); 1194 1195 return 0; 1196 } 1197 1198 static int __maybe_unused sun6i_dsi_runtime_suspend(struct device *dev) 1199 { 1200 struct sun6i_dsi *dsi = dev_get_drvdata(dev); 1201 1202 clk_disable_unprepare(dsi->mod_clk); 1203 reset_control_assert(dsi->reset); 1204 1205 return 0; 1206 } 1207 1208 static const struct dev_pm_ops sun6i_dsi_pm_ops = { 1209 SET_RUNTIME_PM_OPS(sun6i_dsi_runtime_suspend, 1210 sun6i_dsi_runtime_resume, 1211 NULL) 1212 }; 1213 1214 static const struct of_device_id sun6i_dsi_of_table[] = { 1215 { .compatible = "allwinner,sun6i-a31-mipi-dsi" }, 1216 { } 1217 }; 1218 MODULE_DEVICE_TABLE(of, sun6i_dsi_of_table); 1219 1220 static struct platform_driver sun6i_dsi_platform_driver = { 1221 .probe = sun6i_dsi_probe, 1222 .remove = sun6i_dsi_remove, 1223 .driver = { 1224 .name = "sun6i-mipi-dsi", 1225 .of_match_table = sun6i_dsi_of_table, 1226 .pm = &sun6i_dsi_pm_ops, 1227 }, 1228 }; 1229 module_platform_driver(sun6i_dsi_platform_driver); 1230 1231 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1232 MODULE_DESCRIPTION("Allwinner A31 DSI Driver"); 1233 MODULE_LICENSE("GPL"); 1234