1 /* 2 * Copyright (C) 2015 Free Electrons 3 * Copyright (C) 2015 NextThing Co 4 * 5 * Boris Brezillon <boris.brezillon@free-electrons.com> 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #ifndef __SUN4I_TCON_H__ 15 #define __SUN4I_TCON_H__ 16 17 #include <drm/drm_crtc.h> 18 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/reset.h> 22 23 #define SUN4I_TCON_GCTL_REG 0x0 24 #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) 25 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) 26 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0) 27 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0) 28 29 #define SUN4I_TCON_GINT0_REG 0x4 30 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe)) 31 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe)) 32 33 #define SUN4I_TCON_GINT1_REG 0x8 34 #define SUN4I_TCON_FRM_CTL_REG 0x10 35 36 #define SUN4I_TCON0_CTL_REG 0x40 37 #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31) 38 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4) 39 #define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK) 40 41 #define SUN4I_TCON0_DCLK_REG 0x44 42 #define SUN4I_TCON0_DCLK_GATE_BIT (31) 43 #define SUN4I_TCON0_DCLK_DIV_SHIFT (0) 44 #define SUN4I_TCON0_DCLK_DIV_WIDTH (7) 45 46 #define SUN4I_TCON0_BASIC0_REG 0x48 47 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 48 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff) 49 50 #define SUN4I_TCON0_BASIC1_REG 0x4c 51 #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) 52 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) 53 54 #define SUN4I_TCON0_BASIC2_REG 0x50 55 #define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16) 56 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) 57 58 #define SUN4I_TCON0_BASIC3_REG 0x54 59 #define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16) 60 #define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff) 61 62 #define SUN4I_TCON0_HV_IF_REG 0x58 63 #define SUN4I_TCON0_CPU_IF_REG 0x60 64 #define SUN4I_TCON0_CPU_WR_REG 0x64 65 #define SUN4I_TCON0_CPU_RD0_REG 0x68 66 #define SUN4I_TCON0_CPU_RDA_REG 0x6c 67 #define SUN4I_TCON0_TTL0_REG 0x70 68 #define SUN4I_TCON0_TTL1_REG 0x74 69 #define SUN4I_TCON0_TTL2_REG 0x78 70 #define SUN4I_TCON0_TTL3_REG 0x7c 71 #define SUN4I_TCON0_TTL4_REG 0x80 72 #define SUN4I_TCON0_LVDS_IF_REG 0x84 73 #define SUN4I_TCON0_IO_POL_REG 0x88 74 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) 75 #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) 76 #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) 77 78 #define SUN4I_TCON0_IO_TRI_REG 0x8c 79 #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25) 80 #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24) 81 #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0) 82 83 #define SUN4I_TCON1_CTL_REG 0x90 84 #define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31) 85 #define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20) 86 #define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4) 87 #define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK) 88 89 #define SUN4I_TCON1_BASIC0_REG 0x94 90 #define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 91 #define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff) 92 93 #define SUN4I_TCON1_BASIC1_REG 0x98 94 #define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16) 95 #define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff) 96 97 #define SUN4I_TCON1_BASIC2_REG 0x9c 98 #define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16) 99 #define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff) 100 101 #define SUN4I_TCON1_BASIC3_REG 0xa0 102 #define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) 103 #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) 104 105 #define SUN4I_TCON1_BASIC4_REG 0xa4 106 #define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16) 107 #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) 108 109 #define SUN4I_TCON1_BASIC5_REG 0xa8 110 #define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16) 111 #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff) 112 113 #define SUN4I_TCON1_IO_POL_REG 0xf0 114 #define SUN4I_TCON1_IO_TRI_REG 0xf4 115 #define SUN4I_TCON_CEU_CTL_REG 0x100 116 #define SUN4I_TCON_CEU_MUL_RR_REG 0x110 117 #define SUN4I_TCON_CEU_MUL_RG_REG 0x114 118 #define SUN4I_TCON_CEU_MUL_RB_REG 0x118 119 #define SUN4I_TCON_CEU_ADD_RC_REG 0x11c 120 #define SUN4I_TCON_CEU_MUL_GR_REG 0x120 121 #define SUN4I_TCON_CEU_MUL_GG_REG 0x124 122 #define SUN4I_TCON_CEU_MUL_GB_REG 0x128 123 #define SUN4I_TCON_CEU_ADD_GC_REG 0x12c 124 #define SUN4I_TCON_CEU_MUL_BR_REG 0x130 125 #define SUN4I_TCON_CEU_MUL_BG_REG 0x134 126 #define SUN4I_TCON_CEU_MUL_BB_REG 0x138 127 #define SUN4I_TCON_CEU_ADD_BC_REG 0x13c 128 #define SUN4I_TCON_CEU_RANGE_R_REG 0x140 129 #define SUN4I_TCON_CEU_RANGE_G_REG 0x144 130 #define SUN4I_TCON_CEU_RANGE_B_REG 0x148 131 #define SUN4I_TCON_MUX_CTRL_REG 0x200 132 #define SUN4I_TCON1_FILL_CTL_REG 0x300 133 #define SUN4I_TCON1_FILL_BEG0_REG 0x304 134 #define SUN4I_TCON1_FILL_END0_REG 0x308 135 #define SUN4I_TCON1_FILL_DATA0_REG 0x30c 136 #define SUN4I_TCON1_FILL_BEG1_REG 0x310 137 #define SUN4I_TCON1_FILL_END1_REG 0x314 138 #define SUN4I_TCON1_FILL_DATA1_REG 0x318 139 #define SUN4I_TCON1_FILL_BEG2_REG 0x31c 140 #define SUN4I_TCON1_FILL_END2_REG 0x320 141 #define SUN4I_TCON1_FILL_DATA2_REG 0x324 142 #define SUN4I_TCON1_GAMMA_TABLE_REG 0x400 143 144 #define SUN4I_TCON_MAX_CHANNELS 2 145 146 struct sun4i_tcon_quirks { 147 bool has_unknown_mux; /* sun5i has undocumented mux */ 148 bool has_channel_1; /* a33 does not have channel 1 */ 149 }; 150 151 struct sun4i_tcon { 152 struct device *dev; 153 struct drm_device *drm; 154 struct regmap *regs; 155 156 /* Main bus clock */ 157 struct clk *clk; 158 159 /* Clocks for the TCON channels */ 160 struct clk *sclk0; 161 struct clk *sclk1; 162 163 /* Pixel clock */ 164 struct clk *dclk; 165 166 /* Reset control */ 167 struct reset_control *lcd_rst; 168 169 struct drm_panel *panel; 170 171 /* Platform adjustments */ 172 const struct sun4i_tcon_quirks *quirks; 173 174 /* Associated crtc */ 175 struct sun4i_crtc *crtc; 176 177 int id; 178 179 /* TCON list management */ 180 struct list_head list; 181 }; 182 183 struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node); 184 struct drm_panel *sun4i_tcon_find_panel(struct device_node *node); 185 186 /* Global Control */ 187 void sun4i_tcon_disable(struct sun4i_tcon *tcon); 188 void sun4i_tcon_enable(struct sun4i_tcon *tcon); 189 190 /* Channel Control */ 191 void sun4i_tcon_channel_disable(struct sun4i_tcon *tcon, int channel); 192 void sun4i_tcon_channel_enable(struct sun4i_tcon *tcon, int channel); 193 194 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable); 195 196 /* Mode Related Controls */ 197 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, 198 struct drm_encoder *encoder); 199 void sun4i_tcon0_mode_set(struct sun4i_tcon *tcon, 200 struct drm_display_mode *mode); 201 void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 202 struct drm_display_mode *mode); 203 204 #endif /* __SUN4I_TCON_H__ */ 205