1 /* 2 * Copyright (C) 2015 Free Electrons 3 * Copyright (C) 2015 NextThing Co 4 * 5 * Boris Brezillon <boris.brezillon@free-electrons.com> 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #ifndef __SUN4I_TCON_H__ 15 #define __SUN4I_TCON_H__ 16 17 #include <drm/drm_crtc.h> 18 19 #include <linux/kernel.h> 20 #include <linux/list.h> 21 #include <linux/reset.h> 22 23 #define SUN4I_TCON_GCTL_REG 0x0 24 #define SUN4I_TCON_GCTL_TCON_ENABLE BIT(31) 25 #define SUN4I_TCON_GCTL_IOMAP_MASK BIT(0) 26 #define SUN4I_TCON_GCTL_IOMAP_TCON1 (1 << 0) 27 #define SUN4I_TCON_GCTL_IOMAP_TCON0 (0 << 0) 28 29 #define SUN4I_TCON_GINT0_REG 0x4 30 #define SUN4I_TCON_GINT0_VBLANK_ENABLE(pipe) BIT(31 - (pipe)) 31 #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE BIT(27) 32 #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_ENABLE BIT(26) 33 #define SUN4I_TCON_GINT0_VBLANK_INT(pipe) BIT(15 - (pipe)) 34 #define SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT BIT(11) 35 #define SUN4I_TCON_GINT0_TCON0_TRI_COUNTER_INT BIT(10) 36 37 #define SUN4I_TCON_GINT1_REG 0x8 38 39 #define SUN4I_TCON_FRM_CTL_REG 0x10 40 #define SUN4I_TCON0_FRM_CTL_EN BIT(31) 41 #define SUN4I_TCON0_FRM_CTL_MODE_R BIT(6) 42 #define SUN4I_TCON0_FRM_CTL_MODE_G BIT(5) 43 #define SUN4I_TCON0_FRM_CTL_MODE_B BIT(4) 44 45 #define SUN4I_TCON0_FRM_SEED_PR_REG 0x14 46 #define SUN4I_TCON0_FRM_SEED_PG_REG 0x18 47 #define SUN4I_TCON0_FRM_SEED_PB_REG 0x1c 48 #define SUN4I_TCON0_FRM_SEED_LR_REG 0x20 49 #define SUN4I_TCON0_FRM_SEED_LG_REG 0x24 50 #define SUN4I_TCON0_FRM_SEED_LB_REG 0x28 51 #define SUN4I_TCON0_FRM_TBL0_REG 0x2c 52 #define SUN4I_TCON0_FRM_TBL1_REG 0x30 53 #define SUN4I_TCON0_FRM_TBL2_REG 0x34 54 #define SUN4I_TCON0_FRM_TBL3_REG 0x38 55 56 #define SUN4I_TCON0_CTL_REG 0x40 57 #define SUN4I_TCON0_CTL_TCON_ENABLE BIT(31) 58 #define SUN4I_TCON0_CTL_IF_MASK GENMASK(25, 24) 59 #define SUN4I_TCON0_CTL_IF_8080 (1 << 24) 60 #define SUN4I_TCON0_CTL_CLK_DELAY_MASK GENMASK(8, 4) 61 #define SUN4I_TCON0_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON0_CTL_CLK_DELAY_MASK) 62 #define SUN4I_TCON0_CTL_SRC_SEL_MASK GENMASK(2, 0) 63 64 #define SUN4I_TCON0_DCLK_REG 0x44 65 #define SUN4I_TCON0_DCLK_GATE_BIT (31) 66 #define SUN4I_TCON0_DCLK_DIV_SHIFT (0) 67 #define SUN4I_TCON0_DCLK_DIV_WIDTH (7) 68 69 #define SUN4I_TCON0_BASIC0_REG 0x48 70 #define SUN4I_TCON0_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 71 #define SUN4I_TCON0_BASIC0_Y(height) (((height) - 1) & 0xfff) 72 73 #define SUN4I_TCON0_BASIC1_REG 0x4c 74 #define SUN4I_TCON0_BASIC1_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) 75 #define SUN4I_TCON0_BASIC1_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) 76 77 #define SUN4I_TCON0_BASIC2_REG 0x50 78 #define SUN4I_TCON0_BASIC2_V_TOTAL(total) (((total) & 0x1fff) << 16) 79 #define SUN4I_TCON0_BASIC2_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) 80 81 #define SUN4I_TCON0_BASIC3_REG 0x54 82 #define SUN4I_TCON0_BASIC3_H_SYNC(width) ((((width) - 1) & 0x7ff) << 16) 83 #define SUN4I_TCON0_BASIC3_V_SYNC(height) (((height) - 1) & 0x7ff) 84 85 #define SUN4I_TCON0_HV_IF_REG 0x58 86 87 #define SUN4I_TCON0_CPU_IF_REG 0x60 88 #define SUN4I_TCON0_CPU_IF_MODE_MASK GENMASK(31, 28) 89 #define SUN4I_TCON0_CPU_IF_MODE_DSI (1 << 28) 90 #define SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH BIT(16) 91 #define SUN4I_TCON0_CPU_IF_TRI_FIFO_EN BIT(2) 92 #define SUN4I_TCON0_CPU_IF_TRI_EN BIT(0) 93 94 #define SUN4I_TCON0_CPU_WR_REG 0x64 95 #define SUN4I_TCON0_CPU_RD0_REG 0x68 96 #define SUN4I_TCON0_CPU_RDA_REG 0x6c 97 #define SUN4I_TCON0_TTL0_REG 0x70 98 #define SUN4I_TCON0_TTL1_REG 0x74 99 #define SUN4I_TCON0_TTL2_REG 0x78 100 #define SUN4I_TCON0_TTL3_REG 0x7c 101 #define SUN4I_TCON0_TTL4_REG 0x80 102 103 #define SUN4I_TCON0_LVDS_IF_REG 0x84 104 #define SUN4I_TCON0_LVDS_IF_EN BIT(31) 105 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_MASK BIT(26) 106 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS (1 << 26) 107 #define SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS (0 << 26) 108 #define SUN4I_TCON0_LVDS_IF_CLK_SEL_MASK BIT(20) 109 #define SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 (1 << 20) 110 #define SUN4I_TCON0_LVDS_IF_CLK_POL_MASK BIT(4) 111 #define SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL (1 << 4) 112 #define SUN4I_TCON0_LVDS_IF_CLK_POL_INV (0 << 4) 113 #define SUN4I_TCON0_LVDS_IF_DATA_POL_MASK GENMASK(3, 0) 114 #define SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL (0xf) 115 #define SUN4I_TCON0_LVDS_IF_DATA_POL_INV (0) 116 117 #define SUN4I_TCON0_IO_POL_REG 0x88 118 #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28) 119 #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27) 120 #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25) 121 #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24) 122 123 #define SUN4I_TCON0_IO_TRI_REG 0x8c 124 #define SUN4I_TCON0_IO_TRI_HSYNC_DISABLE BIT(25) 125 #define SUN4I_TCON0_IO_TRI_VSYNC_DISABLE BIT(24) 126 #define SUN4I_TCON0_IO_TRI_DATA_PINS_DISABLE(pins) GENMASK(pins, 0) 127 128 #define SUN4I_TCON1_CTL_REG 0x90 129 #define SUN4I_TCON1_CTL_TCON_ENABLE BIT(31) 130 #define SUN4I_TCON1_CTL_INTERLACE_ENABLE BIT(20) 131 #define SUN4I_TCON1_CTL_CLK_DELAY_MASK GENMASK(8, 4) 132 #define SUN4I_TCON1_CTL_CLK_DELAY(delay) ((delay << 4) & SUN4I_TCON1_CTL_CLK_DELAY_MASK) 133 #define SUN4I_TCON1_CTL_SRC_SEL_MASK GENMASK(1, 0) 134 135 #define SUN4I_TCON1_BASIC0_REG 0x94 136 #define SUN4I_TCON1_BASIC0_X(width) ((((width) - 1) & 0xfff) << 16) 137 #define SUN4I_TCON1_BASIC0_Y(height) (((height) - 1) & 0xfff) 138 139 #define SUN4I_TCON1_BASIC1_REG 0x98 140 #define SUN4I_TCON1_BASIC1_X(width) ((((width) - 1) & 0xfff) << 16) 141 #define SUN4I_TCON1_BASIC1_Y(height) (((height) - 1) & 0xfff) 142 143 #define SUN4I_TCON1_BASIC2_REG 0x9c 144 #define SUN4I_TCON1_BASIC2_X(width) ((((width) - 1) & 0xfff) << 16) 145 #define SUN4I_TCON1_BASIC2_Y(height) (((height) - 1) & 0xfff) 146 147 #define SUN4I_TCON1_BASIC3_REG 0xa0 148 #define SUN4I_TCON1_BASIC3_H_TOTAL(total) ((((total) - 1) & 0x1fff) << 16) 149 #define SUN4I_TCON1_BASIC3_H_BACKPORCH(bp) (((bp) - 1) & 0xfff) 150 151 #define SUN4I_TCON1_BASIC4_REG 0xa4 152 #define SUN4I_TCON1_BASIC4_V_TOTAL(total) (((total) & 0x1fff) << 16) 153 #define SUN4I_TCON1_BASIC4_V_BACKPORCH(bp) (((bp) - 1) & 0xfff) 154 155 #define SUN4I_TCON1_BASIC5_REG 0xa8 156 #define SUN4I_TCON1_BASIC5_H_SYNC(width) ((((width) - 1) & 0x3ff) << 16) 157 #define SUN4I_TCON1_BASIC5_V_SYNC(height) (((height) - 1) & 0x3ff) 158 159 #define SUN4I_TCON1_IO_POL_REG 0xf0 160 #define SUN4I_TCON1_IO_TRI_REG 0xf4 161 162 #define SUN4I_TCON_ECC_FIFO_REG 0xf8 163 #define SUN4I_TCON_ECC_FIFO_EN BIT(3) 164 165 #define SUN4I_TCON_CEU_CTL_REG 0x100 166 #define SUN4I_TCON_CEU_MUL_RR_REG 0x110 167 #define SUN4I_TCON_CEU_MUL_RG_REG 0x114 168 #define SUN4I_TCON_CEU_MUL_RB_REG 0x118 169 #define SUN4I_TCON_CEU_ADD_RC_REG 0x11c 170 #define SUN4I_TCON_CEU_MUL_GR_REG 0x120 171 #define SUN4I_TCON_CEU_MUL_GG_REG 0x124 172 #define SUN4I_TCON_CEU_MUL_GB_REG 0x128 173 #define SUN4I_TCON_CEU_ADD_GC_REG 0x12c 174 #define SUN4I_TCON_CEU_MUL_BR_REG 0x130 175 #define SUN4I_TCON_CEU_MUL_BG_REG 0x134 176 #define SUN4I_TCON_CEU_MUL_BB_REG 0x138 177 #define SUN4I_TCON_CEU_ADD_BC_REG 0x13c 178 #define SUN4I_TCON_CEU_RANGE_R_REG 0x140 179 #define SUN4I_TCON_CEU_RANGE_G_REG 0x144 180 #define SUN4I_TCON_CEU_RANGE_B_REG 0x148 181 182 #define SUN4I_TCON0_CPU_TRI0_REG 0x160 183 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(space) ((((space) - 1) & 0xfff) << 16) 184 #define SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(size) (((size) - 1) & 0xfff) 185 186 #define SUN4I_TCON0_CPU_TRI1_REG 0x164 187 #define SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(num) (((num) - 1) & 0xffff) 188 189 #define SUN4I_TCON0_CPU_TRI2_REG 0x168 190 #define SUN4I_TCON0_CPU_TRI2_START_DELAY(delay) (((delay) & 0xffff) << 16) 191 #define SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(set) ((set) & 0xfff) 192 193 #define SUN4I_TCON_SAFE_PERIOD_REG 0x1f0 194 #define SUN4I_TCON_SAFE_PERIOD_NUM(num) (((num) & 0xfff) << 16) 195 #define SUN4I_TCON_SAFE_PERIOD_MODE(mode) ((mode) & 0x3) 196 197 #define SUN4I_TCON_MUX_CTRL_REG 0x200 198 199 #define SUN4I_TCON0_LVDS_ANA0_REG 0x220 200 #define SUN6I_TCON0_LVDS_ANA0_EN_MB BIT(31) 201 #define SUN6I_TCON0_LVDS_ANA0_EN_LDO BIT(30) 202 #define SUN6I_TCON0_LVDS_ANA0_EN_DRVC BIT(24) 203 #define SUN6I_TCON0_LVDS_ANA0_EN_DRVD(x) (((x) & 0xf) << 20) 204 #define SUN6I_TCON0_LVDS_ANA0_C(x) (((x) & 3) << 17) 205 #define SUN6I_TCON0_LVDS_ANA0_V(x) (((x) & 3) << 8) 206 #define SUN6I_TCON0_LVDS_ANA0_PD(x) (((x) & 3) << 4) 207 208 #define SUN4I_TCON1_FILL_CTL_REG 0x300 209 #define SUN4I_TCON1_FILL_BEG0_REG 0x304 210 #define SUN4I_TCON1_FILL_END0_REG 0x308 211 #define SUN4I_TCON1_FILL_DATA0_REG 0x30c 212 #define SUN4I_TCON1_FILL_BEG1_REG 0x310 213 #define SUN4I_TCON1_FILL_END1_REG 0x314 214 #define SUN4I_TCON1_FILL_DATA1_REG 0x318 215 #define SUN4I_TCON1_FILL_BEG2_REG 0x31c 216 #define SUN4I_TCON1_FILL_END2_REG 0x320 217 #define SUN4I_TCON1_FILL_DATA2_REG 0x324 218 #define SUN4I_TCON1_GAMMA_TABLE_REG 0x400 219 220 #define SUN4I_TCON_MAX_CHANNELS 2 221 222 struct sun4i_tcon; 223 224 struct sun4i_tcon_quirks { 225 bool has_channel_0; /* a83t does not have channel 0 on second TCON */ 226 bool has_channel_1; /* a33 does not have channel 1 */ 227 bool has_lvds_alt; /* Does the LVDS clock have a parent other than the TCON clock? */ 228 bool needs_de_be_mux; /* sun6i needs mux to select backend */ 229 bool needs_edp_reset; /* a80 edp reset needed for tcon0 access */ 230 bool supports_lvds; /* Does the TCON support an LVDS output? */ 231 232 /* callback to handle tcon muxing options */ 233 int (*set_mux)(struct sun4i_tcon *, const struct drm_encoder *); 234 }; 235 236 struct sun4i_tcon { 237 struct device *dev; 238 struct drm_device *drm; 239 struct regmap *regs; 240 241 /* Main bus clock */ 242 struct clk *clk; 243 244 /* Clocks for the TCON channels */ 245 struct clk *sclk0; 246 struct clk *sclk1; 247 248 /* Possible mux for the LVDS clock */ 249 struct clk *lvds_pll; 250 251 /* Pixel clock */ 252 struct clk *dclk; 253 u8 dclk_max_div; 254 u8 dclk_min_div; 255 256 /* Reset control */ 257 struct reset_control *lcd_rst; 258 struct reset_control *lvds_rst; 259 260 struct drm_panel *panel; 261 262 /* Platform adjustments */ 263 const struct sun4i_tcon_quirks *quirks; 264 265 /* Associated crtc */ 266 struct sun4i_crtc *crtc; 267 268 int id; 269 270 /* TCON list management */ 271 struct list_head list; 272 }; 273 274 struct drm_bridge *sun4i_tcon_find_bridge(struct device_node *node); 275 struct drm_panel *sun4i_tcon_find_panel(struct device_node *node); 276 277 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable); 278 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, 279 const struct drm_encoder *encoder, 280 const struct drm_display_mode *mode); 281 void sun4i_tcon_set_status(struct sun4i_tcon *crtc, 282 const struct drm_encoder *encoder, bool enable); 283 284 extern const struct of_device_id sun4i_tcon_of_table[]; 285 286 #endif /* __SUN4I_TCON_H__ */ 287