1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Free Electrons 4 * Copyright (C) 2015 NextThing Co 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 */ 8 9 #include <linux/component.h> 10 #include <linux/ioport.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_modes.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <drm/drm_print.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include <uapi/drm/drm_mode.h> 31 32 #include "sun4i_crtc.h" 33 #include "sun4i_dotclock.h" 34 #include "sun4i_drv.h" 35 #include "sun4i_lvds.h" 36 #include "sun4i_rgb.h" 37 #include "sun4i_tcon.h" 38 #include "sun6i_mipi_dsi.h" 39 #include "sun8i_tcon_top.h" 40 #include "sunxi_engine.h" 41 42 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder) 43 { 44 struct drm_connector *connector; 45 struct drm_connector_list_iter iter; 46 47 drm_connector_list_iter_begin(encoder->dev, &iter); 48 drm_for_each_connector_iter(connector, &iter) 49 if (connector->encoder == encoder) { 50 drm_connector_list_iter_end(&iter); 51 return connector; 52 } 53 drm_connector_list_iter_end(&iter); 54 55 return NULL; 56 } 57 58 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder) 59 { 60 struct drm_connector *connector; 61 struct drm_display_info *info; 62 63 connector = sun4i_tcon_get_connector(encoder); 64 if (!connector) 65 return -EINVAL; 66 67 info = &connector->display_info; 68 if (info->num_bus_formats != 1) 69 return -EINVAL; 70 71 switch (info->bus_formats[0]) { 72 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 73 return 18; 74 75 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 76 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 77 return 24; 78 } 79 80 return -EINVAL; 81 } 82 83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, 84 bool enabled) 85 { 86 struct clk *clk; 87 88 switch (channel) { 89 case 0: 90 WARN_ON(!tcon->quirks->has_channel_0); 91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 92 SUN4I_TCON0_CTL_TCON_ENABLE, 93 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0); 94 clk = tcon->dclk; 95 break; 96 case 1: 97 WARN_ON(!tcon->quirks->has_channel_1); 98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 99 SUN4I_TCON1_CTL_TCON_ENABLE, 100 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0); 101 clk = tcon->sclk1; 102 break; 103 default: 104 DRM_WARN("Unknown channel... doing nothing\n"); 105 return; 106 } 107 108 if (enabled) { 109 clk_prepare_enable(clk); 110 clk_rate_exclusive_get(clk); 111 } else { 112 clk_rate_exclusive_put(clk); 113 clk_disable_unprepare(clk); 114 } 115 } 116 117 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 118 const struct drm_encoder *encoder) 119 { 120 u8 val; 121 122 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 123 SUN6I_TCON0_LVDS_ANA0_C(2) | 124 SUN6I_TCON0_LVDS_ANA0_V(3) | 125 SUN6I_TCON0_LVDS_ANA0_PD(2) | 126 SUN6I_TCON0_LVDS_ANA0_EN_LDO); 127 udelay(2); 128 129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 130 SUN6I_TCON0_LVDS_ANA0_EN_MB, 131 SUN6I_TCON0_LVDS_ANA0_EN_MB); 132 udelay(2); 133 134 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 135 SUN6I_TCON0_LVDS_ANA0_EN_DRVC, 136 SUN6I_TCON0_LVDS_ANA0_EN_DRVC); 137 138 if (sun4i_tcon_get_pixel_depth(encoder) == 18) 139 val = 7; 140 else 141 val = 0xf; 142 143 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 144 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), 145 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); 146 } 147 148 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, 149 const struct drm_encoder *encoder, 150 bool enabled) 151 { 152 if (enabled) { 153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 154 SUN4I_TCON0_LVDS_IF_EN, 155 SUN4I_TCON0_LVDS_IF_EN); 156 if (tcon->quirks->setup_lvds_phy) 157 tcon->quirks->setup_lvds_phy(tcon, encoder); 158 } else { 159 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 160 SUN4I_TCON0_LVDS_IF_EN, 0); 161 } 162 } 163 164 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, 165 const struct drm_encoder *encoder, 166 bool enabled) 167 { 168 bool is_lvds = false; 169 int channel; 170 171 switch (encoder->encoder_type) { 172 case DRM_MODE_ENCODER_LVDS: 173 is_lvds = true; 174 /* Fallthrough */ 175 case DRM_MODE_ENCODER_DSI: 176 case DRM_MODE_ENCODER_NONE: 177 channel = 0; 178 break; 179 case DRM_MODE_ENCODER_TMDS: 180 case DRM_MODE_ENCODER_TVDAC: 181 channel = 1; 182 break; 183 default: 184 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 185 return; 186 } 187 188 if (is_lvds && !enabled) 189 sun4i_tcon_lvds_set_status(tcon, encoder, false); 190 191 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 192 SUN4I_TCON_GCTL_TCON_ENABLE, 193 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0); 194 195 if (is_lvds && enabled) 196 sun4i_tcon_lvds_set_status(tcon, encoder, true); 197 198 sun4i_tcon_channel_set_status(tcon, channel, enabled); 199 } 200 201 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) 202 { 203 u32 mask, val = 0; 204 205 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis"); 206 207 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) | 208 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) | 209 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE; 210 211 if (enable) 212 val = mask; 213 214 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); 215 } 216 EXPORT_SYMBOL(sun4i_tcon_enable_vblank); 217 218 /* 219 * This function is a helper for TCON output muxing. The TCON output 220 * muxing control register in earlier SoCs (without the TCON TOP block) 221 * are located in TCON0. This helper returns a pointer to TCON0's 222 * sun4i_tcon structure, or NULL if not found. 223 */ 224 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm) 225 { 226 struct sun4i_drv *drv = drm->dev_private; 227 struct sun4i_tcon *tcon; 228 229 list_for_each_entry(tcon, &drv->tcon_list, list) 230 if (tcon->id == 0) 231 return tcon; 232 233 dev_warn(drm->dev, 234 "TCON0 not found, display output muxing may not work\n"); 235 236 return NULL; 237 } 238 239 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, 240 const struct drm_encoder *encoder) 241 { 242 int ret = -ENOTSUPP; 243 244 if (tcon->quirks->set_mux) 245 ret = tcon->quirks->set_mux(tcon, encoder); 246 247 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n", 248 encoder->name, encoder->crtc->name, ret); 249 } 250 251 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, 252 int channel) 253 { 254 int delay = mode->vtotal - mode->vdisplay; 255 256 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 257 delay /= 2; 258 259 if (channel == 1) 260 delay -= 2; 261 262 delay = min(delay, 30); 263 264 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); 265 266 return delay; 267 } 268 269 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, 270 const struct drm_display_mode *mode) 271 { 272 /* Configure the dot clock */ 273 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); 274 275 /* Set the resolution */ 276 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, 277 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | 278 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); 279 } 280 281 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, 282 const struct drm_connector *connector) 283 { 284 u32 bus_format = 0; 285 u32 val = 0; 286 287 /* XXX Would this ever happen? */ 288 if (!connector) 289 return; 290 291 /* 292 * FIXME: Undocumented bits 293 * 294 * The whole dithering process and these parameters are not 295 * explained in the vendor documents or BSP kernel code. 296 */ 297 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); 298 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); 299 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); 300 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); 301 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); 302 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); 303 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); 304 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); 305 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); 306 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); 307 308 /* Do dithering if panel only supports 6 bits per color */ 309 if (connector->display_info.bpc == 6) 310 val |= SUN4I_TCON0_FRM_CTL_EN; 311 312 if (connector->display_info.num_bus_formats == 1) 313 bus_format = connector->display_info.bus_formats[0]; 314 315 /* Check the connection format */ 316 switch (bus_format) { 317 case MEDIA_BUS_FMT_RGB565_1X16: 318 /* R and B components are only 5 bits deep */ 319 val |= SUN4I_TCON0_FRM_CTL_MODE_R; 320 val |= SUN4I_TCON0_FRM_CTL_MODE_B; 321 /* Fall through */ 322 case MEDIA_BUS_FMT_RGB666_1X18: 323 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 324 /* Fall through: enable dithering */ 325 val |= SUN4I_TCON0_FRM_CTL_EN; 326 break; 327 } 328 329 /* Write dithering settings */ 330 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); 331 } 332 333 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, 334 const struct drm_encoder *encoder, 335 const struct drm_display_mode *mode) 336 { 337 /* TODO support normal CPU interface modes */ 338 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); 339 struct mipi_dsi_device *device = dsi->device; 340 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); 341 u8 lanes = device->lanes; 342 u32 block_space, start_delay; 343 u32 tcon_div; 344 345 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; 346 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; 347 348 sun4i_tcon0_mode_set_common(tcon, mode); 349 350 /* Set dithering if needed */ 351 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 352 353 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 354 SUN4I_TCON0_CTL_IF_MASK, 355 SUN4I_TCON0_CTL_IF_8080); 356 357 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, 358 SUN4I_TCON_ECC_FIFO_EN); 359 360 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, 361 SUN4I_TCON0_CPU_IF_MODE_DSI | 362 SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH | 363 SUN4I_TCON0_CPU_IF_TRI_FIFO_EN | 364 SUN4I_TCON0_CPU_IF_TRI_EN); 365 366 /* 367 * This looks suspicious, but it works... 368 * 369 * The datasheet says that this should be set higher than 20 * 370 * pixel cycle, but it's not clear what a pixel cycle is. 371 */ 372 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); 373 tcon_div &= GENMASK(6, 0); 374 block_space = mode->htotal * bpp / (tcon_div * lanes); 375 block_space -= mode->hdisplay + 40; 376 377 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, 378 SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) | 379 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); 380 381 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, 382 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); 383 384 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); 385 start_delay = start_delay * mode->crtc_htotal * 149; 386 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; 387 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, 388 SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) | 389 SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay)); 390 391 /* 392 * The Allwinner BSP has a comment that the period should be 393 * the display clock * 15, but uses an hardcoded 3000... 394 */ 395 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, 396 SUN4I_TCON_SAFE_PERIOD_NUM(3000) | 397 SUN4I_TCON_SAFE_PERIOD_MODE(3)); 398 399 /* Enable the output on the pins */ 400 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 401 0xe0000000); 402 } 403 404 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, 405 const struct drm_encoder *encoder, 406 const struct drm_display_mode *mode) 407 { 408 unsigned int bp; 409 u8 clk_delay; 410 u32 reg, val = 0; 411 412 WARN_ON(!tcon->quirks->has_channel_0); 413 414 tcon->dclk_min_div = 7; 415 tcon->dclk_max_div = 7; 416 sun4i_tcon0_mode_set_common(tcon, mode); 417 418 /* Set dithering if needed */ 419 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 420 421 /* Adjust clock delay */ 422 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 423 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 424 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 425 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 426 427 /* 428 * This is called a backporch in the register documentation, 429 * but it really is the back porch + hsync 430 */ 431 bp = mode->crtc_htotal - mode->crtc_hsync_start; 432 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 433 mode->crtc_htotal, bp); 434 435 /* Set horizontal display timings */ 436 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 437 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | 438 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 439 440 /* 441 * This is called a backporch in the register documentation, 442 * but it really is the back porch + hsync 443 */ 444 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 445 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 446 mode->crtc_vtotal, bp); 447 448 /* Set vertical display timings */ 449 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 450 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 451 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 452 453 reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 | 454 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL | 455 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL; 456 if (sun4i_tcon_get_pixel_depth(encoder) == 24) 457 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS; 458 else 459 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS; 460 461 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); 462 463 /* Setup the polarity of the various signals */ 464 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) 465 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 466 467 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) 468 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 469 470 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); 471 472 /* Map output pins to channel 0 */ 473 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 474 SUN4I_TCON_GCTL_IOMAP_MASK, 475 SUN4I_TCON_GCTL_IOMAP_TCON0); 476 477 /* Enable the output on the pins */ 478 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); 479 } 480 481 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 482 const struct drm_encoder *encoder, 483 const struct drm_display_mode *mode) 484 { 485 struct drm_connector *connector = sun4i_tcon_get_connector(encoder); 486 const struct drm_display_info *info = &connector->display_info; 487 unsigned int bp, hsync, vsync; 488 u8 clk_delay; 489 u32 val = 0; 490 491 WARN_ON(!tcon->quirks->has_channel_0); 492 493 tcon->dclk_min_div = tcon->quirks->dclk_min_div; 494 tcon->dclk_max_div = 127; 495 sun4i_tcon0_mode_set_common(tcon, mode); 496 497 /* Set dithering if needed */ 498 sun4i_tcon0_mode_set_dithering(tcon, connector); 499 500 /* Adjust clock delay */ 501 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 502 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 503 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 504 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 505 506 /* 507 * This is called a backporch in the register documentation, 508 * but it really is the back porch + hsync 509 */ 510 bp = mode->crtc_htotal - mode->crtc_hsync_start; 511 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 512 mode->crtc_htotal, bp); 513 514 /* Set horizontal display timings */ 515 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 516 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | 517 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 518 519 /* 520 * This is called a backporch in the register documentation, 521 * but it really is the back porch + hsync 522 */ 523 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 524 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 525 mode->crtc_vtotal, bp); 526 527 /* Set vertical display timings */ 528 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 529 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 530 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 531 532 /* Set Hsync and Vsync length */ 533 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 534 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 535 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 536 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, 537 SUN4I_TCON0_BASIC3_V_SYNC(vsync) | 538 SUN4I_TCON0_BASIC3_H_SYNC(hsync)); 539 540 /* Setup the polarity of the various signals */ 541 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 542 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 543 544 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 545 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 546 547 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 548 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; 549 550 /* 551 * On A20 and similar SoCs, the only way to achieve Positive Edge 552 * (Rising Edge), is setting dclk clock phase to 2/3(240°). 553 * By default TCON works in Negative Edge(Falling Edge), 554 * this is why phase is set to 0 in that case. 555 * Unfortunately there's no way to logically invert dclk through 556 * IO_POL register. 557 * The only acceptable way to work, triple checked with scope, 558 * is using clock phase set to 0° for Negative Edge and set to 240° 559 * for Positive Edge. 560 * On A33 and similar SoCs there would be a 90° phase option, 561 * but it divides also dclk by 2. 562 * Following code is a way to avoid quirks all around TCON 563 * and DOTCLOCK drivers. 564 */ 565 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 566 clk_set_phase(tcon->dclk, 240); 567 568 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 569 clk_set_phase(tcon->dclk, 0); 570 571 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, 572 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | 573 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE | 574 SUN4I_TCON0_IO_POL_DE_NEGATIVE, 575 val); 576 577 /* Map output pins to channel 0 */ 578 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 579 SUN4I_TCON_GCTL_IOMAP_MASK, 580 SUN4I_TCON_GCTL_IOMAP_TCON0); 581 582 /* Enable the output on the pins */ 583 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); 584 } 585 586 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 587 const struct drm_display_mode *mode) 588 { 589 unsigned int bp, hsync, vsync, vtotal; 590 u8 clk_delay; 591 u32 val; 592 593 WARN_ON(!tcon->quirks->has_channel_1); 594 595 /* Configure the dot clock */ 596 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); 597 598 /* Adjust clock delay */ 599 clk_delay = sun4i_tcon_get_clk_delay(mode, 1); 600 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 601 SUN4I_TCON1_CTL_CLK_DELAY_MASK, 602 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay)); 603 604 /* Set interlaced mode */ 605 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 606 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE; 607 else 608 val = 0; 609 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 610 SUN4I_TCON1_CTL_INTERLACE_ENABLE, 611 val); 612 613 /* Set the input resolution */ 614 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, 615 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | 616 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); 617 618 /* Set the upscaling resolution */ 619 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, 620 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | 621 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); 622 623 /* Set the output resolution */ 624 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, 625 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | 626 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); 627 628 /* Set horizontal display timings */ 629 bp = mode->crtc_htotal - mode->crtc_hsync_start; 630 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 631 mode->htotal, bp); 632 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, 633 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | 634 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)); 635 636 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 637 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 638 mode->crtc_vtotal, bp); 639 640 /* 641 * The vertical resolution needs to be doubled in all 642 * cases. We could use crtc_vtotal and always multiply by two, 643 * but that leads to a rounding error in interlace when vtotal 644 * is odd. 645 * 646 * This happens with TV's PAL for example, where vtotal will 647 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be 648 * 624, which apparently confuses the hardware. 649 * 650 * To work around this, we will always use vtotal, and 651 * multiply by two only if we're not in interlace. 652 */ 653 vtotal = mode->vtotal; 654 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) 655 vtotal = vtotal * 2; 656 657 /* Set vertical display timings */ 658 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, 659 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) | 660 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)); 661 662 /* Set Hsync and Vsync length */ 663 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 664 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 665 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 666 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, 667 SUN4I_TCON1_BASIC5_V_SYNC(vsync) | 668 SUN4I_TCON1_BASIC5_H_SYNC(hsync)); 669 670 /* Map output pins to channel 1 */ 671 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 672 SUN4I_TCON_GCTL_IOMAP_MASK, 673 SUN4I_TCON_GCTL_IOMAP_TCON1); 674 } 675 676 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, 677 const struct drm_encoder *encoder, 678 const struct drm_display_mode *mode) 679 { 680 switch (encoder->encoder_type) { 681 case DRM_MODE_ENCODER_DSI: 682 /* DSI is tied to special case of CPU interface */ 683 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); 684 break; 685 case DRM_MODE_ENCODER_LVDS: 686 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); 687 break; 688 case DRM_MODE_ENCODER_NONE: 689 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); 690 sun4i_tcon_set_mux(tcon, 0, encoder); 691 break; 692 case DRM_MODE_ENCODER_TVDAC: 693 case DRM_MODE_ENCODER_TMDS: 694 sun4i_tcon1_mode_set(tcon, mode); 695 sun4i_tcon_set_mux(tcon, 1, encoder); 696 break; 697 default: 698 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 699 } 700 } 701 EXPORT_SYMBOL(sun4i_tcon_mode_set); 702 703 static void sun4i_tcon_finish_page_flip(struct drm_device *dev, 704 struct sun4i_crtc *scrtc) 705 { 706 unsigned long flags; 707 708 spin_lock_irqsave(&dev->event_lock, flags); 709 if (scrtc->event) { 710 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); 711 drm_crtc_vblank_put(&scrtc->crtc); 712 scrtc->event = NULL; 713 } 714 spin_unlock_irqrestore(&dev->event_lock, flags); 715 } 716 717 static irqreturn_t sun4i_tcon_handler(int irq, void *private) 718 { 719 struct sun4i_tcon *tcon = private; 720 struct drm_device *drm = tcon->drm; 721 struct sun4i_crtc *scrtc = tcon->crtc; 722 struct sunxi_engine *engine = scrtc->engine; 723 unsigned int status; 724 725 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); 726 727 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) | 728 SUN4I_TCON_GINT0_VBLANK_INT(1) | 729 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT))) 730 return IRQ_NONE; 731 732 drm_crtc_handle_vblank(&scrtc->crtc); 733 sun4i_tcon_finish_page_flip(drm, scrtc); 734 735 /* Acknowledge the interrupt */ 736 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, 737 SUN4I_TCON_GINT0_VBLANK_INT(0) | 738 SUN4I_TCON_GINT0_VBLANK_INT(1) | 739 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT, 740 0); 741 742 if (engine->ops->vblank_quirk) 743 engine->ops->vblank_quirk(engine); 744 745 return IRQ_HANDLED; 746 } 747 748 static int sun4i_tcon_init_clocks(struct device *dev, 749 struct sun4i_tcon *tcon) 750 { 751 tcon->clk = devm_clk_get(dev, "ahb"); 752 if (IS_ERR(tcon->clk)) { 753 dev_err(dev, "Couldn't get the TCON bus clock\n"); 754 return PTR_ERR(tcon->clk); 755 } 756 clk_prepare_enable(tcon->clk); 757 758 if (tcon->quirks->has_channel_0) { 759 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); 760 if (IS_ERR(tcon->sclk0)) { 761 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); 762 return PTR_ERR(tcon->sclk0); 763 } 764 } 765 clk_prepare_enable(tcon->sclk0); 766 767 if (tcon->quirks->has_channel_1) { 768 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); 769 if (IS_ERR(tcon->sclk1)) { 770 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); 771 return PTR_ERR(tcon->sclk1); 772 } 773 } 774 775 return 0; 776 } 777 778 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) 779 { 780 clk_disable_unprepare(tcon->sclk0); 781 clk_disable_unprepare(tcon->clk); 782 } 783 784 static int sun4i_tcon_init_irq(struct device *dev, 785 struct sun4i_tcon *tcon) 786 { 787 struct platform_device *pdev = to_platform_device(dev); 788 int irq, ret; 789 790 irq = platform_get_irq(pdev, 0); 791 if (irq < 0) { 792 dev_err(dev, "Couldn't retrieve the TCON interrupt\n"); 793 return irq; 794 } 795 796 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0, 797 dev_name(dev), tcon); 798 if (ret) { 799 dev_err(dev, "Couldn't request the IRQ\n"); 800 return ret; 801 } 802 803 return 0; 804 } 805 806 static struct regmap_config sun4i_tcon_regmap_config = { 807 .reg_bits = 32, 808 .val_bits = 32, 809 .reg_stride = 4, 810 .max_register = 0x800, 811 }; 812 813 static int sun4i_tcon_init_regmap(struct device *dev, 814 struct sun4i_tcon *tcon) 815 { 816 struct platform_device *pdev = to_platform_device(dev); 817 struct resource *res; 818 void __iomem *regs; 819 820 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 821 regs = devm_ioremap_resource(dev, res); 822 if (IS_ERR(regs)) 823 return PTR_ERR(regs); 824 825 tcon->regs = devm_regmap_init_mmio(dev, regs, 826 &sun4i_tcon_regmap_config); 827 if (IS_ERR(tcon->regs)) { 828 dev_err(dev, "Couldn't create the TCON regmap\n"); 829 return PTR_ERR(tcon->regs); 830 } 831 832 /* Make sure the TCON is disabled and all IRQs are off */ 833 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); 834 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); 835 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); 836 837 /* Disable IO lines and set them to tristate */ 838 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); 839 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); 840 841 return 0; 842 } 843 844 /* 845 * On SoCs with the old display pipeline design (Display Engine 1.0), 846 * the TCON is always tied to just one backend. Hence we can traverse 847 * the of_graph upwards to find the backend our tcon is connected to, 848 * and take its ID as our own. 849 * 850 * We can either identify backends from their compatible strings, which 851 * means maintaining a large list of them. Or, since the backend is 852 * registered and binded before the TCON, we can just go through the 853 * list of registered backends and compare the device node. 854 * 855 * As the structures now store engines instead of backends, here this 856 * function in fact searches the corresponding engine, and the ID is 857 * requested via the get_id function of the engine. 858 */ 859 static struct sunxi_engine * 860 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv, 861 struct device_node *node, 862 u32 port_id) 863 { 864 struct device_node *port, *ep, *remote; 865 struct sunxi_engine *engine = ERR_PTR(-EINVAL); 866 u32 reg = 0; 867 868 port = of_graph_get_port_by_id(node, port_id); 869 if (!port) 870 return ERR_PTR(-EINVAL); 871 872 /* 873 * This only works if there is only one path from the TCON 874 * to any display engine. Otherwise the probe order of the 875 * TCONs and display engines is not guaranteed. They may 876 * either bind to the wrong one, or worse, bind to the same 877 * one if additional checks are not done. 878 * 879 * Bail out if there are multiple input connections. 880 */ 881 if (of_get_available_child_count(port) != 1) 882 goto out_put_port; 883 884 /* Get the first connection without specifying an ID */ 885 ep = of_get_next_available_child(port, NULL); 886 if (!ep) 887 goto out_put_port; 888 889 remote = of_graph_get_remote_port_parent(ep); 890 if (!remote) 891 goto out_put_ep; 892 893 /* does this node match any registered engines? */ 894 list_for_each_entry(engine, &drv->engine_list, list) 895 if (remote == engine->node) 896 goto out_put_remote; 897 898 /* 899 * According to device tree binding input ports have even id 900 * number and output ports have odd id. Since component with 901 * more than one input and one output (TCON TOP) exits, correct 902 * remote input id has to be calculated by subtracting 1 from 903 * remote output id. If this for some reason can't be done, 0 904 * is used as input port id. 905 */ 906 of_node_put(port); 907 port = of_graph_get_remote_port(ep); 908 if (!of_property_read_u32(port, "reg", ®) && reg > 0) 909 reg -= 1; 910 911 /* keep looking through upstream ports */ 912 engine = sun4i_tcon_find_engine_traverse(drv, remote, reg); 913 914 out_put_remote: 915 of_node_put(remote); 916 out_put_ep: 917 of_node_put(ep); 918 out_put_port: 919 of_node_put(port); 920 921 return engine; 922 } 923 924 /* 925 * The device tree binding says that the remote endpoint ID of any 926 * connection between components, up to and including the TCON, of 927 * the display pipeline should be equal to the actual ID of the local 928 * component. Thus we can look at any one of the input connections of 929 * the TCONs, and use that connection's remote endpoint ID as our own. 930 * 931 * Since the user of this function already finds the input port, 932 * the port is passed in directly without further checks. 933 */ 934 static int sun4i_tcon_of_get_id_from_port(struct device_node *port) 935 { 936 struct device_node *ep; 937 int ret = -EINVAL; 938 939 /* try finding an upstream endpoint */ 940 for_each_available_child_of_node(port, ep) { 941 struct device_node *remote; 942 u32 reg; 943 944 remote = of_graph_get_remote_endpoint(ep); 945 if (!remote) 946 continue; 947 948 ret = of_property_read_u32(remote, "reg", ®); 949 if (ret) 950 continue; 951 952 ret = reg; 953 } 954 955 return ret; 956 } 957 958 /* 959 * Once we know the TCON's id, we can look through the list of 960 * engines to find a matching one. We assume all engines have 961 * been probed and added to the list. 962 */ 963 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv, 964 int id) 965 { 966 struct sunxi_engine *engine; 967 968 list_for_each_entry(engine, &drv->engine_list, list) 969 if (engine->id == id) 970 return engine; 971 972 return ERR_PTR(-EINVAL); 973 } 974 975 static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node) 976 { 977 struct device_node *remote; 978 bool ret = false; 979 980 remote = of_graph_get_remote_node(node, 0, -1); 981 if (remote) { 982 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 983 of_match_node(sun8i_tcon_top_of_table, remote)); 984 of_node_put(remote); 985 } 986 987 return ret; 988 } 989 990 static int sun4i_tcon_get_index(struct sun4i_drv *drv) 991 { 992 struct list_head *pos; 993 int size = 0; 994 995 /* 996 * Because TCON is added to the list at the end of the probe 997 * (after this function is called), index of the current TCON 998 * will be same as current TCON list size. 999 */ 1000 list_for_each(pos, &drv->tcon_list) 1001 ++size; 1002 1003 return size; 1004 } 1005 1006 /* 1007 * On SoCs with the old display pipeline design (Display Engine 1.0), 1008 * we assumed the TCON was always tied to just one backend. However 1009 * this proved not to be the case. On the A31, the TCON can select 1010 * either backend as its source. On the A20 (and likely on the A10), 1011 * the backend can choose which TCON to output to. 1012 * 1013 * The device tree binding says that the remote endpoint ID of any 1014 * connection between components, up to and including the TCON, of 1015 * the display pipeline should be equal to the actual ID of the local 1016 * component. Thus we should be able to look at any one of the input 1017 * connections of the TCONs, and use that connection's remote endpoint 1018 * ID as our own. 1019 * 1020 * However the connections between the backend and TCON were assumed 1021 * to be always singular, and their endpoit IDs were all incorrectly 1022 * set to 0. This means for these old device trees, we cannot just look 1023 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be 1024 * incorrectly identified as TCON0. 1025 * 1026 * This function first checks if the TCON node has 2 input endpoints. 1027 * If so, then the device tree is a corrected version, and it will use 1028 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above 1029 * to fetch the ID and engine directly. If not, then it is likely an 1030 * old device trees, where the endpoint IDs were incorrect, but did not 1031 * have endpoint connections between the backend and TCON across 1032 * different display pipelines. It will fall back to the old method of 1033 * traversing the of_graph to try and find a matching engine by device 1034 * node. 1035 * 1036 * In the case of single display pipeline device trees, either method 1037 * works. 1038 */ 1039 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv, 1040 struct device_node *node) 1041 { 1042 struct device_node *port; 1043 struct sunxi_engine *engine; 1044 1045 port = of_graph_get_port_by_id(node, 0); 1046 if (!port) 1047 return ERR_PTR(-EINVAL); 1048 1049 /* 1050 * Is this a corrected device tree with cross pipeline 1051 * connections between the backend and TCON? 1052 */ 1053 if (of_get_child_count(port) > 1) { 1054 int id; 1055 1056 /* 1057 * When pipeline has the same number of TCONs and engines which 1058 * are represented by frontends/backends (DE1) or mixers (DE2), 1059 * we match them by their respective IDs. However, if pipeline 1060 * contains TCON TOP, chances are that there are either more 1061 * TCONs than engines (R40) or TCONs with non-consecutive ids. 1062 * (H6). In that case it's easier just use TCON index in list 1063 * as an id. That means that on R40, any 2 TCONs can be enabled 1064 * in DT out of 4 (there are 2 mixers). Due to the design of 1065 * TCON TOP, remaining 2 TCONs can't be connected to anything 1066 * anyway. 1067 */ 1068 if (sun4i_tcon_connected_to_tcon_top(node)) 1069 id = sun4i_tcon_get_index(drv); 1070 else 1071 id = sun4i_tcon_of_get_id_from_port(port); 1072 1073 /* Get our engine by matching our ID */ 1074 engine = sun4i_tcon_get_engine_by_id(drv, id); 1075 1076 of_node_put(port); 1077 return engine; 1078 } 1079 1080 /* Fallback to old method by traversing input endpoints */ 1081 of_node_put(port); 1082 return sun4i_tcon_find_engine_traverse(drv, node, 0); 1083 } 1084 1085 static int sun4i_tcon_bind(struct device *dev, struct device *master, 1086 void *data) 1087 { 1088 struct drm_device *drm = data; 1089 struct sun4i_drv *drv = drm->dev_private; 1090 struct sunxi_engine *engine; 1091 struct device_node *remote; 1092 struct sun4i_tcon *tcon; 1093 struct reset_control *edp_rstc; 1094 bool has_lvds_rst, has_lvds_alt, can_lvds; 1095 int ret; 1096 1097 engine = sun4i_tcon_find_engine(drv, dev->of_node); 1098 if (IS_ERR(engine)) { 1099 dev_err(dev, "Couldn't find matching engine\n"); 1100 return -EPROBE_DEFER; 1101 } 1102 1103 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); 1104 if (!tcon) 1105 return -ENOMEM; 1106 dev_set_drvdata(dev, tcon); 1107 tcon->drm = drm; 1108 tcon->dev = dev; 1109 tcon->id = engine->id; 1110 tcon->quirks = of_device_get_match_data(dev); 1111 1112 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); 1113 if (IS_ERR(tcon->lcd_rst)) { 1114 dev_err(dev, "Couldn't get our reset line\n"); 1115 return PTR_ERR(tcon->lcd_rst); 1116 } 1117 1118 if (tcon->quirks->needs_edp_reset) { 1119 edp_rstc = devm_reset_control_get_shared(dev, "edp"); 1120 if (IS_ERR(edp_rstc)) { 1121 dev_err(dev, "Couldn't get edp reset line\n"); 1122 return PTR_ERR(edp_rstc); 1123 } 1124 1125 ret = reset_control_deassert(edp_rstc); 1126 if (ret) { 1127 dev_err(dev, "Couldn't deassert edp reset line\n"); 1128 return ret; 1129 } 1130 } 1131 1132 /* Make sure our TCON is reset */ 1133 ret = reset_control_reset(tcon->lcd_rst); 1134 if (ret) { 1135 dev_err(dev, "Couldn't deassert our reset line\n"); 1136 return ret; 1137 } 1138 1139 if (tcon->quirks->supports_lvds) { 1140 /* 1141 * This can only be made optional since we've had DT 1142 * nodes without the LVDS reset properties. 1143 * 1144 * If the property is missing, just disable LVDS, and 1145 * print a warning. 1146 */ 1147 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); 1148 if (IS_ERR(tcon->lvds_rst)) { 1149 dev_err(dev, "Couldn't get our reset line\n"); 1150 return PTR_ERR(tcon->lvds_rst); 1151 } else if (tcon->lvds_rst) { 1152 has_lvds_rst = true; 1153 reset_control_reset(tcon->lvds_rst); 1154 } else { 1155 has_lvds_rst = false; 1156 } 1157 1158 /* 1159 * This can only be made optional since we've had DT 1160 * nodes without the LVDS reset properties. 1161 * 1162 * If the property is missing, just disable LVDS, and 1163 * print a warning. 1164 */ 1165 if (tcon->quirks->has_lvds_alt) { 1166 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); 1167 if (IS_ERR(tcon->lvds_pll)) { 1168 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { 1169 has_lvds_alt = false; 1170 } else { 1171 dev_err(dev, "Couldn't get the LVDS PLL\n"); 1172 return PTR_ERR(tcon->lvds_pll); 1173 } 1174 } else { 1175 has_lvds_alt = true; 1176 } 1177 } 1178 1179 if (!has_lvds_rst || 1180 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { 1181 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n"); 1182 dev_warn(dev, "LVDS output disabled\n"); 1183 can_lvds = false; 1184 } else { 1185 can_lvds = true; 1186 } 1187 } else { 1188 can_lvds = false; 1189 } 1190 1191 ret = sun4i_tcon_init_clocks(dev, tcon); 1192 if (ret) { 1193 dev_err(dev, "Couldn't init our TCON clocks\n"); 1194 goto err_assert_reset; 1195 } 1196 1197 ret = sun4i_tcon_init_regmap(dev, tcon); 1198 if (ret) { 1199 dev_err(dev, "Couldn't init our TCON regmap\n"); 1200 goto err_free_clocks; 1201 } 1202 1203 if (tcon->quirks->has_channel_0) { 1204 ret = sun4i_dclk_create(dev, tcon); 1205 if (ret) { 1206 dev_err(dev, "Couldn't create our TCON dot clock\n"); 1207 goto err_free_clocks; 1208 } 1209 } 1210 1211 ret = sun4i_tcon_init_irq(dev, tcon); 1212 if (ret) { 1213 dev_err(dev, "Couldn't init our TCON interrupts\n"); 1214 goto err_free_dotclock; 1215 } 1216 1217 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); 1218 if (IS_ERR(tcon->crtc)) { 1219 dev_err(dev, "Couldn't create our CRTC\n"); 1220 ret = PTR_ERR(tcon->crtc); 1221 goto err_free_dotclock; 1222 } 1223 1224 if (tcon->quirks->has_channel_0) { 1225 /* 1226 * If we have an LVDS panel connected to the TCON, we should 1227 * just probe the LVDS connector. Otherwise, just probe RGB as 1228 * we used to. 1229 */ 1230 remote = of_graph_get_remote_node(dev->of_node, 1, 0); 1231 if (of_device_is_compatible(remote, "panel-lvds")) 1232 if (can_lvds) 1233 ret = sun4i_lvds_init(drm, tcon); 1234 else 1235 ret = -EINVAL; 1236 else 1237 ret = sun4i_rgb_init(drm, tcon); 1238 of_node_put(remote); 1239 1240 if (ret < 0) 1241 goto err_free_dotclock; 1242 } 1243 1244 if (tcon->quirks->needs_de_be_mux) { 1245 /* 1246 * We assume there is no dynamic muxing of backends 1247 * and TCONs, so we select the backend with same ID. 1248 * 1249 * While dynamic selection might be interesting, since 1250 * the CRTC is tied to the TCON, while the layers are 1251 * tied to the backends, this means, we will need to 1252 * switch between groups of layers. There might not be 1253 * a way to represent this constraint in DRM. 1254 */ 1255 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 1256 SUN4I_TCON0_CTL_SRC_SEL_MASK, 1257 tcon->id); 1258 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 1259 SUN4I_TCON1_CTL_SRC_SEL_MASK, 1260 tcon->id); 1261 } 1262 1263 list_add_tail(&tcon->list, &drv->tcon_list); 1264 1265 return 0; 1266 1267 err_free_dotclock: 1268 if (tcon->quirks->has_channel_0) 1269 sun4i_dclk_free(tcon); 1270 err_free_clocks: 1271 sun4i_tcon_free_clocks(tcon); 1272 err_assert_reset: 1273 reset_control_assert(tcon->lcd_rst); 1274 return ret; 1275 } 1276 1277 static void sun4i_tcon_unbind(struct device *dev, struct device *master, 1278 void *data) 1279 { 1280 struct sun4i_tcon *tcon = dev_get_drvdata(dev); 1281 1282 list_del(&tcon->list); 1283 if (tcon->quirks->has_channel_0) 1284 sun4i_dclk_free(tcon); 1285 sun4i_tcon_free_clocks(tcon); 1286 } 1287 1288 static const struct component_ops sun4i_tcon_ops = { 1289 .bind = sun4i_tcon_bind, 1290 .unbind = sun4i_tcon_unbind, 1291 }; 1292 1293 static int sun4i_tcon_probe(struct platform_device *pdev) 1294 { 1295 struct device_node *node = pdev->dev.of_node; 1296 const struct sun4i_tcon_quirks *quirks; 1297 struct drm_bridge *bridge; 1298 struct drm_panel *panel; 1299 int ret; 1300 1301 quirks = of_device_get_match_data(&pdev->dev); 1302 1303 /* panels and bridges are present only on TCONs with channel 0 */ 1304 if (quirks->has_channel_0) { 1305 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); 1306 if (ret == -EPROBE_DEFER) 1307 return ret; 1308 } 1309 1310 return component_add(&pdev->dev, &sun4i_tcon_ops); 1311 } 1312 1313 static int sun4i_tcon_remove(struct platform_device *pdev) 1314 { 1315 component_del(&pdev->dev, &sun4i_tcon_ops); 1316 1317 return 0; 1318 } 1319 1320 /* platform specific TCON muxing callbacks */ 1321 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, 1322 const struct drm_encoder *encoder) 1323 { 1324 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1325 u32 shift; 1326 1327 if (!tcon0) 1328 return -EINVAL; 1329 1330 switch (encoder->encoder_type) { 1331 case DRM_MODE_ENCODER_TMDS: 1332 /* HDMI */ 1333 shift = 8; 1334 break; 1335 default: 1336 return -EINVAL; 1337 } 1338 1339 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1340 0x3 << shift, tcon->id << shift); 1341 1342 return 0; 1343 } 1344 1345 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, 1346 const struct drm_encoder *encoder) 1347 { 1348 u32 val; 1349 1350 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1351 val = 1; 1352 else 1353 val = 0; 1354 1355 /* 1356 * FIXME: Undocumented bits 1357 */ 1358 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); 1359 } 1360 1361 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, 1362 const struct drm_encoder *encoder) 1363 { 1364 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1365 u32 shift; 1366 1367 if (!tcon0) 1368 return -EINVAL; 1369 1370 switch (encoder->encoder_type) { 1371 case DRM_MODE_ENCODER_TMDS: 1372 /* HDMI */ 1373 shift = 8; 1374 break; 1375 default: 1376 /* TODO A31 has MIPI DSI but A31s does not */ 1377 return -EINVAL; 1378 } 1379 1380 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1381 0x3 << shift, tcon->id << shift); 1382 1383 return 0; 1384 } 1385 1386 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, 1387 const struct drm_encoder *encoder) 1388 { 1389 struct device_node *port, *remote; 1390 struct platform_device *pdev; 1391 int id, ret; 1392 1393 /* find TCON TOP platform device and TCON id */ 1394 1395 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); 1396 if (!port) 1397 return -EINVAL; 1398 1399 id = sun4i_tcon_of_get_id_from_port(port); 1400 of_node_put(port); 1401 1402 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); 1403 if (!remote) 1404 return -EINVAL; 1405 1406 pdev = of_find_device_by_node(remote); 1407 of_node_put(remote); 1408 if (!pdev) 1409 return -EINVAL; 1410 1411 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1412 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { 1413 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); 1414 if (ret) 1415 return ret; 1416 } 1417 1418 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) { 1419 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); 1420 if (ret) 1421 return ret; 1422 } 1423 1424 return 0; 1425 } 1426 1427 static const struct sun4i_tcon_quirks sun4i_a10_quirks = { 1428 .has_channel_0 = true, 1429 .has_channel_1 = true, 1430 .dclk_min_div = 4, 1431 .set_mux = sun4i_a10_tcon_set_mux, 1432 }; 1433 1434 static const struct sun4i_tcon_quirks sun5i_a13_quirks = { 1435 .has_channel_0 = true, 1436 .has_channel_1 = true, 1437 .dclk_min_div = 4, 1438 .set_mux = sun5i_a13_tcon_set_mux, 1439 }; 1440 1441 static const struct sun4i_tcon_quirks sun6i_a31_quirks = { 1442 .has_channel_0 = true, 1443 .has_channel_1 = true, 1444 .has_lvds_alt = true, 1445 .needs_de_be_mux = true, 1446 .dclk_min_div = 1, 1447 .set_mux = sun6i_tcon_set_mux, 1448 }; 1449 1450 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = { 1451 .has_channel_0 = true, 1452 .has_channel_1 = true, 1453 .needs_de_be_mux = true, 1454 .dclk_min_div = 1, 1455 }; 1456 1457 static const struct sun4i_tcon_quirks sun7i_a20_quirks = { 1458 .has_channel_0 = true, 1459 .has_channel_1 = true, 1460 .dclk_min_div = 4, 1461 /* Same display pipeline structure as A10 */ 1462 .set_mux = sun4i_a10_tcon_set_mux, 1463 }; 1464 1465 static const struct sun4i_tcon_quirks sun8i_a33_quirks = { 1466 .has_channel_0 = true, 1467 .has_lvds_alt = true, 1468 .dclk_min_div = 1, 1469 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1470 }; 1471 1472 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { 1473 .supports_lvds = true, 1474 .has_channel_0 = true, 1475 .dclk_min_div = 1, 1476 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1477 }; 1478 1479 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { 1480 .has_channel_1 = true, 1481 }; 1482 1483 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { 1484 .has_channel_1 = true, 1485 .set_mux = sun8i_r40_tcon_tv_set_mux, 1486 }; 1487 1488 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = { 1489 .has_channel_0 = true, 1490 .dclk_min_div = 1, 1491 }; 1492 1493 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = { 1494 .has_channel_0 = true, 1495 .needs_edp_reset = true, 1496 .dclk_min_div = 1, 1497 }; 1498 1499 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = { 1500 .has_channel_1 = true, 1501 .needs_edp_reset = true, 1502 }; 1503 1504 /* sun4i_drv uses this list to check if a device node is a TCON */ 1505 const struct of_device_id sun4i_tcon_of_table[] = { 1506 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks }, 1507 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks }, 1508 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks }, 1509 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks }, 1510 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks }, 1511 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_quirks }, 1512 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks }, 1513 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks }, 1514 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks }, 1515 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks }, 1516 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks }, 1517 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks }, 1518 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks }, 1519 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks }, 1520 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks }, 1521 { } 1522 }; 1523 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table); 1524 EXPORT_SYMBOL(sun4i_tcon_of_table); 1525 1526 static struct platform_driver sun4i_tcon_platform_driver = { 1527 .probe = sun4i_tcon_probe, 1528 .remove = sun4i_tcon_remove, 1529 .driver = { 1530 .name = "sun4i-tcon", 1531 .of_match_table = sun4i_tcon_of_table, 1532 }, 1533 }; 1534 module_platform_driver(sun4i_tcon_platform_driver); 1535 1536 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1537 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver"); 1538 MODULE_LICENSE("GPL"); 1539