1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Free Electrons 4 * Copyright (C) 2015 NextThing Co 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 */ 8 9 #include <linux/component.h> 10 #include <linux/ioport.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_modes.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <drm/drm_print.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include <uapi/drm/drm_mode.h> 31 32 #include "sun4i_crtc.h" 33 #include "sun4i_dotclock.h" 34 #include "sun4i_drv.h" 35 #include "sun4i_lvds.h" 36 #include "sun4i_rgb.h" 37 #include "sun4i_tcon.h" 38 #include "sun6i_mipi_dsi.h" 39 #include "sun8i_tcon_top.h" 40 #include "sunxi_engine.h" 41 42 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder) 43 { 44 struct drm_connector *connector; 45 struct drm_connector_list_iter iter; 46 47 drm_connector_list_iter_begin(encoder->dev, &iter); 48 drm_for_each_connector_iter(connector, &iter) 49 if (connector->encoder == encoder) { 50 drm_connector_list_iter_end(&iter); 51 return connector; 52 } 53 drm_connector_list_iter_end(&iter); 54 55 return NULL; 56 } 57 58 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder) 59 { 60 struct drm_connector *connector; 61 struct drm_display_info *info; 62 63 connector = sun4i_tcon_get_connector(encoder); 64 if (!connector) 65 return -EINVAL; 66 67 info = &connector->display_info; 68 if (info->num_bus_formats != 1) 69 return -EINVAL; 70 71 switch (info->bus_formats[0]) { 72 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 73 return 18; 74 75 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 76 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 77 return 24; 78 } 79 80 return -EINVAL; 81 } 82 83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, 84 bool enabled) 85 { 86 struct clk *clk; 87 88 switch (channel) { 89 case 0: 90 WARN_ON(!tcon->quirks->has_channel_0); 91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 92 SUN4I_TCON0_CTL_TCON_ENABLE, 93 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0); 94 clk = tcon->dclk; 95 break; 96 case 1: 97 WARN_ON(!tcon->quirks->has_channel_1); 98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 99 SUN4I_TCON1_CTL_TCON_ENABLE, 100 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0); 101 clk = tcon->sclk1; 102 break; 103 default: 104 DRM_WARN("Unknown channel... doing nothing\n"); 105 return; 106 } 107 108 if (enabled) { 109 clk_prepare_enable(clk); 110 clk_rate_exclusive_get(clk); 111 } else { 112 clk_rate_exclusive_put(clk); 113 clk_disable_unprepare(clk); 114 } 115 } 116 117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 118 const struct drm_encoder *encoder) 119 { 120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 121 SUN4I_TCON0_LVDS_ANA0_CK_EN | 122 SUN4I_TCON0_LVDS_ANA0_REG_V | 123 SUN4I_TCON0_LVDS_ANA0_REG_C | 124 SUN4I_TCON0_LVDS_ANA0_EN_MB | 125 SUN4I_TCON0_LVDS_ANA0_PD | 126 SUN4I_TCON0_LVDS_ANA0_DCHS); 127 128 udelay(2); /* delay at least 1200 ns */ 129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, 130 SUN4I_TCON0_LVDS_ANA1_INIT, 131 SUN4I_TCON0_LVDS_ANA1_INIT); 132 udelay(1); /* delay at least 120 ns */ 133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, 134 SUN4I_TCON0_LVDS_ANA1_UPDATE, 135 SUN4I_TCON0_LVDS_ANA1_UPDATE); 136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 137 SUN4I_TCON0_LVDS_ANA0_EN_MB, 138 SUN4I_TCON0_LVDS_ANA0_EN_MB); 139 } 140 141 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 142 const struct drm_encoder *encoder) 143 { 144 u8 val; 145 146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 147 SUN6I_TCON0_LVDS_ANA0_C(2) | 148 SUN6I_TCON0_LVDS_ANA0_V(3) | 149 SUN6I_TCON0_LVDS_ANA0_PD(2) | 150 SUN6I_TCON0_LVDS_ANA0_EN_LDO); 151 udelay(2); 152 153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 154 SUN6I_TCON0_LVDS_ANA0_EN_MB, 155 SUN6I_TCON0_LVDS_ANA0_EN_MB); 156 udelay(2); 157 158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 159 SUN6I_TCON0_LVDS_ANA0_EN_DRVC, 160 SUN6I_TCON0_LVDS_ANA0_EN_DRVC); 161 162 if (sun4i_tcon_get_pixel_depth(encoder) == 18) 163 val = 7; 164 else 165 val = 0xf; 166 167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 168 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), 169 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); 170 } 171 172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, 173 const struct drm_encoder *encoder, 174 bool enabled) 175 { 176 if (enabled) { 177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 178 SUN4I_TCON0_LVDS_IF_EN, 179 SUN4I_TCON0_LVDS_IF_EN); 180 if (tcon->quirks->setup_lvds_phy) 181 tcon->quirks->setup_lvds_phy(tcon, encoder); 182 } else { 183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 184 SUN4I_TCON0_LVDS_IF_EN, 0); 185 } 186 } 187 188 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, 189 const struct drm_encoder *encoder, 190 bool enabled) 191 { 192 bool is_lvds = false; 193 int channel; 194 195 switch (encoder->encoder_type) { 196 case DRM_MODE_ENCODER_LVDS: 197 is_lvds = true; 198 /* Fallthrough */ 199 case DRM_MODE_ENCODER_DSI: 200 case DRM_MODE_ENCODER_NONE: 201 channel = 0; 202 break; 203 case DRM_MODE_ENCODER_TMDS: 204 case DRM_MODE_ENCODER_TVDAC: 205 channel = 1; 206 break; 207 default: 208 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 209 return; 210 } 211 212 if (is_lvds && !enabled) 213 sun4i_tcon_lvds_set_status(tcon, encoder, false); 214 215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 216 SUN4I_TCON_GCTL_TCON_ENABLE, 217 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0); 218 219 if (is_lvds && enabled) 220 sun4i_tcon_lvds_set_status(tcon, encoder, true); 221 222 sun4i_tcon_channel_set_status(tcon, channel, enabled); 223 } 224 225 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) 226 { 227 u32 mask, val = 0; 228 229 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis"); 230 231 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) | 232 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) | 233 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE; 234 235 if (enable) 236 val = mask; 237 238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); 239 } 240 EXPORT_SYMBOL(sun4i_tcon_enable_vblank); 241 242 /* 243 * This function is a helper for TCON output muxing. The TCON output 244 * muxing control register in earlier SoCs (without the TCON TOP block) 245 * are located in TCON0. This helper returns a pointer to TCON0's 246 * sun4i_tcon structure, or NULL if not found. 247 */ 248 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm) 249 { 250 struct sun4i_drv *drv = drm->dev_private; 251 struct sun4i_tcon *tcon; 252 253 list_for_each_entry(tcon, &drv->tcon_list, list) 254 if (tcon->id == 0) 255 return tcon; 256 257 dev_warn(drm->dev, 258 "TCON0 not found, display output muxing may not work\n"); 259 260 return NULL; 261 } 262 263 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, 264 const struct drm_encoder *encoder) 265 { 266 int ret = -ENOTSUPP; 267 268 if (tcon->quirks->set_mux) 269 ret = tcon->quirks->set_mux(tcon, encoder); 270 271 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n", 272 encoder->name, encoder->crtc->name, ret); 273 } 274 275 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, 276 int channel) 277 { 278 int delay = mode->vtotal - mode->vdisplay; 279 280 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 281 delay /= 2; 282 283 if (channel == 1) 284 delay -= 2; 285 286 delay = min(delay, 30); 287 288 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); 289 290 return delay; 291 } 292 293 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, 294 const struct drm_display_mode *mode) 295 { 296 /* Configure the dot clock */ 297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); 298 299 /* Set the resolution */ 300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, 301 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | 302 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); 303 } 304 305 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, 306 const struct drm_connector *connector) 307 { 308 u32 bus_format = 0; 309 u32 val = 0; 310 311 /* XXX Would this ever happen? */ 312 if (!connector) 313 return; 314 315 /* 316 * FIXME: Undocumented bits 317 * 318 * The whole dithering process and these parameters are not 319 * explained in the vendor documents or BSP kernel code. 320 */ 321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); 322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); 323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); 324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); 325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); 326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); 327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); 328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); 329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); 330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); 331 332 /* Do dithering if panel only supports 6 bits per color */ 333 if (connector->display_info.bpc == 6) 334 val |= SUN4I_TCON0_FRM_CTL_EN; 335 336 if (connector->display_info.num_bus_formats == 1) 337 bus_format = connector->display_info.bus_formats[0]; 338 339 /* Check the connection format */ 340 switch (bus_format) { 341 case MEDIA_BUS_FMT_RGB565_1X16: 342 /* R and B components are only 5 bits deep */ 343 val |= SUN4I_TCON0_FRM_CTL_MODE_R; 344 val |= SUN4I_TCON0_FRM_CTL_MODE_B; 345 /* Fall through */ 346 case MEDIA_BUS_FMT_RGB666_1X18: 347 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 348 /* Fall through: enable dithering */ 349 val |= SUN4I_TCON0_FRM_CTL_EN; 350 break; 351 } 352 353 /* Write dithering settings */ 354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); 355 } 356 357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, 358 const struct drm_encoder *encoder, 359 const struct drm_display_mode *mode) 360 { 361 /* TODO support normal CPU interface modes */ 362 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); 363 struct mipi_dsi_device *device = dsi->device; 364 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); 365 u8 lanes = device->lanes; 366 u32 block_space, start_delay; 367 u32 tcon_div; 368 369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; 370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; 371 372 sun4i_tcon0_mode_set_common(tcon, mode); 373 374 /* Set dithering if needed */ 375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 376 377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 378 SUN4I_TCON0_CTL_IF_MASK, 379 SUN4I_TCON0_CTL_IF_8080); 380 381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, 382 SUN4I_TCON_ECC_FIFO_EN); 383 384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, 385 SUN4I_TCON0_CPU_IF_MODE_DSI | 386 SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH | 387 SUN4I_TCON0_CPU_IF_TRI_FIFO_EN | 388 SUN4I_TCON0_CPU_IF_TRI_EN); 389 390 /* 391 * This looks suspicious, but it works... 392 * 393 * The datasheet says that this should be set higher than 20 * 394 * pixel cycle, but it's not clear what a pixel cycle is. 395 */ 396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); 397 tcon_div &= GENMASK(6, 0); 398 block_space = mode->htotal * bpp / (tcon_div * lanes); 399 block_space -= mode->hdisplay + 40; 400 401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, 402 SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) | 403 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); 404 405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, 406 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); 407 408 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); 409 start_delay = start_delay * mode->crtc_htotal * 149; 410 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; 411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, 412 SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) | 413 SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay)); 414 415 /* 416 * The Allwinner BSP has a comment that the period should be 417 * the display clock * 15, but uses an hardcoded 3000... 418 */ 419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, 420 SUN4I_TCON_SAFE_PERIOD_NUM(3000) | 421 SUN4I_TCON_SAFE_PERIOD_MODE(3)); 422 423 /* Enable the output on the pins */ 424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 425 0xe0000000); 426 } 427 428 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, 429 const struct drm_encoder *encoder, 430 const struct drm_display_mode *mode) 431 { 432 unsigned int bp; 433 u8 clk_delay; 434 u32 reg, val = 0; 435 436 WARN_ON(!tcon->quirks->has_channel_0); 437 438 tcon->dclk_min_div = 7; 439 tcon->dclk_max_div = 7; 440 sun4i_tcon0_mode_set_common(tcon, mode); 441 442 /* Set dithering if needed */ 443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 444 445 /* Adjust clock delay */ 446 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 448 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 449 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 450 451 /* 452 * This is called a backporch in the register documentation, 453 * but it really is the back porch + hsync 454 */ 455 bp = mode->crtc_htotal - mode->crtc_hsync_start; 456 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 457 mode->crtc_htotal, bp); 458 459 /* Set horizontal display timings */ 460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 461 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | 462 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 463 464 /* 465 * This is called a backporch in the register documentation, 466 * but it really is the back porch + hsync 467 */ 468 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 469 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 470 mode->crtc_vtotal, bp); 471 472 /* Set vertical display timings */ 473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 474 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 475 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 476 477 reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 | 478 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL | 479 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL; 480 if (sun4i_tcon_get_pixel_depth(encoder) == 24) 481 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS; 482 else 483 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS; 484 485 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); 486 487 /* Setup the polarity of the various signals */ 488 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) 489 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 490 491 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) 492 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 493 494 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); 495 496 /* Map output pins to channel 0 */ 497 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 498 SUN4I_TCON_GCTL_IOMAP_MASK, 499 SUN4I_TCON_GCTL_IOMAP_TCON0); 500 501 /* Enable the output on the pins */ 502 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); 503 } 504 505 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 506 const struct drm_encoder *encoder, 507 const struct drm_display_mode *mode) 508 { 509 struct drm_connector *connector = sun4i_tcon_get_connector(encoder); 510 const struct drm_display_info *info = &connector->display_info; 511 unsigned int bp, hsync, vsync; 512 u8 clk_delay; 513 u32 val = 0; 514 515 WARN_ON(!tcon->quirks->has_channel_0); 516 517 tcon->dclk_min_div = tcon->quirks->dclk_min_div; 518 tcon->dclk_max_div = 127; 519 sun4i_tcon0_mode_set_common(tcon, mode); 520 521 /* Set dithering if needed */ 522 sun4i_tcon0_mode_set_dithering(tcon, connector); 523 524 /* Adjust clock delay */ 525 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 526 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 527 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 528 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 529 530 /* 531 * This is called a backporch in the register documentation, 532 * but it really is the back porch + hsync 533 */ 534 bp = mode->crtc_htotal - mode->crtc_hsync_start; 535 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 536 mode->crtc_htotal, bp); 537 538 /* Set horizontal display timings */ 539 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 540 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | 541 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 542 543 /* 544 * This is called a backporch in the register documentation, 545 * but it really is the back porch + hsync 546 */ 547 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 548 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 549 mode->crtc_vtotal, bp); 550 551 /* Set vertical display timings */ 552 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 553 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 554 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 555 556 /* Set Hsync and Vsync length */ 557 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 558 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 559 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 560 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, 561 SUN4I_TCON0_BASIC3_V_SYNC(vsync) | 562 SUN4I_TCON0_BASIC3_H_SYNC(hsync)); 563 564 /* Setup the polarity of the various signals */ 565 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 566 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 567 568 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 569 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 570 571 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 572 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; 573 574 /* 575 * On A20 and similar SoCs, the only way to achieve Positive Edge 576 * (Rising Edge), is setting dclk clock phase to 2/3(240°). 577 * By default TCON works in Negative Edge(Falling Edge), 578 * this is why phase is set to 0 in that case. 579 * Unfortunately there's no way to logically invert dclk through 580 * IO_POL register. 581 * The only acceptable way to work, triple checked with scope, 582 * is using clock phase set to 0° for Negative Edge and set to 240° 583 * for Positive Edge. 584 * On A33 and similar SoCs there would be a 90° phase option, 585 * but it divides also dclk by 2. 586 * Following code is a way to avoid quirks all around TCON 587 * and DOTCLOCK drivers. 588 */ 589 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 590 clk_set_phase(tcon->dclk, 240); 591 592 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 593 clk_set_phase(tcon->dclk, 0); 594 595 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, 596 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | 597 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE | 598 SUN4I_TCON0_IO_POL_DE_NEGATIVE, 599 val); 600 601 /* Map output pins to channel 0 */ 602 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 603 SUN4I_TCON_GCTL_IOMAP_MASK, 604 SUN4I_TCON_GCTL_IOMAP_TCON0); 605 606 /* Enable the output on the pins */ 607 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); 608 } 609 610 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 611 const struct drm_display_mode *mode) 612 { 613 unsigned int bp, hsync, vsync, vtotal; 614 u8 clk_delay; 615 u32 val; 616 617 WARN_ON(!tcon->quirks->has_channel_1); 618 619 /* Configure the dot clock */ 620 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); 621 622 /* Adjust clock delay */ 623 clk_delay = sun4i_tcon_get_clk_delay(mode, 1); 624 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 625 SUN4I_TCON1_CTL_CLK_DELAY_MASK, 626 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay)); 627 628 /* Set interlaced mode */ 629 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 630 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE; 631 else 632 val = 0; 633 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 634 SUN4I_TCON1_CTL_INTERLACE_ENABLE, 635 val); 636 637 /* Set the input resolution */ 638 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, 639 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | 640 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); 641 642 /* Set the upscaling resolution */ 643 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, 644 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | 645 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); 646 647 /* Set the output resolution */ 648 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, 649 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | 650 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); 651 652 /* Set horizontal display timings */ 653 bp = mode->crtc_htotal - mode->crtc_hsync_start; 654 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 655 mode->htotal, bp); 656 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, 657 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | 658 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)); 659 660 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 661 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 662 mode->crtc_vtotal, bp); 663 664 /* 665 * The vertical resolution needs to be doubled in all 666 * cases. We could use crtc_vtotal and always multiply by two, 667 * but that leads to a rounding error in interlace when vtotal 668 * is odd. 669 * 670 * This happens with TV's PAL for example, where vtotal will 671 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be 672 * 624, which apparently confuses the hardware. 673 * 674 * To work around this, we will always use vtotal, and 675 * multiply by two only if we're not in interlace. 676 */ 677 vtotal = mode->vtotal; 678 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) 679 vtotal = vtotal * 2; 680 681 /* Set vertical display timings */ 682 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, 683 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) | 684 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)); 685 686 /* Set Hsync and Vsync length */ 687 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 688 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 689 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 690 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, 691 SUN4I_TCON1_BASIC5_V_SYNC(vsync) | 692 SUN4I_TCON1_BASIC5_H_SYNC(hsync)); 693 694 /* Map output pins to channel 1 */ 695 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 696 SUN4I_TCON_GCTL_IOMAP_MASK, 697 SUN4I_TCON_GCTL_IOMAP_TCON1); 698 } 699 700 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, 701 const struct drm_encoder *encoder, 702 const struct drm_display_mode *mode) 703 { 704 switch (encoder->encoder_type) { 705 case DRM_MODE_ENCODER_DSI: 706 /* DSI is tied to special case of CPU interface */ 707 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); 708 break; 709 case DRM_MODE_ENCODER_LVDS: 710 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); 711 break; 712 case DRM_MODE_ENCODER_NONE: 713 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); 714 sun4i_tcon_set_mux(tcon, 0, encoder); 715 break; 716 case DRM_MODE_ENCODER_TVDAC: 717 case DRM_MODE_ENCODER_TMDS: 718 sun4i_tcon1_mode_set(tcon, mode); 719 sun4i_tcon_set_mux(tcon, 1, encoder); 720 break; 721 default: 722 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 723 } 724 } 725 EXPORT_SYMBOL(sun4i_tcon_mode_set); 726 727 static void sun4i_tcon_finish_page_flip(struct drm_device *dev, 728 struct sun4i_crtc *scrtc) 729 { 730 unsigned long flags; 731 732 spin_lock_irqsave(&dev->event_lock, flags); 733 if (scrtc->event) { 734 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); 735 drm_crtc_vblank_put(&scrtc->crtc); 736 scrtc->event = NULL; 737 } 738 spin_unlock_irqrestore(&dev->event_lock, flags); 739 } 740 741 static irqreturn_t sun4i_tcon_handler(int irq, void *private) 742 { 743 struct sun4i_tcon *tcon = private; 744 struct drm_device *drm = tcon->drm; 745 struct sun4i_crtc *scrtc = tcon->crtc; 746 struct sunxi_engine *engine = scrtc->engine; 747 unsigned int status; 748 749 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); 750 751 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) | 752 SUN4I_TCON_GINT0_VBLANK_INT(1) | 753 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT))) 754 return IRQ_NONE; 755 756 drm_crtc_handle_vblank(&scrtc->crtc); 757 sun4i_tcon_finish_page_flip(drm, scrtc); 758 759 /* Acknowledge the interrupt */ 760 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, 761 SUN4I_TCON_GINT0_VBLANK_INT(0) | 762 SUN4I_TCON_GINT0_VBLANK_INT(1) | 763 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT, 764 0); 765 766 if (engine->ops->vblank_quirk) 767 engine->ops->vblank_quirk(engine); 768 769 return IRQ_HANDLED; 770 } 771 772 static int sun4i_tcon_init_clocks(struct device *dev, 773 struct sun4i_tcon *tcon) 774 { 775 tcon->clk = devm_clk_get(dev, "ahb"); 776 if (IS_ERR(tcon->clk)) { 777 dev_err(dev, "Couldn't get the TCON bus clock\n"); 778 return PTR_ERR(tcon->clk); 779 } 780 clk_prepare_enable(tcon->clk); 781 782 if (tcon->quirks->has_channel_0) { 783 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); 784 if (IS_ERR(tcon->sclk0)) { 785 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); 786 return PTR_ERR(tcon->sclk0); 787 } 788 } 789 clk_prepare_enable(tcon->sclk0); 790 791 if (tcon->quirks->has_channel_1) { 792 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); 793 if (IS_ERR(tcon->sclk1)) { 794 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); 795 return PTR_ERR(tcon->sclk1); 796 } 797 } 798 799 return 0; 800 } 801 802 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) 803 { 804 clk_disable_unprepare(tcon->sclk0); 805 clk_disable_unprepare(tcon->clk); 806 } 807 808 static int sun4i_tcon_init_irq(struct device *dev, 809 struct sun4i_tcon *tcon) 810 { 811 struct platform_device *pdev = to_platform_device(dev); 812 int irq, ret; 813 814 irq = platform_get_irq(pdev, 0); 815 if (irq < 0) 816 return irq; 817 818 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0, 819 dev_name(dev), tcon); 820 if (ret) { 821 dev_err(dev, "Couldn't request the IRQ\n"); 822 return ret; 823 } 824 825 return 0; 826 } 827 828 static struct regmap_config sun4i_tcon_regmap_config = { 829 .reg_bits = 32, 830 .val_bits = 32, 831 .reg_stride = 4, 832 .max_register = 0x800, 833 }; 834 835 static int sun4i_tcon_init_regmap(struct device *dev, 836 struct sun4i_tcon *tcon) 837 { 838 struct platform_device *pdev = to_platform_device(dev); 839 struct resource *res; 840 void __iomem *regs; 841 842 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 843 regs = devm_ioremap_resource(dev, res); 844 if (IS_ERR(regs)) 845 return PTR_ERR(regs); 846 847 tcon->regs = devm_regmap_init_mmio(dev, regs, 848 &sun4i_tcon_regmap_config); 849 if (IS_ERR(tcon->regs)) { 850 dev_err(dev, "Couldn't create the TCON regmap\n"); 851 return PTR_ERR(tcon->regs); 852 } 853 854 /* Make sure the TCON is disabled and all IRQs are off */ 855 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); 856 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); 857 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); 858 859 /* Disable IO lines and set them to tristate */ 860 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); 861 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); 862 863 return 0; 864 } 865 866 /* 867 * On SoCs with the old display pipeline design (Display Engine 1.0), 868 * the TCON is always tied to just one backend. Hence we can traverse 869 * the of_graph upwards to find the backend our tcon is connected to, 870 * and take its ID as our own. 871 * 872 * We can either identify backends from their compatible strings, which 873 * means maintaining a large list of them. Or, since the backend is 874 * registered and binded before the TCON, we can just go through the 875 * list of registered backends and compare the device node. 876 * 877 * As the structures now store engines instead of backends, here this 878 * function in fact searches the corresponding engine, and the ID is 879 * requested via the get_id function of the engine. 880 */ 881 static struct sunxi_engine * 882 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv, 883 struct device_node *node, 884 u32 port_id) 885 { 886 struct device_node *port, *ep, *remote; 887 struct sunxi_engine *engine = ERR_PTR(-EINVAL); 888 u32 reg = 0; 889 890 port = of_graph_get_port_by_id(node, port_id); 891 if (!port) 892 return ERR_PTR(-EINVAL); 893 894 /* 895 * This only works if there is only one path from the TCON 896 * to any display engine. Otherwise the probe order of the 897 * TCONs and display engines is not guaranteed. They may 898 * either bind to the wrong one, or worse, bind to the same 899 * one if additional checks are not done. 900 * 901 * Bail out if there are multiple input connections. 902 */ 903 if (of_get_available_child_count(port) != 1) 904 goto out_put_port; 905 906 /* Get the first connection without specifying an ID */ 907 ep = of_get_next_available_child(port, NULL); 908 if (!ep) 909 goto out_put_port; 910 911 remote = of_graph_get_remote_port_parent(ep); 912 if (!remote) 913 goto out_put_ep; 914 915 /* does this node match any registered engines? */ 916 list_for_each_entry(engine, &drv->engine_list, list) 917 if (remote == engine->node) 918 goto out_put_remote; 919 920 /* 921 * According to device tree binding input ports have even id 922 * number and output ports have odd id. Since component with 923 * more than one input and one output (TCON TOP) exits, correct 924 * remote input id has to be calculated by subtracting 1 from 925 * remote output id. If this for some reason can't be done, 0 926 * is used as input port id. 927 */ 928 of_node_put(port); 929 port = of_graph_get_remote_port(ep); 930 if (!of_property_read_u32(port, "reg", ®) && reg > 0) 931 reg -= 1; 932 933 /* keep looking through upstream ports */ 934 engine = sun4i_tcon_find_engine_traverse(drv, remote, reg); 935 936 out_put_remote: 937 of_node_put(remote); 938 out_put_ep: 939 of_node_put(ep); 940 out_put_port: 941 of_node_put(port); 942 943 return engine; 944 } 945 946 /* 947 * The device tree binding says that the remote endpoint ID of any 948 * connection between components, up to and including the TCON, of 949 * the display pipeline should be equal to the actual ID of the local 950 * component. Thus we can look at any one of the input connections of 951 * the TCONs, and use that connection's remote endpoint ID as our own. 952 * 953 * Since the user of this function already finds the input port, 954 * the port is passed in directly without further checks. 955 */ 956 static int sun4i_tcon_of_get_id_from_port(struct device_node *port) 957 { 958 struct device_node *ep; 959 int ret = -EINVAL; 960 961 /* try finding an upstream endpoint */ 962 for_each_available_child_of_node(port, ep) { 963 struct device_node *remote; 964 u32 reg; 965 966 remote = of_graph_get_remote_endpoint(ep); 967 if (!remote) 968 continue; 969 970 ret = of_property_read_u32(remote, "reg", ®); 971 if (ret) 972 continue; 973 974 ret = reg; 975 } 976 977 return ret; 978 } 979 980 /* 981 * Once we know the TCON's id, we can look through the list of 982 * engines to find a matching one. We assume all engines have 983 * been probed and added to the list. 984 */ 985 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv, 986 int id) 987 { 988 struct sunxi_engine *engine; 989 990 list_for_each_entry(engine, &drv->engine_list, list) 991 if (engine->id == id) 992 return engine; 993 994 return ERR_PTR(-EINVAL); 995 } 996 997 static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node) 998 { 999 struct device_node *remote; 1000 bool ret = false; 1001 1002 remote = of_graph_get_remote_node(node, 0, -1); 1003 if (remote) { 1004 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1005 of_match_node(sun8i_tcon_top_of_table, remote)); 1006 of_node_put(remote); 1007 } 1008 1009 return ret; 1010 } 1011 1012 static int sun4i_tcon_get_index(struct sun4i_drv *drv) 1013 { 1014 struct list_head *pos; 1015 int size = 0; 1016 1017 /* 1018 * Because TCON is added to the list at the end of the probe 1019 * (after this function is called), index of the current TCON 1020 * will be same as current TCON list size. 1021 */ 1022 list_for_each(pos, &drv->tcon_list) 1023 ++size; 1024 1025 return size; 1026 } 1027 1028 /* 1029 * On SoCs with the old display pipeline design (Display Engine 1.0), 1030 * we assumed the TCON was always tied to just one backend. However 1031 * this proved not to be the case. On the A31, the TCON can select 1032 * either backend as its source. On the A20 (and likely on the A10), 1033 * the backend can choose which TCON to output to. 1034 * 1035 * The device tree binding says that the remote endpoint ID of any 1036 * connection between components, up to and including the TCON, of 1037 * the display pipeline should be equal to the actual ID of the local 1038 * component. Thus we should be able to look at any one of the input 1039 * connections of the TCONs, and use that connection's remote endpoint 1040 * ID as our own. 1041 * 1042 * However the connections between the backend and TCON were assumed 1043 * to be always singular, and their endpoit IDs were all incorrectly 1044 * set to 0. This means for these old device trees, we cannot just look 1045 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be 1046 * incorrectly identified as TCON0. 1047 * 1048 * This function first checks if the TCON node has 2 input endpoints. 1049 * If so, then the device tree is a corrected version, and it will use 1050 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above 1051 * to fetch the ID and engine directly. If not, then it is likely an 1052 * old device trees, where the endpoint IDs were incorrect, but did not 1053 * have endpoint connections between the backend and TCON across 1054 * different display pipelines. It will fall back to the old method of 1055 * traversing the of_graph to try and find a matching engine by device 1056 * node. 1057 * 1058 * In the case of single display pipeline device trees, either method 1059 * works. 1060 */ 1061 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv, 1062 struct device_node *node) 1063 { 1064 struct device_node *port; 1065 struct sunxi_engine *engine; 1066 1067 port = of_graph_get_port_by_id(node, 0); 1068 if (!port) 1069 return ERR_PTR(-EINVAL); 1070 1071 /* 1072 * Is this a corrected device tree with cross pipeline 1073 * connections between the backend and TCON? 1074 */ 1075 if (of_get_child_count(port) > 1) { 1076 int id; 1077 1078 /* 1079 * When pipeline has the same number of TCONs and engines which 1080 * are represented by frontends/backends (DE1) or mixers (DE2), 1081 * we match them by their respective IDs. However, if pipeline 1082 * contains TCON TOP, chances are that there are either more 1083 * TCONs than engines (R40) or TCONs with non-consecutive ids. 1084 * (H6). In that case it's easier just use TCON index in list 1085 * as an id. That means that on R40, any 2 TCONs can be enabled 1086 * in DT out of 4 (there are 2 mixers). Due to the design of 1087 * TCON TOP, remaining 2 TCONs can't be connected to anything 1088 * anyway. 1089 */ 1090 if (sun4i_tcon_connected_to_tcon_top(node)) 1091 id = sun4i_tcon_get_index(drv); 1092 else 1093 id = sun4i_tcon_of_get_id_from_port(port); 1094 1095 /* Get our engine by matching our ID */ 1096 engine = sun4i_tcon_get_engine_by_id(drv, id); 1097 1098 of_node_put(port); 1099 return engine; 1100 } 1101 1102 /* Fallback to old method by traversing input endpoints */ 1103 of_node_put(port); 1104 return sun4i_tcon_find_engine_traverse(drv, node, 0); 1105 } 1106 1107 static int sun4i_tcon_bind(struct device *dev, struct device *master, 1108 void *data) 1109 { 1110 struct drm_device *drm = data; 1111 struct sun4i_drv *drv = drm->dev_private; 1112 struct sunxi_engine *engine; 1113 struct device_node *remote; 1114 struct sun4i_tcon *tcon; 1115 struct reset_control *edp_rstc; 1116 bool has_lvds_rst, has_lvds_alt, can_lvds; 1117 int ret; 1118 1119 engine = sun4i_tcon_find_engine(drv, dev->of_node); 1120 if (IS_ERR(engine)) { 1121 dev_err(dev, "Couldn't find matching engine\n"); 1122 return -EPROBE_DEFER; 1123 } 1124 1125 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); 1126 if (!tcon) 1127 return -ENOMEM; 1128 dev_set_drvdata(dev, tcon); 1129 tcon->drm = drm; 1130 tcon->dev = dev; 1131 tcon->id = engine->id; 1132 tcon->quirks = of_device_get_match_data(dev); 1133 1134 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); 1135 if (IS_ERR(tcon->lcd_rst)) { 1136 dev_err(dev, "Couldn't get our reset line\n"); 1137 return PTR_ERR(tcon->lcd_rst); 1138 } 1139 1140 if (tcon->quirks->needs_edp_reset) { 1141 edp_rstc = devm_reset_control_get_shared(dev, "edp"); 1142 if (IS_ERR(edp_rstc)) { 1143 dev_err(dev, "Couldn't get edp reset line\n"); 1144 return PTR_ERR(edp_rstc); 1145 } 1146 1147 ret = reset_control_deassert(edp_rstc); 1148 if (ret) { 1149 dev_err(dev, "Couldn't deassert edp reset line\n"); 1150 return ret; 1151 } 1152 } 1153 1154 /* Make sure our TCON is reset */ 1155 ret = reset_control_reset(tcon->lcd_rst); 1156 if (ret) { 1157 dev_err(dev, "Couldn't deassert our reset line\n"); 1158 return ret; 1159 } 1160 1161 if (tcon->quirks->supports_lvds) { 1162 /* 1163 * This can only be made optional since we've had DT 1164 * nodes without the LVDS reset properties. 1165 * 1166 * If the property is missing, just disable LVDS, and 1167 * print a warning. 1168 */ 1169 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); 1170 if (IS_ERR(tcon->lvds_rst)) { 1171 dev_err(dev, "Couldn't get our reset line\n"); 1172 return PTR_ERR(tcon->lvds_rst); 1173 } else if (tcon->lvds_rst) { 1174 has_lvds_rst = true; 1175 reset_control_reset(tcon->lvds_rst); 1176 } else { 1177 has_lvds_rst = false; 1178 } 1179 1180 /* 1181 * This can only be made optional since we've had DT 1182 * nodes without the LVDS reset properties. 1183 * 1184 * If the property is missing, just disable LVDS, and 1185 * print a warning. 1186 */ 1187 if (tcon->quirks->has_lvds_alt) { 1188 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); 1189 if (IS_ERR(tcon->lvds_pll)) { 1190 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { 1191 has_lvds_alt = false; 1192 } else { 1193 dev_err(dev, "Couldn't get the LVDS PLL\n"); 1194 return PTR_ERR(tcon->lvds_pll); 1195 } 1196 } else { 1197 has_lvds_alt = true; 1198 } 1199 } 1200 1201 if (!has_lvds_rst || 1202 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { 1203 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n"); 1204 dev_warn(dev, "LVDS output disabled\n"); 1205 can_lvds = false; 1206 } else { 1207 can_lvds = true; 1208 } 1209 } else { 1210 can_lvds = false; 1211 } 1212 1213 ret = sun4i_tcon_init_clocks(dev, tcon); 1214 if (ret) { 1215 dev_err(dev, "Couldn't init our TCON clocks\n"); 1216 goto err_assert_reset; 1217 } 1218 1219 ret = sun4i_tcon_init_regmap(dev, tcon); 1220 if (ret) { 1221 dev_err(dev, "Couldn't init our TCON regmap\n"); 1222 goto err_free_clocks; 1223 } 1224 1225 if (tcon->quirks->has_channel_0) { 1226 ret = sun4i_dclk_create(dev, tcon); 1227 if (ret) { 1228 dev_err(dev, "Couldn't create our TCON dot clock\n"); 1229 goto err_free_clocks; 1230 } 1231 } 1232 1233 ret = sun4i_tcon_init_irq(dev, tcon); 1234 if (ret) { 1235 dev_err(dev, "Couldn't init our TCON interrupts\n"); 1236 goto err_free_dotclock; 1237 } 1238 1239 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); 1240 if (IS_ERR(tcon->crtc)) { 1241 dev_err(dev, "Couldn't create our CRTC\n"); 1242 ret = PTR_ERR(tcon->crtc); 1243 goto err_free_dotclock; 1244 } 1245 1246 if (tcon->quirks->has_channel_0) { 1247 /* 1248 * If we have an LVDS panel connected to the TCON, we should 1249 * just probe the LVDS connector. Otherwise, just probe RGB as 1250 * we used to. 1251 */ 1252 remote = of_graph_get_remote_node(dev->of_node, 1, 0); 1253 if (of_device_is_compatible(remote, "panel-lvds")) 1254 if (can_lvds) 1255 ret = sun4i_lvds_init(drm, tcon); 1256 else 1257 ret = -EINVAL; 1258 else 1259 ret = sun4i_rgb_init(drm, tcon); 1260 of_node_put(remote); 1261 1262 if (ret < 0) 1263 goto err_free_dotclock; 1264 } 1265 1266 if (tcon->quirks->needs_de_be_mux) { 1267 /* 1268 * We assume there is no dynamic muxing of backends 1269 * and TCONs, so we select the backend with same ID. 1270 * 1271 * While dynamic selection might be interesting, since 1272 * the CRTC is tied to the TCON, while the layers are 1273 * tied to the backends, this means, we will need to 1274 * switch between groups of layers. There might not be 1275 * a way to represent this constraint in DRM. 1276 */ 1277 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 1278 SUN4I_TCON0_CTL_SRC_SEL_MASK, 1279 tcon->id); 1280 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 1281 SUN4I_TCON1_CTL_SRC_SEL_MASK, 1282 tcon->id); 1283 } 1284 1285 list_add_tail(&tcon->list, &drv->tcon_list); 1286 1287 return 0; 1288 1289 err_free_dotclock: 1290 if (tcon->quirks->has_channel_0) 1291 sun4i_dclk_free(tcon); 1292 err_free_clocks: 1293 sun4i_tcon_free_clocks(tcon); 1294 err_assert_reset: 1295 reset_control_assert(tcon->lcd_rst); 1296 return ret; 1297 } 1298 1299 static void sun4i_tcon_unbind(struct device *dev, struct device *master, 1300 void *data) 1301 { 1302 struct sun4i_tcon *tcon = dev_get_drvdata(dev); 1303 1304 list_del(&tcon->list); 1305 if (tcon->quirks->has_channel_0) 1306 sun4i_dclk_free(tcon); 1307 sun4i_tcon_free_clocks(tcon); 1308 } 1309 1310 static const struct component_ops sun4i_tcon_ops = { 1311 .bind = sun4i_tcon_bind, 1312 .unbind = sun4i_tcon_unbind, 1313 }; 1314 1315 static int sun4i_tcon_probe(struct platform_device *pdev) 1316 { 1317 struct device_node *node = pdev->dev.of_node; 1318 const struct sun4i_tcon_quirks *quirks; 1319 struct drm_bridge *bridge; 1320 struct drm_panel *panel; 1321 int ret; 1322 1323 quirks = of_device_get_match_data(&pdev->dev); 1324 1325 /* panels and bridges are present only on TCONs with channel 0 */ 1326 if (quirks->has_channel_0) { 1327 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); 1328 if (ret == -EPROBE_DEFER) 1329 return ret; 1330 } 1331 1332 return component_add(&pdev->dev, &sun4i_tcon_ops); 1333 } 1334 1335 static int sun4i_tcon_remove(struct platform_device *pdev) 1336 { 1337 component_del(&pdev->dev, &sun4i_tcon_ops); 1338 1339 return 0; 1340 } 1341 1342 /* platform specific TCON muxing callbacks */ 1343 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, 1344 const struct drm_encoder *encoder) 1345 { 1346 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1347 u32 shift; 1348 1349 if (!tcon0) 1350 return -EINVAL; 1351 1352 switch (encoder->encoder_type) { 1353 case DRM_MODE_ENCODER_TMDS: 1354 /* HDMI */ 1355 shift = 8; 1356 break; 1357 default: 1358 return -EINVAL; 1359 } 1360 1361 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1362 0x3 << shift, tcon->id << shift); 1363 1364 return 0; 1365 } 1366 1367 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, 1368 const struct drm_encoder *encoder) 1369 { 1370 u32 val; 1371 1372 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1373 val = 1; 1374 else 1375 val = 0; 1376 1377 /* 1378 * FIXME: Undocumented bits 1379 */ 1380 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); 1381 } 1382 1383 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, 1384 const struct drm_encoder *encoder) 1385 { 1386 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1387 u32 shift; 1388 1389 if (!tcon0) 1390 return -EINVAL; 1391 1392 switch (encoder->encoder_type) { 1393 case DRM_MODE_ENCODER_TMDS: 1394 /* HDMI */ 1395 shift = 8; 1396 break; 1397 default: 1398 /* TODO A31 has MIPI DSI but A31s does not */ 1399 return -EINVAL; 1400 } 1401 1402 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1403 0x3 << shift, tcon->id << shift); 1404 1405 return 0; 1406 } 1407 1408 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, 1409 const struct drm_encoder *encoder) 1410 { 1411 struct device_node *port, *remote; 1412 struct platform_device *pdev; 1413 int id, ret; 1414 1415 /* find TCON TOP platform device and TCON id */ 1416 1417 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); 1418 if (!port) 1419 return -EINVAL; 1420 1421 id = sun4i_tcon_of_get_id_from_port(port); 1422 of_node_put(port); 1423 1424 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); 1425 if (!remote) 1426 return -EINVAL; 1427 1428 pdev = of_find_device_by_node(remote); 1429 of_node_put(remote); 1430 if (!pdev) 1431 return -EINVAL; 1432 1433 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1434 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { 1435 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); 1436 if (ret) 1437 return ret; 1438 } 1439 1440 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) { 1441 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); 1442 if (ret) 1443 return ret; 1444 } 1445 1446 return 0; 1447 } 1448 1449 static const struct sun4i_tcon_quirks sun4i_a10_quirks = { 1450 .has_channel_0 = true, 1451 .has_channel_1 = true, 1452 .dclk_min_div = 4, 1453 .set_mux = sun4i_a10_tcon_set_mux, 1454 }; 1455 1456 static const struct sun4i_tcon_quirks sun5i_a13_quirks = { 1457 .has_channel_0 = true, 1458 .has_channel_1 = true, 1459 .dclk_min_div = 4, 1460 .set_mux = sun5i_a13_tcon_set_mux, 1461 }; 1462 1463 static const struct sun4i_tcon_quirks sun6i_a31_quirks = { 1464 .has_channel_0 = true, 1465 .has_channel_1 = true, 1466 .has_lvds_alt = true, 1467 .needs_de_be_mux = true, 1468 .dclk_min_div = 1, 1469 .set_mux = sun6i_tcon_set_mux, 1470 }; 1471 1472 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = { 1473 .has_channel_0 = true, 1474 .has_channel_1 = true, 1475 .needs_de_be_mux = true, 1476 .dclk_min_div = 1, 1477 }; 1478 1479 static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = { 1480 .supports_lvds = true, 1481 .has_channel_0 = true, 1482 .has_channel_1 = true, 1483 .dclk_min_div = 4, 1484 /* Same display pipeline structure as A10 */ 1485 .set_mux = sun4i_a10_tcon_set_mux, 1486 .setup_lvds_phy = sun4i_tcon_setup_lvds_phy, 1487 }; 1488 1489 static const struct sun4i_tcon_quirks sun7i_a20_quirks = { 1490 .has_channel_0 = true, 1491 .has_channel_1 = true, 1492 .dclk_min_div = 4, 1493 /* Same display pipeline structure as A10 */ 1494 .set_mux = sun4i_a10_tcon_set_mux, 1495 }; 1496 1497 static const struct sun4i_tcon_quirks sun8i_a33_quirks = { 1498 .has_channel_0 = true, 1499 .has_lvds_alt = true, 1500 .dclk_min_div = 1, 1501 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1502 .supports_lvds = true, 1503 }; 1504 1505 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { 1506 .supports_lvds = true, 1507 .has_channel_0 = true, 1508 .dclk_min_div = 1, 1509 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1510 }; 1511 1512 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { 1513 .has_channel_1 = true, 1514 }; 1515 1516 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { 1517 .has_channel_1 = true, 1518 .set_mux = sun8i_r40_tcon_tv_set_mux, 1519 }; 1520 1521 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = { 1522 .has_channel_0 = true, 1523 .dclk_min_div = 1, 1524 }; 1525 1526 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = { 1527 .has_channel_0 = true, 1528 .needs_edp_reset = true, 1529 .dclk_min_div = 1, 1530 }; 1531 1532 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = { 1533 .has_channel_1 = true, 1534 .needs_edp_reset = true, 1535 }; 1536 1537 /* sun4i_drv uses this list to check if a device node is a TCON */ 1538 const struct of_device_id sun4i_tcon_of_table[] = { 1539 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks }, 1540 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks }, 1541 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks }, 1542 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks }, 1543 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks }, 1544 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks }, 1545 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks }, 1546 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks }, 1547 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks }, 1548 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks }, 1549 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks }, 1550 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks }, 1551 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks }, 1552 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks }, 1553 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks }, 1554 { } 1555 }; 1556 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table); 1557 EXPORT_SYMBOL(sun4i_tcon_of_table); 1558 1559 static struct platform_driver sun4i_tcon_platform_driver = { 1560 .probe = sun4i_tcon_probe, 1561 .remove = sun4i_tcon_remove, 1562 .driver = { 1563 .name = "sun4i-tcon", 1564 .of_match_table = sun4i_tcon_of_table, 1565 }, 1566 }; 1567 module_platform_driver(sun4i_tcon_platform_driver); 1568 1569 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1570 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver"); 1571 MODULE_LICENSE("GPL"); 1572