1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2015 Free Electrons 4 * Copyright (C) 2015 NextThing Co 5 * 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 */ 8 9 #include <linux/component.h> 10 #include <linux/ioport.h> 11 #include <linux/module.h> 12 #include <linux/of_address.h> 13 #include <linux/of_device.h> 14 #include <linux/of_irq.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_bridge.h> 20 #include <drm/drm_connector.h> 21 #include <drm/drm_crtc.h> 22 #include <drm/drm_encoder.h> 23 #include <drm/drm_modes.h> 24 #include <drm/drm_of.h> 25 #include <drm/drm_panel.h> 26 #include <drm/drm_print.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include <uapi/drm/drm_mode.h> 31 32 #include "sun4i_crtc.h" 33 #include "sun4i_dotclock.h" 34 #include "sun4i_drv.h" 35 #include "sun4i_lvds.h" 36 #include "sun4i_rgb.h" 37 #include "sun4i_tcon.h" 38 #include "sun6i_mipi_dsi.h" 39 #include "sun8i_tcon_top.h" 40 #include "sunxi_engine.h" 41 42 static struct drm_connector *sun4i_tcon_get_connector(const struct drm_encoder *encoder) 43 { 44 struct drm_connector *connector; 45 struct drm_connector_list_iter iter; 46 47 drm_connector_list_iter_begin(encoder->dev, &iter); 48 drm_for_each_connector_iter(connector, &iter) 49 if (connector->encoder == encoder) { 50 drm_connector_list_iter_end(&iter); 51 return connector; 52 } 53 drm_connector_list_iter_end(&iter); 54 55 return NULL; 56 } 57 58 static int sun4i_tcon_get_pixel_depth(const struct drm_encoder *encoder) 59 { 60 struct drm_connector *connector; 61 struct drm_display_info *info; 62 63 connector = sun4i_tcon_get_connector(encoder); 64 if (!connector) 65 return -EINVAL; 66 67 info = &connector->display_info; 68 if (info->num_bus_formats != 1) 69 return -EINVAL; 70 71 switch (info->bus_formats[0]) { 72 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 73 return 18; 74 75 case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA: 76 case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG: 77 return 24; 78 } 79 80 return -EINVAL; 81 } 82 83 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, 84 bool enabled) 85 { 86 struct clk *clk; 87 88 switch (channel) { 89 case 0: 90 WARN_ON(!tcon->quirks->has_channel_0); 91 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 92 SUN4I_TCON0_CTL_TCON_ENABLE, 93 enabled ? SUN4I_TCON0_CTL_TCON_ENABLE : 0); 94 clk = tcon->dclk; 95 break; 96 case 1: 97 WARN_ON(!tcon->quirks->has_channel_1); 98 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 99 SUN4I_TCON1_CTL_TCON_ENABLE, 100 enabled ? SUN4I_TCON1_CTL_TCON_ENABLE : 0); 101 clk = tcon->sclk1; 102 break; 103 default: 104 DRM_WARN("Unknown channel... doing nothing\n"); 105 return; 106 } 107 108 if (enabled) { 109 clk_prepare_enable(clk); 110 clk_rate_exclusive_get(clk); 111 } else { 112 clk_rate_exclusive_put(clk); 113 clk_disable_unprepare(clk); 114 } 115 } 116 117 static void sun4i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 118 const struct drm_encoder *encoder) 119 { 120 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 121 SUN4I_TCON0_LVDS_ANA0_CK_EN | 122 SUN4I_TCON0_LVDS_ANA0_REG_V | 123 SUN4I_TCON0_LVDS_ANA0_REG_C | 124 SUN4I_TCON0_LVDS_ANA0_EN_MB | 125 SUN4I_TCON0_LVDS_ANA0_PD | 126 SUN4I_TCON0_LVDS_ANA0_DCHS); 127 128 udelay(2); /* delay at least 1200 ns */ 129 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, 130 SUN4I_TCON0_LVDS_ANA1_INIT, 131 SUN4I_TCON0_LVDS_ANA1_INIT); 132 udelay(1); /* delay at least 120 ns */ 133 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA1_REG, 134 SUN4I_TCON0_LVDS_ANA1_UPDATE, 135 SUN4I_TCON0_LVDS_ANA1_UPDATE); 136 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 137 SUN4I_TCON0_LVDS_ANA0_EN_MB, 138 SUN4I_TCON0_LVDS_ANA0_EN_MB); 139 } 140 141 static void sun6i_tcon_setup_lvds_phy(struct sun4i_tcon *tcon, 142 const struct drm_encoder *encoder) 143 { 144 u8 val; 145 146 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 147 SUN6I_TCON0_LVDS_ANA0_C(2) | 148 SUN6I_TCON0_LVDS_ANA0_V(3) | 149 SUN6I_TCON0_LVDS_ANA0_PD(2) | 150 SUN6I_TCON0_LVDS_ANA0_EN_LDO); 151 udelay(2); 152 153 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 154 SUN6I_TCON0_LVDS_ANA0_EN_MB, 155 SUN6I_TCON0_LVDS_ANA0_EN_MB); 156 udelay(2); 157 158 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 159 SUN6I_TCON0_LVDS_ANA0_EN_DRVC, 160 SUN6I_TCON0_LVDS_ANA0_EN_DRVC); 161 162 if (sun4i_tcon_get_pixel_depth(encoder) == 18) 163 val = 7; 164 else 165 val = 0xf; 166 167 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, 168 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(0xf), 169 SUN6I_TCON0_LVDS_ANA0_EN_DRVD(val)); 170 } 171 172 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, 173 const struct drm_encoder *encoder, 174 bool enabled) 175 { 176 if (enabled) { 177 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 178 SUN4I_TCON0_LVDS_IF_EN, 179 SUN4I_TCON0_LVDS_IF_EN); 180 if (tcon->quirks->setup_lvds_phy) 181 tcon->quirks->setup_lvds_phy(tcon, encoder); 182 } else { 183 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, 184 SUN4I_TCON0_LVDS_IF_EN, 0); 185 } 186 } 187 188 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, 189 const struct drm_encoder *encoder, 190 bool enabled) 191 { 192 bool is_lvds = false; 193 int channel; 194 195 switch (encoder->encoder_type) { 196 case DRM_MODE_ENCODER_LVDS: 197 is_lvds = true; 198 /* Fallthrough */ 199 case DRM_MODE_ENCODER_DSI: 200 case DRM_MODE_ENCODER_NONE: 201 channel = 0; 202 break; 203 case DRM_MODE_ENCODER_TMDS: 204 case DRM_MODE_ENCODER_TVDAC: 205 channel = 1; 206 break; 207 default: 208 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 209 return; 210 } 211 212 if (is_lvds && !enabled) 213 sun4i_tcon_lvds_set_status(tcon, encoder, false); 214 215 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 216 SUN4I_TCON_GCTL_TCON_ENABLE, 217 enabled ? SUN4I_TCON_GCTL_TCON_ENABLE : 0); 218 219 if (is_lvds && enabled) 220 sun4i_tcon_lvds_set_status(tcon, encoder, true); 221 222 sun4i_tcon_channel_set_status(tcon, channel, enabled); 223 } 224 225 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) 226 { 227 u32 mask, val = 0; 228 229 DRM_DEBUG_DRIVER("%sabling VBLANK interrupt\n", enable ? "En" : "Dis"); 230 231 mask = SUN4I_TCON_GINT0_VBLANK_ENABLE(0) | 232 SUN4I_TCON_GINT0_VBLANK_ENABLE(1) | 233 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_ENABLE; 234 235 if (enable) 236 val = mask; 237 238 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); 239 } 240 EXPORT_SYMBOL(sun4i_tcon_enable_vblank); 241 242 /* 243 * This function is a helper for TCON output muxing. The TCON output 244 * muxing control register in earlier SoCs (without the TCON TOP block) 245 * are located in TCON0. This helper returns a pointer to TCON0's 246 * sun4i_tcon structure, or NULL if not found. 247 */ 248 static struct sun4i_tcon *sun4i_get_tcon0(struct drm_device *drm) 249 { 250 struct sun4i_drv *drv = drm->dev_private; 251 struct sun4i_tcon *tcon; 252 253 list_for_each_entry(tcon, &drv->tcon_list, list) 254 if (tcon->id == 0) 255 return tcon; 256 257 dev_warn(drm->dev, 258 "TCON0 not found, display output muxing may not work\n"); 259 260 return NULL; 261 } 262 263 static void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, 264 const struct drm_encoder *encoder) 265 { 266 int ret = -ENOTSUPP; 267 268 if (tcon->quirks->set_mux) 269 ret = tcon->quirks->set_mux(tcon, encoder); 270 271 DRM_DEBUG_DRIVER("Muxing encoder %s to CRTC %s: %d\n", 272 encoder->name, encoder->crtc->name, ret); 273 } 274 275 static int sun4i_tcon_get_clk_delay(const struct drm_display_mode *mode, 276 int channel) 277 { 278 int delay = mode->vtotal - mode->vdisplay; 279 280 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 281 delay /= 2; 282 283 if (channel == 1) 284 delay -= 2; 285 286 delay = min(delay, 30); 287 288 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); 289 290 return delay; 291 } 292 293 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, 294 const struct drm_display_mode *mode) 295 { 296 /* Configure the dot clock */ 297 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); 298 299 /* Set the resolution */ 300 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, 301 SUN4I_TCON0_BASIC0_X(mode->crtc_hdisplay) | 302 SUN4I_TCON0_BASIC0_Y(mode->crtc_vdisplay)); 303 } 304 305 static void sun4i_tcon0_mode_set_dithering(struct sun4i_tcon *tcon, 306 const struct drm_connector *connector) 307 { 308 u32 bus_format = 0; 309 u32 val = 0; 310 311 /* XXX Would this ever happen? */ 312 if (!connector) 313 return; 314 315 /* 316 * FIXME: Undocumented bits 317 * 318 * The whole dithering process and these parameters are not 319 * explained in the vendor documents or BSP kernel code. 320 */ 321 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PR_REG, 0x11111111); 322 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PG_REG, 0x11111111); 323 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_PB_REG, 0x11111111); 324 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LR_REG, 0x11111111); 325 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LG_REG, 0x11111111); 326 regmap_write(tcon->regs, SUN4I_TCON0_FRM_SEED_LB_REG, 0x11111111); 327 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL0_REG, 0x01010000); 328 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL1_REG, 0x15151111); 329 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL2_REG, 0x57575555); 330 regmap_write(tcon->regs, SUN4I_TCON0_FRM_TBL3_REG, 0x7f7f7777); 331 332 /* Do dithering if panel only supports 6 bits per color */ 333 if (connector->display_info.bpc == 6) 334 val |= SUN4I_TCON0_FRM_CTL_EN; 335 336 if (connector->display_info.num_bus_formats == 1) 337 bus_format = connector->display_info.bus_formats[0]; 338 339 /* Check the connection format */ 340 switch (bus_format) { 341 case MEDIA_BUS_FMT_RGB565_1X16: 342 /* R and B components are only 5 bits deep */ 343 val |= SUN4I_TCON0_FRM_CTL_MODE_R; 344 val |= SUN4I_TCON0_FRM_CTL_MODE_B; 345 /* Fall through */ 346 case MEDIA_BUS_FMT_RGB666_1X18: 347 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG: 348 /* Fall through: enable dithering */ 349 val |= SUN4I_TCON0_FRM_CTL_EN; 350 break; 351 } 352 353 /* Write dithering settings */ 354 regmap_write(tcon->regs, SUN4I_TCON_FRM_CTL_REG, val); 355 } 356 357 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, 358 const struct drm_encoder *encoder, 359 const struct drm_display_mode *mode) 360 { 361 /* TODO support normal CPU interface modes */ 362 struct sun6i_dsi *dsi = encoder_to_sun6i_dsi(encoder); 363 struct mipi_dsi_device *device = dsi->device; 364 u8 bpp = mipi_dsi_pixel_format_to_bpp(device->format); 365 u8 lanes = device->lanes; 366 u32 block_space, start_delay; 367 u32 tcon_div; 368 369 tcon->dclk_min_div = SUN6I_DSI_TCON_DIV; 370 tcon->dclk_max_div = SUN6I_DSI_TCON_DIV; 371 372 sun4i_tcon0_mode_set_common(tcon, mode); 373 374 /* Set dithering if needed */ 375 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 376 377 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 378 SUN4I_TCON0_CTL_IF_MASK, 379 SUN4I_TCON0_CTL_IF_8080); 380 381 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, 382 SUN4I_TCON_ECC_FIFO_EN); 383 384 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, 385 SUN4I_TCON0_CPU_IF_MODE_DSI | 386 SUN4I_TCON0_CPU_IF_TRI_FIFO_FLUSH | 387 SUN4I_TCON0_CPU_IF_TRI_FIFO_EN | 388 SUN4I_TCON0_CPU_IF_TRI_EN); 389 390 /* 391 * This looks suspicious, but it works... 392 * 393 * The datasheet says that this should be set higher than 20 * 394 * pixel cycle, but it's not clear what a pixel cycle is. 395 */ 396 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); 397 tcon_div &= GENMASK(6, 0); 398 block_space = mode->htotal * bpp / (tcon_div * lanes); 399 block_space -= mode->hdisplay + 40; 400 401 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, 402 SUN4I_TCON0_CPU_TRI0_BLOCK_SPACE(block_space) | 403 SUN4I_TCON0_CPU_TRI0_BLOCK_SIZE(mode->hdisplay)); 404 405 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, 406 SUN4I_TCON0_CPU_TRI1_BLOCK_NUM(mode->vdisplay)); 407 408 start_delay = (mode->crtc_vtotal - mode->crtc_vdisplay - 10 - 1); 409 start_delay = start_delay * mode->crtc_htotal * 149; 410 start_delay = start_delay / (mode->crtc_clock / 1000) / 8; 411 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, 412 SUN4I_TCON0_CPU_TRI2_TRANS_START_SET(10) | 413 SUN4I_TCON0_CPU_TRI2_START_DELAY(start_delay)); 414 415 /* 416 * The Allwinner BSP has a comment that the period should be 417 * the display clock * 15, but uses an hardcoded 3000... 418 */ 419 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, 420 SUN4I_TCON_SAFE_PERIOD_NUM(3000) | 421 SUN4I_TCON_SAFE_PERIOD_MODE(3)); 422 423 /* Enable the output on the pins */ 424 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 425 0xe0000000); 426 } 427 428 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, 429 const struct drm_encoder *encoder, 430 const struct drm_display_mode *mode) 431 { 432 unsigned int bp; 433 u8 clk_delay; 434 u32 reg, val = 0; 435 436 WARN_ON(!tcon->quirks->has_channel_0); 437 438 tcon->dclk_min_div = 7; 439 tcon->dclk_max_div = 7; 440 sun4i_tcon0_mode_set_common(tcon, mode); 441 442 /* Set dithering if needed */ 443 sun4i_tcon0_mode_set_dithering(tcon, sun4i_tcon_get_connector(encoder)); 444 445 /* Adjust clock delay */ 446 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 447 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 448 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 449 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 450 451 /* 452 * This is called a backporch in the register documentation, 453 * but it really is the back porch + hsync 454 */ 455 bp = mode->crtc_htotal - mode->crtc_hsync_start; 456 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 457 mode->crtc_htotal, bp); 458 459 /* Set horizontal display timings */ 460 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 461 SUN4I_TCON0_BASIC1_H_TOTAL(mode->htotal) | 462 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 463 464 /* 465 * This is called a backporch in the register documentation, 466 * but it really is the back porch + hsync 467 */ 468 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 469 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 470 mode->crtc_vtotal, bp); 471 472 /* Set vertical display timings */ 473 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 474 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 475 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 476 477 reg = SUN4I_TCON0_LVDS_IF_CLK_SEL_TCON0 | 478 SUN4I_TCON0_LVDS_IF_DATA_POL_NORMAL | 479 SUN4I_TCON0_LVDS_IF_CLK_POL_NORMAL; 480 if (sun4i_tcon_get_pixel_depth(encoder) == 24) 481 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_24BITS; 482 else 483 reg |= SUN4I_TCON0_LVDS_IF_BITWIDTH_18BITS; 484 485 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); 486 487 /* Setup the polarity of the various signals */ 488 if (!(mode->flags & DRM_MODE_FLAG_PHSYNC)) 489 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 490 491 if (!(mode->flags & DRM_MODE_FLAG_PVSYNC)) 492 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 493 494 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); 495 496 /* Map output pins to channel 0 */ 497 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 498 SUN4I_TCON_GCTL_IOMAP_MASK, 499 SUN4I_TCON_GCTL_IOMAP_TCON0); 500 501 /* Enable the output on the pins */ 502 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); 503 } 504 505 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, 506 const struct drm_encoder *encoder, 507 const struct drm_display_mode *mode) 508 { 509 struct drm_connector *connector = sun4i_tcon_get_connector(encoder); 510 const struct drm_display_info *info = &connector->display_info; 511 unsigned int bp, hsync, vsync; 512 u8 clk_delay; 513 u32 val = 0; 514 515 WARN_ON(!tcon->quirks->has_channel_0); 516 517 tcon->dclk_min_div = tcon->quirks->dclk_min_div; 518 tcon->dclk_max_div = 127; 519 sun4i_tcon0_mode_set_common(tcon, mode); 520 521 /* Set dithering if needed */ 522 sun4i_tcon0_mode_set_dithering(tcon, connector); 523 524 /* Adjust clock delay */ 525 clk_delay = sun4i_tcon_get_clk_delay(mode, 0); 526 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 527 SUN4I_TCON0_CTL_CLK_DELAY_MASK, 528 SUN4I_TCON0_CTL_CLK_DELAY(clk_delay)); 529 530 /* 531 * This is called a backporch in the register documentation, 532 * but it really is the back porch + hsync 533 */ 534 bp = mode->crtc_htotal - mode->crtc_hsync_start; 535 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 536 mode->crtc_htotal, bp); 537 538 /* Set horizontal display timings */ 539 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, 540 SUN4I_TCON0_BASIC1_H_TOTAL(mode->crtc_htotal) | 541 SUN4I_TCON0_BASIC1_H_BACKPORCH(bp)); 542 543 /* 544 * This is called a backporch in the register documentation, 545 * but it really is the back porch + hsync 546 */ 547 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 548 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 549 mode->crtc_vtotal, bp); 550 551 /* Set vertical display timings */ 552 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, 553 SUN4I_TCON0_BASIC2_V_TOTAL(mode->crtc_vtotal * 2) | 554 SUN4I_TCON0_BASIC2_V_BACKPORCH(bp)); 555 556 /* Set Hsync and Vsync length */ 557 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 558 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 559 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 560 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, 561 SUN4I_TCON0_BASIC3_V_SYNC(vsync) | 562 SUN4I_TCON0_BASIC3_H_SYNC(hsync)); 563 564 /* Setup the polarity of the various signals */ 565 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 566 val |= SUN4I_TCON0_IO_POL_HSYNC_POSITIVE; 567 568 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 569 val |= SUN4I_TCON0_IO_POL_VSYNC_POSITIVE; 570 571 if (info->bus_flags & DRM_BUS_FLAG_DE_LOW) 572 val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE; 573 574 /* 575 * On A20 and similar SoCs, the only way to achieve Positive Edge 576 * (Rising Edge), is setting dclk clock phase to 2/3(240°). 577 * By default TCON works in Negative Edge(Falling Edge), 578 * this is why phase is set to 0 in that case. 579 * Unfortunately there's no way to logically invert dclk through 580 * IO_POL register. 581 * The only acceptable way to work, triple checked with scope, 582 * is using clock phase set to 0° for Negative Edge and set to 240° 583 * for Positive Edge. 584 * On A33 and similar SoCs there would be a 90° phase option, 585 * but it divides also dclk by 2. 586 * Following code is a way to avoid quirks all around TCON 587 * and DOTCLOCK drivers. 588 */ 589 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE) 590 clk_set_phase(tcon->dclk, 240); 591 592 if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE) 593 clk_set_phase(tcon->dclk, 0); 594 595 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, 596 SUN4I_TCON0_IO_POL_HSYNC_POSITIVE | 597 SUN4I_TCON0_IO_POL_VSYNC_POSITIVE | 598 SUN4I_TCON0_IO_POL_DE_NEGATIVE, 599 val); 600 601 /* Map output pins to channel 0 */ 602 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 603 SUN4I_TCON_GCTL_IOMAP_MASK, 604 SUN4I_TCON_GCTL_IOMAP_TCON0); 605 606 /* Enable the output on the pins */ 607 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); 608 } 609 610 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, 611 const struct drm_display_mode *mode) 612 { 613 unsigned int bp, hsync, vsync, vtotal; 614 u8 clk_delay; 615 u32 val; 616 617 WARN_ON(!tcon->quirks->has_channel_1); 618 619 /* Configure the dot clock */ 620 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); 621 622 /* Adjust clock delay */ 623 clk_delay = sun4i_tcon_get_clk_delay(mode, 1); 624 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 625 SUN4I_TCON1_CTL_CLK_DELAY_MASK, 626 SUN4I_TCON1_CTL_CLK_DELAY(clk_delay)); 627 628 /* Set interlaced mode */ 629 if (mode->flags & DRM_MODE_FLAG_INTERLACE) 630 val = SUN4I_TCON1_CTL_INTERLACE_ENABLE; 631 else 632 val = 0; 633 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 634 SUN4I_TCON1_CTL_INTERLACE_ENABLE, 635 val); 636 637 /* Set the input resolution */ 638 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, 639 SUN4I_TCON1_BASIC0_X(mode->crtc_hdisplay) | 640 SUN4I_TCON1_BASIC0_Y(mode->crtc_vdisplay)); 641 642 /* Set the upscaling resolution */ 643 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, 644 SUN4I_TCON1_BASIC1_X(mode->crtc_hdisplay) | 645 SUN4I_TCON1_BASIC1_Y(mode->crtc_vdisplay)); 646 647 /* Set the output resolution */ 648 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, 649 SUN4I_TCON1_BASIC2_X(mode->crtc_hdisplay) | 650 SUN4I_TCON1_BASIC2_Y(mode->crtc_vdisplay)); 651 652 /* Set horizontal display timings */ 653 bp = mode->crtc_htotal - mode->crtc_hsync_start; 654 DRM_DEBUG_DRIVER("Setting horizontal total %d, backporch %d\n", 655 mode->htotal, bp); 656 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, 657 SUN4I_TCON1_BASIC3_H_TOTAL(mode->crtc_htotal) | 658 SUN4I_TCON1_BASIC3_H_BACKPORCH(bp)); 659 660 bp = mode->crtc_vtotal - mode->crtc_vsync_start; 661 DRM_DEBUG_DRIVER("Setting vertical total %d, backporch %d\n", 662 mode->crtc_vtotal, bp); 663 664 /* 665 * The vertical resolution needs to be doubled in all 666 * cases. We could use crtc_vtotal and always multiply by two, 667 * but that leads to a rounding error in interlace when vtotal 668 * is odd. 669 * 670 * This happens with TV's PAL for example, where vtotal will 671 * be 625, crtc_vtotal 312, and thus crtc_vtotal * 2 will be 672 * 624, which apparently confuses the hardware. 673 * 674 * To work around this, we will always use vtotal, and 675 * multiply by two only if we're not in interlace. 676 */ 677 vtotal = mode->vtotal; 678 if (!(mode->flags & DRM_MODE_FLAG_INTERLACE)) 679 vtotal = vtotal * 2; 680 681 /* Set vertical display timings */ 682 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, 683 SUN4I_TCON1_BASIC4_V_TOTAL(vtotal) | 684 SUN4I_TCON1_BASIC4_V_BACKPORCH(bp)); 685 686 /* Set Hsync and Vsync length */ 687 hsync = mode->crtc_hsync_end - mode->crtc_hsync_start; 688 vsync = mode->crtc_vsync_end - mode->crtc_vsync_start; 689 DRM_DEBUG_DRIVER("Setting HSYNC %d, VSYNC %d\n", hsync, vsync); 690 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, 691 SUN4I_TCON1_BASIC5_V_SYNC(vsync) | 692 SUN4I_TCON1_BASIC5_H_SYNC(hsync)); 693 694 /* Map output pins to channel 1 */ 695 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, 696 SUN4I_TCON_GCTL_IOMAP_MASK, 697 SUN4I_TCON_GCTL_IOMAP_TCON1); 698 } 699 700 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, 701 const struct drm_encoder *encoder, 702 const struct drm_display_mode *mode) 703 { 704 switch (encoder->encoder_type) { 705 case DRM_MODE_ENCODER_DSI: 706 /* DSI is tied to special case of CPU interface */ 707 sun4i_tcon0_mode_set_cpu(tcon, encoder, mode); 708 break; 709 case DRM_MODE_ENCODER_LVDS: 710 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); 711 break; 712 case DRM_MODE_ENCODER_NONE: 713 sun4i_tcon0_mode_set_rgb(tcon, encoder, mode); 714 sun4i_tcon_set_mux(tcon, 0, encoder); 715 break; 716 case DRM_MODE_ENCODER_TVDAC: 717 case DRM_MODE_ENCODER_TMDS: 718 sun4i_tcon1_mode_set(tcon, mode); 719 sun4i_tcon_set_mux(tcon, 1, encoder); 720 break; 721 default: 722 DRM_DEBUG_DRIVER("Unknown encoder type, doing nothing...\n"); 723 } 724 } 725 EXPORT_SYMBOL(sun4i_tcon_mode_set); 726 727 static void sun4i_tcon_finish_page_flip(struct drm_device *dev, 728 struct sun4i_crtc *scrtc) 729 { 730 unsigned long flags; 731 732 spin_lock_irqsave(&dev->event_lock, flags); 733 if (scrtc->event) { 734 drm_crtc_send_vblank_event(&scrtc->crtc, scrtc->event); 735 drm_crtc_vblank_put(&scrtc->crtc); 736 scrtc->event = NULL; 737 } 738 spin_unlock_irqrestore(&dev->event_lock, flags); 739 } 740 741 static irqreturn_t sun4i_tcon_handler(int irq, void *private) 742 { 743 struct sun4i_tcon *tcon = private; 744 struct drm_device *drm = tcon->drm; 745 struct sun4i_crtc *scrtc = tcon->crtc; 746 struct sunxi_engine *engine = scrtc->engine; 747 unsigned int status; 748 749 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); 750 751 if (!(status & (SUN4I_TCON_GINT0_VBLANK_INT(0) | 752 SUN4I_TCON_GINT0_VBLANK_INT(1) | 753 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT))) 754 return IRQ_NONE; 755 756 drm_crtc_handle_vblank(&scrtc->crtc); 757 sun4i_tcon_finish_page_flip(drm, scrtc); 758 759 /* Acknowledge the interrupt */ 760 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, 761 SUN4I_TCON_GINT0_VBLANK_INT(0) | 762 SUN4I_TCON_GINT0_VBLANK_INT(1) | 763 SUN4I_TCON_GINT0_TCON0_TRI_FINISH_INT, 764 0); 765 766 if (engine->ops->vblank_quirk) 767 engine->ops->vblank_quirk(engine); 768 769 return IRQ_HANDLED; 770 } 771 772 static int sun4i_tcon_init_clocks(struct device *dev, 773 struct sun4i_tcon *tcon) 774 { 775 tcon->clk = devm_clk_get(dev, "ahb"); 776 if (IS_ERR(tcon->clk)) { 777 dev_err(dev, "Couldn't get the TCON bus clock\n"); 778 return PTR_ERR(tcon->clk); 779 } 780 clk_prepare_enable(tcon->clk); 781 782 if (tcon->quirks->has_channel_0) { 783 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); 784 if (IS_ERR(tcon->sclk0)) { 785 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); 786 return PTR_ERR(tcon->sclk0); 787 } 788 } 789 clk_prepare_enable(tcon->sclk0); 790 791 if (tcon->quirks->has_channel_1) { 792 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); 793 if (IS_ERR(tcon->sclk1)) { 794 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); 795 return PTR_ERR(tcon->sclk1); 796 } 797 } 798 799 return 0; 800 } 801 802 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) 803 { 804 clk_disable_unprepare(tcon->sclk0); 805 clk_disable_unprepare(tcon->clk); 806 } 807 808 static int sun4i_tcon_init_irq(struct device *dev, 809 struct sun4i_tcon *tcon) 810 { 811 struct platform_device *pdev = to_platform_device(dev); 812 int irq, ret; 813 814 irq = platform_get_irq(pdev, 0); 815 if (irq < 0) { 816 dev_err(dev, "Couldn't retrieve the TCON interrupt\n"); 817 return irq; 818 } 819 820 ret = devm_request_irq(dev, irq, sun4i_tcon_handler, 0, 821 dev_name(dev), tcon); 822 if (ret) { 823 dev_err(dev, "Couldn't request the IRQ\n"); 824 return ret; 825 } 826 827 return 0; 828 } 829 830 static struct regmap_config sun4i_tcon_regmap_config = { 831 .reg_bits = 32, 832 .val_bits = 32, 833 .reg_stride = 4, 834 .max_register = 0x800, 835 }; 836 837 static int sun4i_tcon_init_regmap(struct device *dev, 838 struct sun4i_tcon *tcon) 839 { 840 struct platform_device *pdev = to_platform_device(dev); 841 struct resource *res; 842 void __iomem *regs; 843 844 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 845 regs = devm_ioremap_resource(dev, res); 846 if (IS_ERR(regs)) 847 return PTR_ERR(regs); 848 849 tcon->regs = devm_regmap_init_mmio(dev, regs, 850 &sun4i_tcon_regmap_config); 851 if (IS_ERR(tcon->regs)) { 852 dev_err(dev, "Couldn't create the TCON regmap\n"); 853 return PTR_ERR(tcon->regs); 854 } 855 856 /* Make sure the TCON is disabled and all IRQs are off */ 857 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); 858 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); 859 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); 860 861 /* Disable IO lines and set them to tristate */ 862 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); 863 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); 864 865 return 0; 866 } 867 868 /* 869 * On SoCs with the old display pipeline design (Display Engine 1.0), 870 * the TCON is always tied to just one backend. Hence we can traverse 871 * the of_graph upwards to find the backend our tcon is connected to, 872 * and take its ID as our own. 873 * 874 * We can either identify backends from their compatible strings, which 875 * means maintaining a large list of them. Or, since the backend is 876 * registered and binded before the TCON, we can just go through the 877 * list of registered backends and compare the device node. 878 * 879 * As the structures now store engines instead of backends, here this 880 * function in fact searches the corresponding engine, and the ID is 881 * requested via the get_id function of the engine. 882 */ 883 static struct sunxi_engine * 884 sun4i_tcon_find_engine_traverse(struct sun4i_drv *drv, 885 struct device_node *node, 886 u32 port_id) 887 { 888 struct device_node *port, *ep, *remote; 889 struct sunxi_engine *engine = ERR_PTR(-EINVAL); 890 u32 reg = 0; 891 892 port = of_graph_get_port_by_id(node, port_id); 893 if (!port) 894 return ERR_PTR(-EINVAL); 895 896 /* 897 * This only works if there is only one path from the TCON 898 * to any display engine. Otherwise the probe order of the 899 * TCONs and display engines is not guaranteed. They may 900 * either bind to the wrong one, or worse, bind to the same 901 * one if additional checks are not done. 902 * 903 * Bail out if there are multiple input connections. 904 */ 905 if (of_get_available_child_count(port) != 1) 906 goto out_put_port; 907 908 /* Get the first connection without specifying an ID */ 909 ep = of_get_next_available_child(port, NULL); 910 if (!ep) 911 goto out_put_port; 912 913 remote = of_graph_get_remote_port_parent(ep); 914 if (!remote) 915 goto out_put_ep; 916 917 /* does this node match any registered engines? */ 918 list_for_each_entry(engine, &drv->engine_list, list) 919 if (remote == engine->node) 920 goto out_put_remote; 921 922 /* 923 * According to device tree binding input ports have even id 924 * number and output ports have odd id. Since component with 925 * more than one input and one output (TCON TOP) exits, correct 926 * remote input id has to be calculated by subtracting 1 from 927 * remote output id. If this for some reason can't be done, 0 928 * is used as input port id. 929 */ 930 of_node_put(port); 931 port = of_graph_get_remote_port(ep); 932 if (!of_property_read_u32(port, "reg", ®) && reg > 0) 933 reg -= 1; 934 935 /* keep looking through upstream ports */ 936 engine = sun4i_tcon_find_engine_traverse(drv, remote, reg); 937 938 out_put_remote: 939 of_node_put(remote); 940 out_put_ep: 941 of_node_put(ep); 942 out_put_port: 943 of_node_put(port); 944 945 return engine; 946 } 947 948 /* 949 * The device tree binding says that the remote endpoint ID of any 950 * connection between components, up to and including the TCON, of 951 * the display pipeline should be equal to the actual ID of the local 952 * component. Thus we can look at any one of the input connections of 953 * the TCONs, and use that connection's remote endpoint ID as our own. 954 * 955 * Since the user of this function already finds the input port, 956 * the port is passed in directly without further checks. 957 */ 958 static int sun4i_tcon_of_get_id_from_port(struct device_node *port) 959 { 960 struct device_node *ep; 961 int ret = -EINVAL; 962 963 /* try finding an upstream endpoint */ 964 for_each_available_child_of_node(port, ep) { 965 struct device_node *remote; 966 u32 reg; 967 968 remote = of_graph_get_remote_endpoint(ep); 969 if (!remote) 970 continue; 971 972 ret = of_property_read_u32(remote, "reg", ®); 973 if (ret) 974 continue; 975 976 ret = reg; 977 } 978 979 return ret; 980 } 981 982 /* 983 * Once we know the TCON's id, we can look through the list of 984 * engines to find a matching one. We assume all engines have 985 * been probed and added to the list. 986 */ 987 static struct sunxi_engine *sun4i_tcon_get_engine_by_id(struct sun4i_drv *drv, 988 int id) 989 { 990 struct sunxi_engine *engine; 991 992 list_for_each_entry(engine, &drv->engine_list, list) 993 if (engine->id == id) 994 return engine; 995 996 return ERR_PTR(-EINVAL); 997 } 998 999 static bool sun4i_tcon_connected_to_tcon_top(struct device_node *node) 1000 { 1001 struct device_node *remote; 1002 bool ret = false; 1003 1004 remote = of_graph_get_remote_node(node, 0, -1); 1005 if (remote) { 1006 ret = !!(IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1007 of_match_node(sun8i_tcon_top_of_table, remote)); 1008 of_node_put(remote); 1009 } 1010 1011 return ret; 1012 } 1013 1014 static int sun4i_tcon_get_index(struct sun4i_drv *drv) 1015 { 1016 struct list_head *pos; 1017 int size = 0; 1018 1019 /* 1020 * Because TCON is added to the list at the end of the probe 1021 * (after this function is called), index of the current TCON 1022 * will be same as current TCON list size. 1023 */ 1024 list_for_each(pos, &drv->tcon_list) 1025 ++size; 1026 1027 return size; 1028 } 1029 1030 /* 1031 * On SoCs with the old display pipeline design (Display Engine 1.0), 1032 * we assumed the TCON was always tied to just one backend. However 1033 * this proved not to be the case. On the A31, the TCON can select 1034 * either backend as its source. On the A20 (and likely on the A10), 1035 * the backend can choose which TCON to output to. 1036 * 1037 * The device tree binding says that the remote endpoint ID of any 1038 * connection between components, up to and including the TCON, of 1039 * the display pipeline should be equal to the actual ID of the local 1040 * component. Thus we should be able to look at any one of the input 1041 * connections of the TCONs, and use that connection's remote endpoint 1042 * ID as our own. 1043 * 1044 * However the connections between the backend and TCON were assumed 1045 * to be always singular, and their endpoit IDs were all incorrectly 1046 * set to 0. This means for these old device trees, we cannot just look 1047 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be 1048 * incorrectly identified as TCON0. 1049 * 1050 * This function first checks if the TCON node has 2 input endpoints. 1051 * If so, then the device tree is a corrected version, and it will use 1052 * sun4i_tcon_of_get_id() and sun4i_tcon_get_engine_by_id() from above 1053 * to fetch the ID and engine directly. If not, then it is likely an 1054 * old device trees, where the endpoint IDs were incorrect, but did not 1055 * have endpoint connections between the backend and TCON across 1056 * different display pipelines. It will fall back to the old method of 1057 * traversing the of_graph to try and find a matching engine by device 1058 * node. 1059 * 1060 * In the case of single display pipeline device trees, either method 1061 * works. 1062 */ 1063 static struct sunxi_engine *sun4i_tcon_find_engine(struct sun4i_drv *drv, 1064 struct device_node *node) 1065 { 1066 struct device_node *port; 1067 struct sunxi_engine *engine; 1068 1069 port = of_graph_get_port_by_id(node, 0); 1070 if (!port) 1071 return ERR_PTR(-EINVAL); 1072 1073 /* 1074 * Is this a corrected device tree with cross pipeline 1075 * connections between the backend and TCON? 1076 */ 1077 if (of_get_child_count(port) > 1) { 1078 int id; 1079 1080 /* 1081 * When pipeline has the same number of TCONs and engines which 1082 * are represented by frontends/backends (DE1) or mixers (DE2), 1083 * we match them by their respective IDs. However, if pipeline 1084 * contains TCON TOP, chances are that there are either more 1085 * TCONs than engines (R40) or TCONs with non-consecutive ids. 1086 * (H6). In that case it's easier just use TCON index in list 1087 * as an id. That means that on R40, any 2 TCONs can be enabled 1088 * in DT out of 4 (there are 2 mixers). Due to the design of 1089 * TCON TOP, remaining 2 TCONs can't be connected to anything 1090 * anyway. 1091 */ 1092 if (sun4i_tcon_connected_to_tcon_top(node)) 1093 id = sun4i_tcon_get_index(drv); 1094 else 1095 id = sun4i_tcon_of_get_id_from_port(port); 1096 1097 /* Get our engine by matching our ID */ 1098 engine = sun4i_tcon_get_engine_by_id(drv, id); 1099 1100 of_node_put(port); 1101 return engine; 1102 } 1103 1104 /* Fallback to old method by traversing input endpoints */ 1105 of_node_put(port); 1106 return sun4i_tcon_find_engine_traverse(drv, node, 0); 1107 } 1108 1109 static int sun4i_tcon_bind(struct device *dev, struct device *master, 1110 void *data) 1111 { 1112 struct drm_device *drm = data; 1113 struct sun4i_drv *drv = drm->dev_private; 1114 struct sunxi_engine *engine; 1115 struct device_node *remote; 1116 struct sun4i_tcon *tcon; 1117 struct reset_control *edp_rstc; 1118 bool has_lvds_rst, has_lvds_alt, can_lvds; 1119 int ret; 1120 1121 engine = sun4i_tcon_find_engine(drv, dev->of_node); 1122 if (IS_ERR(engine)) { 1123 dev_err(dev, "Couldn't find matching engine\n"); 1124 return -EPROBE_DEFER; 1125 } 1126 1127 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); 1128 if (!tcon) 1129 return -ENOMEM; 1130 dev_set_drvdata(dev, tcon); 1131 tcon->drm = drm; 1132 tcon->dev = dev; 1133 tcon->id = engine->id; 1134 tcon->quirks = of_device_get_match_data(dev); 1135 1136 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); 1137 if (IS_ERR(tcon->lcd_rst)) { 1138 dev_err(dev, "Couldn't get our reset line\n"); 1139 return PTR_ERR(tcon->lcd_rst); 1140 } 1141 1142 if (tcon->quirks->needs_edp_reset) { 1143 edp_rstc = devm_reset_control_get_shared(dev, "edp"); 1144 if (IS_ERR(edp_rstc)) { 1145 dev_err(dev, "Couldn't get edp reset line\n"); 1146 return PTR_ERR(edp_rstc); 1147 } 1148 1149 ret = reset_control_deassert(edp_rstc); 1150 if (ret) { 1151 dev_err(dev, "Couldn't deassert edp reset line\n"); 1152 return ret; 1153 } 1154 } 1155 1156 /* Make sure our TCON is reset */ 1157 ret = reset_control_reset(tcon->lcd_rst); 1158 if (ret) { 1159 dev_err(dev, "Couldn't deassert our reset line\n"); 1160 return ret; 1161 } 1162 1163 if (tcon->quirks->supports_lvds) { 1164 /* 1165 * This can only be made optional since we've had DT 1166 * nodes without the LVDS reset properties. 1167 * 1168 * If the property is missing, just disable LVDS, and 1169 * print a warning. 1170 */ 1171 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); 1172 if (IS_ERR(tcon->lvds_rst)) { 1173 dev_err(dev, "Couldn't get our reset line\n"); 1174 return PTR_ERR(tcon->lvds_rst); 1175 } else if (tcon->lvds_rst) { 1176 has_lvds_rst = true; 1177 reset_control_reset(tcon->lvds_rst); 1178 } else { 1179 has_lvds_rst = false; 1180 } 1181 1182 /* 1183 * This can only be made optional since we've had DT 1184 * nodes without the LVDS reset properties. 1185 * 1186 * If the property is missing, just disable LVDS, and 1187 * print a warning. 1188 */ 1189 if (tcon->quirks->has_lvds_alt) { 1190 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); 1191 if (IS_ERR(tcon->lvds_pll)) { 1192 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { 1193 has_lvds_alt = false; 1194 } else { 1195 dev_err(dev, "Couldn't get the LVDS PLL\n"); 1196 return PTR_ERR(tcon->lvds_pll); 1197 } 1198 } else { 1199 has_lvds_alt = true; 1200 } 1201 } 1202 1203 if (!has_lvds_rst || 1204 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { 1205 dev_warn(dev, "Missing LVDS properties, Please upgrade your DT\n"); 1206 dev_warn(dev, "LVDS output disabled\n"); 1207 can_lvds = false; 1208 } else { 1209 can_lvds = true; 1210 } 1211 } else { 1212 can_lvds = false; 1213 } 1214 1215 ret = sun4i_tcon_init_clocks(dev, tcon); 1216 if (ret) { 1217 dev_err(dev, "Couldn't init our TCON clocks\n"); 1218 goto err_assert_reset; 1219 } 1220 1221 ret = sun4i_tcon_init_regmap(dev, tcon); 1222 if (ret) { 1223 dev_err(dev, "Couldn't init our TCON regmap\n"); 1224 goto err_free_clocks; 1225 } 1226 1227 if (tcon->quirks->has_channel_0) { 1228 ret = sun4i_dclk_create(dev, tcon); 1229 if (ret) { 1230 dev_err(dev, "Couldn't create our TCON dot clock\n"); 1231 goto err_free_clocks; 1232 } 1233 } 1234 1235 ret = sun4i_tcon_init_irq(dev, tcon); 1236 if (ret) { 1237 dev_err(dev, "Couldn't init our TCON interrupts\n"); 1238 goto err_free_dotclock; 1239 } 1240 1241 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); 1242 if (IS_ERR(tcon->crtc)) { 1243 dev_err(dev, "Couldn't create our CRTC\n"); 1244 ret = PTR_ERR(tcon->crtc); 1245 goto err_free_dotclock; 1246 } 1247 1248 if (tcon->quirks->has_channel_0) { 1249 /* 1250 * If we have an LVDS panel connected to the TCON, we should 1251 * just probe the LVDS connector. Otherwise, just probe RGB as 1252 * we used to. 1253 */ 1254 remote = of_graph_get_remote_node(dev->of_node, 1, 0); 1255 if (of_device_is_compatible(remote, "panel-lvds")) 1256 if (can_lvds) 1257 ret = sun4i_lvds_init(drm, tcon); 1258 else 1259 ret = -EINVAL; 1260 else 1261 ret = sun4i_rgb_init(drm, tcon); 1262 of_node_put(remote); 1263 1264 if (ret < 0) 1265 goto err_free_dotclock; 1266 } 1267 1268 if (tcon->quirks->needs_de_be_mux) { 1269 /* 1270 * We assume there is no dynamic muxing of backends 1271 * and TCONs, so we select the backend with same ID. 1272 * 1273 * While dynamic selection might be interesting, since 1274 * the CRTC is tied to the TCON, while the layers are 1275 * tied to the backends, this means, we will need to 1276 * switch between groups of layers. There might not be 1277 * a way to represent this constraint in DRM. 1278 */ 1279 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, 1280 SUN4I_TCON0_CTL_SRC_SEL_MASK, 1281 tcon->id); 1282 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, 1283 SUN4I_TCON1_CTL_SRC_SEL_MASK, 1284 tcon->id); 1285 } 1286 1287 list_add_tail(&tcon->list, &drv->tcon_list); 1288 1289 return 0; 1290 1291 err_free_dotclock: 1292 if (tcon->quirks->has_channel_0) 1293 sun4i_dclk_free(tcon); 1294 err_free_clocks: 1295 sun4i_tcon_free_clocks(tcon); 1296 err_assert_reset: 1297 reset_control_assert(tcon->lcd_rst); 1298 return ret; 1299 } 1300 1301 static void sun4i_tcon_unbind(struct device *dev, struct device *master, 1302 void *data) 1303 { 1304 struct sun4i_tcon *tcon = dev_get_drvdata(dev); 1305 1306 list_del(&tcon->list); 1307 if (tcon->quirks->has_channel_0) 1308 sun4i_dclk_free(tcon); 1309 sun4i_tcon_free_clocks(tcon); 1310 } 1311 1312 static const struct component_ops sun4i_tcon_ops = { 1313 .bind = sun4i_tcon_bind, 1314 .unbind = sun4i_tcon_unbind, 1315 }; 1316 1317 static int sun4i_tcon_probe(struct platform_device *pdev) 1318 { 1319 struct device_node *node = pdev->dev.of_node; 1320 const struct sun4i_tcon_quirks *quirks; 1321 struct drm_bridge *bridge; 1322 struct drm_panel *panel; 1323 int ret; 1324 1325 quirks = of_device_get_match_data(&pdev->dev); 1326 1327 /* panels and bridges are present only on TCONs with channel 0 */ 1328 if (quirks->has_channel_0) { 1329 ret = drm_of_find_panel_or_bridge(node, 1, 0, &panel, &bridge); 1330 if (ret == -EPROBE_DEFER) 1331 return ret; 1332 } 1333 1334 return component_add(&pdev->dev, &sun4i_tcon_ops); 1335 } 1336 1337 static int sun4i_tcon_remove(struct platform_device *pdev) 1338 { 1339 component_del(&pdev->dev, &sun4i_tcon_ops); 1340 1341 return 0; 1342 } 1343 1344 /* platform specific TCON muxing callbacks */ 1345 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, 1346 const struct drm_encoder *encoder) 1347 { 1348 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1349 u32 shift; 1350 1351 if (!tcon0) 1352 return -EINVAL; 1353 1354 switch (encoder->encoder_type) { 1355 case DRM_MODE_ENCODER_TMDS: 1356 /* HDMI */ 1357 shift = 8; 1358 break; 1359 default: 1360 return -EINVAL; 1361 } 1362 1363 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1364 0x3 << shift, tcon->id << shift); 1365 1366 return 0; 1367 } 1368 1369 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, 1370 const struct drm_encoder *encoder) 1371 { 1372 u32 val; 1373 1374 if (encoder->encoder_type == DRM_MODE_ENCODER_TVDAC) 1375 val = 1; 1376 else 1377 val = 0; 1378 1379 /* 1380 * FIXME: Undocumented bits 1381 */ 1382 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); 1383 } 1384 1385 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, 1386 const struct drm_encoder *encoder) 1387 { 1388 struct sun4i_tcon *tcon0 = sun4i_get_tcon0(encoder->dev); 1389 u32 shift; 1390 1391 if (!tcon0) 1392 return -EINVAL; 1393 1394 switch (encoder->encoder_type) { 1395 case DRM_MODE_ENCODER_TMDS: 1396 /* HDMI */ 1397 shift = 8; 1398 break; 1399 default: 1400 /* TODO A31 has MIPI DSI but A31s does not */ 1401 return -EINVAL; 1402 } 1403 1404 regmap_update_bits(tcon0->regs, SUN4I_TCON_MUX_CTRL_REG, 1405 0x3 << shift, tcon->id << shift); 1406 1407 return 0; 1408 } 1409 1410 static int sun8i_r40_tcon_tv_set_mux(struct sun4i_tcon *tcon, 1411 const struct drm_encoder *encoder) 1412 { 1413 struct device_node *port, *remote; 1414 struct platform_device *pdev; 1415 int id, ret; 1416 1417 /* find TCON TOP platform device and TCON id */ 1418 1419 port = of_graph_get_port_by_id(tcon->dev->of_node, 0); 1420 if (!port) 1421 return -EINVAL; 1422 1423 id = sun4i_tcon_of_get_id_from_port(port); 1424 of_node_put(port); 1425 1426 remote = of_graph_get_remote_node(tcon->dev->of_node, 0, -1); 1427 if (!remote) 1428 return -EINVAL; 1429 1430 pdev = of_find_device_by_node(remote); 1431 of_node_put(remote); 1432 if (!pdev) 1433 return -EINVAL; 1434 1435 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) && 1436 encoder->encoder_type == DRM_MODE_ENCODER_TMDS) { 1437 ret = sun8i_tcon_top_set_hdmi_src(&pdev->dev, id); 1438 if (ret) 1439 return ret; 1440 } 1441 1442 if (IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP)) { 1443 ret = sun8i_tcon_top_de_config(&pdev->dev, tcon->id, id); 1444 if (ret) 1445 return ret; 1446 } 1447 1448 return 0; 1449 } 1450 1451 static const struct sun4i_tcon_quirks sun4i_a10_quirks = { 1452 .has_channel_0 = true, 1453 .has_channel_1 = true, 1454 .dclk_min_div = 4, 1455 .set_mux = sun4i_a10_tcon_set_mux, 1456 }; 1457 1458 static const struct sun4i_tcon_quirks sun5i_a13_quirks = { 1459 .has_channel_0 = true, 1460 .has_channel_1 = true, 1461 .dclk_min_div = 4, 1462 .set_mux = sun5i_a13_tcon_set_mux, 1463 }; 1464 1465 static const struct sun4i_tcon_quirks sun6i_a31_quirks = { 1466 .has_channel_0 = true, 1467 .has_channel_1 = true, 1468 .has_lvds_alt = true, 1469 .needs_de_be_mux = true, 1470 .dclk_min_div = 1, 1471 .set_mux = sun6i_tcon_set_mux, 1472 }; 1473 1474 static const struct sun4i_tcon_quirks sun6i_a31s_quirks = { 1475 .has_channel_0 = true, 1476 .has_channel_1 = true, 1477 .needs_de_be_mux = true, 1478 .dclk_min_div = 1, 1479 }; 1480 1481 static const struct sun4i_tcon_quirks sun7i_a20_tcon0_quirks = { 1482 .supports_lvds = true, 1483 .has_channel_0 = true, 1484 .has_channel_1 = true, 1485 .dclk_min_div = 4, 1486 /* Same display pipeline structure as A10 */ 1487 .set_mux = sun4i_a10_tcon_set_mux, 1488 .setup_lvds_phy = sun4i_tcon_setup_lvds_phy, 1489 }; 1490 1491 static const struct sun4i_tcon_quirks sun7i_a20_quirks = { 1492 .has_channel_0 = true, 1493 .has_channel_1 = true, 1494 .dclk_min_div = 4, 1495 /* Same display pipeline structure as A10 */ 1496 .set_mux = sun4i_a10_tcon_set_mux, 1497 }; 1498 1499 static const struct sun4i_tcon_quirks sun8i_a33_quirks = { 1500 .has_channel_0 = true, 1501 .has_lvds_alt = true, 1502 .dclk_min_div = 1, 1503 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1504 .supports_lvds = true, 1505 }; 1506 1507 static const struct sun4i_tcon_quirks sun8i_a83t_lcd_quirks = { 1508 .supports_lvds = true, 1509 .has_channel_0 = true, 1510 .dclk_min_div = 1, 1511 .setup_lvds_phy = sun6i_tcon_setup_lvds_phy, 1512 }; 1513 1514 static const struct sun4i_tcon_quirks sun8i_a83t_tv_quirks = { 1515 .has_channel_1 = true, 1516 }; 1517 1518 static const struct sun4i_tcon_quirks sun8i_r40_tv_quirks = { 1519 .has_channel_1 = true, 1520 .set_mux = sun8i_r40_tcon_tv_set_mux, 1521 }; 1522 1523 static const struct sun4i_tcon_quirks sun8i_v3s_quirks = { 1524 .has_channel_0 = true, 1525 .dclk_min_div = 1, 1526 }; 1527 1528 static const struct sun4i_tcon_quirks sun9i_a80_tcon_lcd_quirks = { 1529 .has_channel_0 = true, 1530 .needs_edp_reset = true, 1531 .dclk_min_div = 1, 1532 }; 1533 1534 static const struct sun4i_tcon_quirks sun9i_a80_tcon_tv_quirks = { 1535 .has_channel_1 = true, 1536 .needs_edp_reset = true, 1537 }; 1538 1539 /* sun4i_drv uses this list to check if a device node is a TCON */ 1540 const struct of_device_id sun4i_tcon_of_table[] = { 1541 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks }, 1542 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks }, 1543 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks }, 1544 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks }, 1545 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks }, 1546 { .compatible = "allwinner,sun7i-a20-tcon0", .data = &sun7i_a20_tcon0_quirks }, 1547 { .compatible = "allwinner,sun7i-a20-tcon1", .data = &sun7i_a20_quirks }, 1548 { .compatible = "allwinner,sun8i-a23-tcon", .data = &sun8i_a33_quirks }, 1549 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks }, 1550 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks }, 1551 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks }, 1552 { .compatible = "allwinner,sun8i-r40-tcon-tv", .data = &sun8i_r40_tv_quirks }, 1553 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks }, 1554 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks }, 1555 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks }, 1556 { } 1557 }; 1558 MODULE_DEVICE_TABLE(of, sun4i_tcon_of_table); 1559 EXPORT_SYMBOL(sun4i_tcon_of_table); 1560 1561 static struct platform_driver sun4i_tcon_platform_driver = { 1562 .probe = sun4i_tcon_probe, 1563 .remove = sun4i_tcon_remove, 1564 .driver = { 1565 .name = "sun4i-tcon", 1566 .of_match_table = sun4i_tcon_of_table, 1567 }, 1568 }; 1569 module_platform_driver(sun4i_tcon_platform_driver); 1570 1571 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1572 MODULE_DESCRIPTION("Allwinner A10 Timing Controller Driver"); 1573 MODULE_LICENSE("GPL"); 1574