1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #include <drm/drmP.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_edid.h> 16 #include <drm/drm_encoder.h> 17 #include <drm/drm_of.h> 18 #include <drm/drm_panel.h> 19 20 #include <linux/clk.h> 21 #include <linux/component.h> 22 #include <linux/iopoll.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/reset.h> 28 29 #include "sun4i_backend.h" 30 #include "sun4i_crtc.h" 31 #include "sun4i_drv.h" 32 #include "sun4i_hdmi.h" 33 34 static inline struct sun4i_hdmi * 35 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) 36 { 37 return container_of(encoder, struct sun4i_hdmi, 38 encoder); 39 } 40 41 static inline struct sun4i_hdmi * 42 drm_connector_to_sun4i_hdmi(struct drm_connector *connector) 43 { 44 return container_of(connector, struct sun4i_hdmi, 45 connector); 46 } 47 48 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 49 struct drm_display_mode *mode) 50 { 51 struct hdmi_avi_infoframe frame; 52 u8 buffer[17]; 53 int i, ret; 54 55 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 56 &hdmi->connector, mode); 57 if (ret < 0) { 58 DRM_ERROR("Failed to get infoframes from mode\n"); 59 return ret; 60 } 61 62 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 63 if (ret < 0) { 64 DRM_ERROR("Failed to pack infoframes\n"); 65 return ret; 66 } 67 68 for (i = 0; i < sizeof(buffer); i++) 69 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 70 71 return 0; 72 } 73 74 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder, 75 struct drm_crtc_state *crtc_state, 76 struct drm_connector_state *conn_state) 77 { 78 struct drm_display_mode *mode = &crtc_state->mode; 79 80 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 static void sun4i_hdmi_disable(struct drm_encoder *encoder) 87 { 88 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 89 u32 val; 90 91 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 92 93 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 94 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 95 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 96 97 clk_disable_unprepare(hdmi->tmds_clk); 98 } 99 100 static void sun4i_hdmi_enable(struct drm_encoder *encoder) 101 { 102 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 103 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 104 u32 val = 0; 105 106 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 107 108 clk_prepare_enable(hdmi->tmds_clk); 109 110 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 111 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 112 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 113 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 114 115 val = SUN4I_HDMI_VID_CTRL_ENABLE; 116 if (hdmi->hdmi_monitor) 117 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 118 119 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 120 } 121 122 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder, 123 struct drm_display_mode *mode, 124 struct drm_display_mode *adjusted_mode) 125 { 126 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 127 unsigned int x, y; 128 u32 val; 129 130 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 131 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 132 133 /* Set input sync enable */ 134 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 135 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 136 137 /* 138 * Setup output pad (?) controls 139 * 140 * This is done here instead of at probe/bind time because 141 * the controller seems to toggle some of the bits on its own. 142 * 143 * We can't just initialize the register there, we need to 144 * protect the clock bits that have already been read out and 145 * cached by the clock framework. 146 */ 147 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 148 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 149 val |= hdmi->variant->pad_ctrl1_init_val; 150 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 151 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 152 153 /* Setup timing registers */ 154 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 155 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 156 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 157 158 x = mode->htotal - mode->hsync_start; 159 y = mode->vtotal - mode->vsync_start; 160 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 161 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 162 163 x = mode->hsync_start - mode->hdisplay; 164 y = mode->vsync_start - mode->vdisplay; 165 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 166 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 167 168 x = mode->hsync_end - mode->hsync_start; 169 y = mode->vsync_end - mode->vsync_start; 170 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 171 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 172 173 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 174 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 175 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 176 177 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 178 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 179 180 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 181 } 182 183 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder, 184 const struct drm_display_mode *mode) 185 { 186 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 187 unsigned long rate = mode->clock * 1000; 188 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ 189 long rounded_rate; 190 191 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 192 if (rate > 165000000) 193 return MODE_CLOCK_HIGH; 194 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); 195 if (rounded_rate > 0 && 196 max_t(unsigned long, rounded_rate, rate) - 197 min_t(unsigned long, rounded_rate, rate) < diff) 198 return MODE_OK; 199 return MODE_NOCLOCK; 200 } 201 202 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 203 .atomic_check = sun4i_hdmi_atomic_check, 204 .disable = sun4i_hdmi_disable, 205 .enable = sun4i_hdmi_enable, 206 .mode_set = sun4i_hdmi_mode_set, 207 .mode_valid = sun4i_hdmi_mode_valid, 208 }; 209 210 static const struct drm_encoder_funcs sun4i_hdmi_funcs = { 211 .destroy = drm_encoder_cleanup, 212 }; 213 214 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 215 { 216 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 217 struct edid *edid; 218 int ret; 219 220 edid = drm_get_edid(connector, hdmi->i2c); 221 if (!edid) 222 return 0; 223 224 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid); 225 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 226 hdmi->hdmi_monitor ? "an HDMI" : "a DVI"); 227 228 drm_connector_update_edid_property(connector, edid); 229 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); 230 ret = drm_add_edid_modes(connector, edid); 231 kfree(edid); 232 233 return ret; 234 } 235 236 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 237 .get_modes = sun4i_hdmi_get_modes, 238 }; 239 240 static enum drm_connector_status 241 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 242 { 243 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 244 unsigned long reg; 245 246 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, 247 reg & SUN4I_HDMI_HPD_HIGH, 248 0, 500000)) { 249 cec_phys_addr_invalidate(hdmi->cec_adap); 250 return connector_status_disconnected; 251 } 252 253 return connector_status_connected; 254 } 255 256 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 257 .detect = sun4i_hdmi_connector_detect, 258 .fill_modes = drm_helper_probe_single_connector_modes, 259 .destroy = drm_connector_cleanup, 260 .reset = drm_atomic_helper_connector_reset, 261 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 262 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 263 }; 264 265 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 266 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 267 { 268 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 269 270 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 271 } 272 273 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 274 { 275 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 276 277 /* Start driving the CEC pin low */ 278 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 279 } 280 281 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 282 { 283 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 284 285 /* 286 * Stop driving the CEC pin, the pull up will take over 287 * unless another CEC device is driving the pin low. 288 */ 289 writel(0, hdmi->base + SUN4I_HDMI_CEC); 290 } 291 292 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 293 .read = sun4i_hdmi_cec_pin_read, 294 .low = sun4i_hdmi_cec_pin_low, 295 .high = sun4i_hdmi_cec_pin_high, 296 }; 297 #endif 298 299 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 300 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 301 302 /* Only difference from sun5i is AMP is 4 instead of 6 */ 303 static const struct sun4i_hdmi_variant sun4i_variant = { 304 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 305 SUN4I_HDMI_PAD_CTRL0_CKEN | 306 SUN4I_HDMI_PAD_CTRL0_PWENG | 307 SUN4I_HDMI_PAD_CTRL0_PWEND | 308 SUN4I_HDMI_PAD_CTRL0_PWENC | 309 SUN4I_HDMI_PAD_CTRL0_LDODEN | 310 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 311 SUN4I_HDMI_PAD_CTRL0_BIASEN, 312 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 313 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 314 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 315 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 316 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 317 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 318 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 319 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 320 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 321 SUN4I_HDMI_PLL_CTRL_CS(7) | 322 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 323 SUN4I_HDMI_PLL_CTRL_S(7) | 324 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 325 SUN4I_HDMI_PLL_CTRL_SDIV2 | 326 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 327 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 328 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 329 SUN4I_HDMI_PLL_CTRL_BWS | 330 SUN4I_HDMI_PLL_CTRL_PLL_EN, 331 332 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 333 .ddc_clk_pre_divider = 2, 334 .ddc_clk_m_offset = 1, 335 336 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 337 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 338 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 339 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 340 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 341 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 342 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 343 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 344 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 345 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 346 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 347 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 348 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 349 350 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 351 .ddc_fifo_has_dir = true, 352 }; 353 354 static const struct sun4i_hdmi_variant sun5i_variant = { 355 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 356 SUN4I_HDMI_PAD_CTRL0_CKEN | 357 SUN4I_HDMI_PAD_CTRL0_PWENG | 358 SUN4I_HDMI_PAD_CTRL0_PWEND | 359 SUN4I_HDMI_PAD_CTRL0_PWENC | 360 SUN4I_HDMI_PAD_CTRL0_LDODEN | 361 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 362 SUN4I_HDMI_PAD_CTRL0_BIASEN, 363 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 364 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 365 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 366 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 367 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 368 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 369 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 370 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 371 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 372 SUN4I_HDMI_PLL_CTRL_CS(7) | 373 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 374 SUN4I_HDMI_PLL_CTRL_S(7) | 375 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 376 SUN4I_HDMI_PLL_CTRL_SDIV2 | 377 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 378 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 379 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 380 SUN4I_HDMI_PLL_CTRL_BWS | 381 SUN4I_HDMI_PLL_CTRL_PLL_EN, 382 383 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 384 .ddc_clk_pre_divider = 2, 385 .ddc_clk_m_offset = 1, 386 387 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 388 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 389 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 390 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 391 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 392 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 393 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 394 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 395 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 396 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 397 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 398 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 399 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 400 401 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 402 .ddc_fifo_has_dir = true, 403 }; 404 405 static const struct sun4i_hdmi_variant sun6i_variant = { 406 .has_ddc_parent_clk = true, 407 .has_reset_control = true, 408 .pad_ctrl0_init_val = 0xff | 409 SUN4I_HDMI_PAD_CTRL0_TXEN | 410 SUN4I_HDMI_PAD_CTRL0_CKEN | 411 SUN4I_HDMI_PAD_CTRL0_PWENG | 412 SUN4I_HDMI_PAD_CTRL0_PWEND | 413 SUN4I_HDMI_PAD_CTRL0_PWENC | 414 SUN4I_HDMI_PAD_CTRL0_LDODEN | 415 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 416 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 417 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 418 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 419 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 420 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 421 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 422 SUN4I_HDMI_PAD_CTRL1_PWSDT | 423 SUN4I_HDMI_PAD_CTRL1_PWSCK | 424 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 425 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 426 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 427 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 428 SUN4I_HDMI_PLL_CTRL_CS(3) | 429 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 430 SUN4I_HDMI_PLL_CTRL_S(4) | 431 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 432 SUN4I_HDMI_PLL_CTRL_SDIV2 | 433 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 434 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 435 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 436 SUN4I_HDMI_PLL_CTRL_PLL_EN, 437 438 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 439 .ddc_clk_pre_divider = 1, 440 .ddc_clk_m_offset = 2, 441 442 .tmds_clk_div_offset = 1, 443 444 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 445 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 446 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 447 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 448 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 449 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 450 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 451 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 452 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 453 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 454 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 455 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 456 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 457 458 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 459 .ddc_fifo_thres_incl = true, 460 }; 461 462 static const struct regmap_config sun4i_hdmi_regmap_config = { 463 .reg_bits = 32, 464 .val_bits = 32, 465 .reg_stride = 4, 466 .max_register = 0x580, 467 }; 468 469 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 470 void *data) 471 { 472 struct platform_device *pdev = to_platform_device(dev); 473 struct drm_device *drm = data; 474 struct sun4i_drv *drv = drm->dev_private; 475 struct sun4i_hdmi *hdmi; 476 struct resource *res; 477 u32 reg; 478 int ret; 479 480 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 481 if (!hdmi) 482 return -ENOMEM; 483 dev_set_drvdata(dev, hdmi); 484 hdmi->dev = dev; 485 hdmi->drv = drv; 486 487 hdmi->variant = of_device_get_match_data(dev); 488 if (!hdmi->variant) 489 return -EINVAL; 490 491 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 492 hdmi->base = devm_ioremap_resource(dev, res); 493 if (IS_ERR(hdmi->base)) { 494 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 495 return PTR_ERR(hdmi->base); 496 } 497 498 if (hdmi->variant->has_reset_control) { 499 hdmi->reset = devm_reset_control_get(dev, NULL); 500 if (IS_ERR(hdmi->reset)) { 501 dev_err(dev, "Couldn't get the HDMI reset control\n"); 502 return PTR_ERR(hdmi->reset); 503 } 504 505 ret = reset_control_deassert(hdmi->reset); 506 if (ret) { 507 dev_err(dev, "Couldn't deassert HDMI reset\n"); 508 return ret; 509 } 510 } 511 512 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 513 if (IS_ERR(hdmi->bus_clk)) { 514 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 515 ret = PTR_ERR(hdmi->bus_clk); 516 goto err_assert_reset; 517 } 518 clk_prepare_enable(hdmi->bus_clk); 519 520 hdmi->mod_clk = devm_clk_get(dev, "mod"); 521 if (IS_ERR(hdmi->mod_clk)) { 522 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 523 ret = PTR_ERR(hdmi->mod_clk); 524 goto err_disable_bus_clk; 525 } 526 clk_prepare_enable(hdmi->mod_clk); 527 528 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 529 if (IS_ERR(hdmi->pll0_clk)) { 530 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 531 ret = PTR_ERR(hdmi->pll0_clk); 532 goto err_disable_mod_clk; 533 } 534 535 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 536 if (IS_ERR(hdmi->pll1_clk)) { 537 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 538 ret = PTR_ERR(hdmi->pll1_clk); 539 goto err_disable_mod_clk; 540 } 541 542 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 543 &sun4i_hdmi_regmap_config); 544 if (IS_ERR(hdmi->regmap)) { 545 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 546 ret = PTR_ERR(hdmi->regmap); 547 goto err_disable_mod_clk; 548 } 549 550 ret = sun4i_tmds_create(hdmi); 551 if (ret) { 552 dev_err(dev, "Couldn't create the TMDS clock\n"); 553 goto err_disable_mod_clk; 554 } 555 556 if (hdmi->variant->has_ddc_parent_clk) { 557 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 558 if (IS_ERR(hdmi->ddc_parent_clk)) { 559 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 560 ret = PTR_ERR(hdmi->ddc_parent_clk); 561 goto err_disable_mod_clk; 562 } 563 } else { 564 hdmi->ddc_parent_clk = hdmi->tmds_clk; 565 } 566 567 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 568 569 writel(hdmi->variant->pad_ctrl0_init_val, 570 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 571 572 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 573 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 574 reg |= hdmi->variant->pll_ctrl_init_val; 575 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 576 577 ret = sun4i_hdmi_i2c_create(dev, hdmi); 578 if (ret) { 579 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 580 goto err_disable_mod_clk; 581 } 582 583 drm_encoder_helper_add(&hdmi->encoder, 584 &sun4i_hdmi_helper_funcs); 585 ret = drm_encoder_init(drm, 586 &hdmi->encoder, 587 &sun4i_hdmi_funcs, 588 DRM_MODE_ENCODER_TMDS, 589 NULL); 590 if (ret) { 591 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 592 goto err_del_i2c_adapter; 593 } 594 595 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 596 dev->of_node); 597 if (!hdmi->encoder.possible_crtcs) { 598 ret = -EPROBE_DEFER; 599 goto err_del_i2c_adapter; 600 } 601 602 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 603 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 604 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS | 605 CEC_CAP_PASSTHROUGH | CEC_CAP_RC); 606 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 607 if (ret < 0) 608 goto err_cleanup_connector; 609 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 610 hdmi->base + SUN4I_HDMI_CEC); 611 #endif 612 613 drm_connector_helper_add(&hdmi->connector, 614 &sun4i_hdmi_connector_helper_funcs); 615 ret = drm_connector_init(drm, &hdmi->connector, 616 &sun4i_hdmi_connector_funcs, 617 DRM_MODE_CONNECTOR_HDMIA); 618 if (ret) { 619 dev_err(dev, 620 "Couldn't initialise the HDMI connector\n"); 621 goto err_cleanup_connector; 622 } 623 624 /* There is no HPD interrupt, so we need to poll the controller */ 625 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 626 DRM_CONNECTOR_POLL_DISCONNECT; 627 628 ret = cec_register_adapter(hdmi->cec_adap, dev); 629 if (ret < 0) 630 goto err_cleanup_connector; 631 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 632 633 return 0; 634 635 err_cleanup_connector: 636 cec_delete_adapter(hdmi->cec_adap); 637 drm_encoder_cleanup(&hdmi->encoder); 638 err_del_i2c_adapter: 639 i2c_del_adapter(hdmi->i2c); 640 err_disable_mod_clk: 641 clk_disable_unprepare(hdmi->mod_clk); 642 err_disable_bus_clk: 643 clk_disable_unprepare(hdmi->bus_clk); 644 err_assert_reset: 645 reset_control_assert(hdmi->reset); 646 return ret; 647 } 648 649 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 650 void *data) 651 { 652 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 653 654 cec_unregister_adapter(hdmi->cec_adap); 655 drm_connector_cleanup(&hdmi->connector); 656 drm_encoder_cleanup(&hdmi->encoder); 657 i2c_del_adapter(hdmi->i2c); 658 clk_disable_unprepare(hdmi->mod_clk); 659 clk_disable_unprepare(hdmi->bus_clk); 660 } 661 662 static const struct component_ops sun4i_hdmi_ops = { 663 .bind = sun4i_hdmi_bind, 664 .unbind = sun4i_hdmi_unbind, 665 }; 666 667 static int sun4i_hdmi_probe(struct platform_device *pdev) 668 { 669 return component_add(&pdev->dev, &sun4i_hdmi_ops); 670 } 671 672 static int sun4i_hdmi_remove(struct platform_device *pdev) 673 { 674 component_del(&pdev->dev, &sun4i_hdmi_ops); 675 676 return 0; 677 } 678 679 static const struct of_device_id sun4i_hdmi_of_table[] = { 680 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 681 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 682 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 683 { } 684 }; 685 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 686 687 static struct platform_driver sun4i_hdmi_driver = { 688 .probe = sun4i_hdmi_probe, 689 .remove = sun4i_hdmi_remove, 690 .driver = { 691 .name = "sun4i-hdmi", 692 .of_match_table = sun4i_hdmi_of_table, 693 }, 694 }; 695 module_platform_driver(sun4i_hdmi_driver); 696 697 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 698 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 699 MODULE_LICENSE("GPL"); 700