1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/i2c.h> 11 #include <linux/iopoll.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/regmap.h> 17 #include <linux/reset.h> 18 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_edid.h> 21 #include <drm/drm_encoder.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_panel.h> 24 #include <drm/drm_print.h> 25 #include <drm/drm_probe_helper.h> 26 #include <drm/drm_simple_kms_helper.h> 27 28 #include "sun4i_backend.h" 29 #include "sun4i_crtc.h" 30 #include "sun4i_drv.h" 31 #include "sun4i_hdmi.h" 32 33 static inline struct sun4i_hdmi * 34 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) 35 { 36 return container_of(encoder, struct sun4i_hdmi, 37 encoder); 38 } 39 40 static inline struct sun4i_hdmi * 41 drm_connector_to_sun4i_hdmi(struct drm_connector *connector) 42 { 43 return container_of(connector, struct sun4i_hdmi, 44 connector); 45 } 46 47 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 48 struct drm_display_mode *mode) 49 { 50 struct hdmi_avi_infoframe frame; 51 u8 buffer[17]; 52 int i, ret; 53 54 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 55 &hdmi->connector, mode); 56 if (ret < 0) { 57 DRM_ERROR("Failed to get infoframes from mode\n"); 58 return ret; 59 } 60 61 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 62 if (ret < 0) { 63 DRM_ERROR("Failed to pack infoframes\n"); 64 return ret; 65 } 66 67 for (i = 0; i < sizeof(buffer); i++) 68 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 69 70 return 0; 71 } 72 73 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder, 74 struct drm_crtc_state *crtc_state, 75 struct drm_connector_state *conn_state) 76 { 77 struct drm_display_mode *mode = &crtc_state->mode; 78 79 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 80 return -EINVAL; 81 82 return 0; 83 } 84 85 static void sun4i_hdmi_disable(struct drm_encoder *encoder, 86 struct drm_atomic_state *state) 87 { 88 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 89 u32 val; 90 91 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 92 93 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 94 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 95 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 96 97 clk_disable_unprepare(hdmi->tmds_clk); 98 } 99 100 static void sun4i_hdmi_enable(struct drm_encoder *encoder, 101 struct drm_atomic_state *state) 102 { 103 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 104 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 105 struct drm_display_info *display = &hdmi->connector.display_info; 106 unsigned int x, y; 107 u32 val = 0; 108 109 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 110 111 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 112 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 113 114 /* Set input sync enable */ 115 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 116 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 117 118 /* 119 * Setup output pad (?) controls 120 * 121 * This is done here instead of at probe/bind time because 122 * the controller seems to toggle some of the bits on its own. 123 * 124 * We can't just initialize the register there, we need to 125 * protect the clock bits that have already been read out and 126 * cached by the clock framework. 127 */ 128 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 129 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 130 val |= hdmi->variant->pad_ctrl1_init_val; 131 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 132 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 133 134 /* Setup timing registers */ 135 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 136 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 137 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 138 139 x = mode->htotal - mode->hsync_start; 140 y = mode->vtotal - mode->vsync_start; 141 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 142 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 143 144 x = mode->hsync_start - mode->hdisplay; 145 y = mode->vsync_start - mode->vdisplay; 146 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 147 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 148 149 x = mode->hsync_end - mode->hsync_start; 150 y = mode->vsync_end - mode->vsync_start; 151 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 152 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 153 154 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 155 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 156 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 157 158 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 159 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 160 161 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 162 163 clk_prepare_enable(hdmi->tmds_clk); 164 165 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 166 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 167 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 168 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 169 170 val = SUN4I_HDMI_VID_CTRL_ENABLE; 171 if (display->is_hdmi) 172 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 173 174 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 175 } 176 177 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder, 178 const struct drm_display_mode *mode) 179 { 180 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 181 unsigned long rate = mode->clock * 1000; 182 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ 183 long rounded_rate; 184 185 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 186 if (rate > 165000000) 187 return MODE_CLOCK_HIGH; 188 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); 189 if (rounded_rate > 0 && 190 max_t(unsigned long, rounded_rate, rate) - 191 min_t(unsigned long, rounded_rate, rate) < diff) 192 return MODE_OK; 193 return MODE_NOCLOCK; 194 } 195 196 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 197 .atomic_check = sun4i_hdmi_atomic_check, 198 .atomic_disable = sun4i_hdmi_disable, 199 .atomic_enable = sun4i_hdmi_enable, 200 .mode_valid = sun4i_hdmi_mode_valid, 201 }; 202 203 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 204 { 205 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 206 struct edid *edid; 207 int ret; 208 209 edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c); 210 if (!edid) 211 return 0; 212 213 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 214 connector->display_info.is_hdmi ? "an HDMI" : "a DVI"); 215 216 drm_connector_update_edid_property(connector, edid); 217 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); 218 ret = drm_add_edid_modes(connector, edid); 219 kfree(edid); 220 221 return ret; 222 } 223 224 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 225 { 226 struct device_node *phandle, *remote; 227 struct i2c_adapter *ddc; 228 229 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 230 if (!remote) 231 return ERR_PTR(-EINVAL); 232 233 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 234 of_node_put(remote); 235 if (!phandle) 236 return ERR_PTR(-ENODEV); 237 238 ddc = of_get_i2c_adapter_by_node(phandle); 239 of_node_put(phandle); 240 if (!ddc) 241 return ERR_PTR(-EPROBE_DEFER); 242 243 return ddc; 244 } 245 246 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 247 .get_modes = sun4i_hdmi_get_modes, 248 }; 249 250 static enum drm_connector_status 251 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 252 { 253 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 254 unsigned long reg; 255 256 reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG); 257 if (!(reg & SUN4I_HDMI_HPD_HIGH)) { 258 cec_phys_addr_invalidate(hdmi->cec_adap); 259 return connector_status_disconnected; 260 } 261 262 return connector_status_connected; 263 } 264 265 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 266 .detect = sun4i_hdmi_connector_detect, 267 .fill_modes = drm_helper_probe_single_connector_modes, 268 .destroy = drm_connector_cleanup, 269 .reset = drm_atomic_helper_connector_reset, 270 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 271 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 272 }; 273 274 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 275 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 276 { 277 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 278 279 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 280 } 281 282 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 283 { 284 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 285 286 /* Start driving the CEC pin low */ 287 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 288 } 289 290 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 291 { 292 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 293 294 /* 295 * Stop driving the CEC pin, the pull up will take over 296 * unless another CEC device is driving the pin low. 297 */ 298 writel(0, hdmi->base + SUN4I_HDMI_CEC); 299 } 300 301 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 302 .read = sun4i_hdmi_cec_pin_read, 303 .low = sun4i_hdmi_cec_pin_low, 304 .high = sun4i_hdmi_cec_pin_high, 305 }; 306 #endif 307 308 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 309 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 310 311 /* Only difference from sun5i is AMP is 4 instead of 6 */ 312 static const struct sun4i_hdmi_variant sun4i_variant = { 313 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 314 SUN4I_HDMI_PAD_CTRL0_CKEN | 315 SUN4I_HDMI_PAD_CTRL0_PWENG | 316 SUN4I_HDMI_PAD_CTRL0_PWEND | 317 SUN4I_HDMI_PAD_CTRL0_PWENC | 318 SUN4I_HDMI_PAD_CTRL0_LDODEN | 319 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 320 SUN4I_HDMI_PAD_CTRL0_BIASEN, 321 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 322 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 323 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 324 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 325 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 326 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 327 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 328 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 329 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 330 SUN4I_HDMI_PLL_CTRL_CS(7) | 331 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 332 SUN4I_HDMI_PLL_CTRL_S(7) | 333 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 334 SUN4I_HDMI_PLL_CTRL_SDIV2 | 335 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 336 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 337 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 338 SUN4I_HDMI_PLL_CTRL_BWS | 339 SUN4I_HDMI_PLL_CTRL_PLL_EN, 340 341 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 342 .ddc_clk_pre_divider = 2, 343 .ddc_clk_m_offset = 1, 344 345 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 346 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 347 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 348 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 349 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 350 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 351 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 352 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 353 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 354 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 355 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 356 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 357 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 358 359 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 360 .ddc_fifo_has_dir = true, 361 }; 362 363 static const struct sun4i_hdmi_variant sun5i_variant = { 364 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 365 SUN4I_HDMI_PAD_CTRL0_CKEN | 366 SUN4I_HDMI_PAD_CTRL0_PWENG | 367 SUN4I_HDMI_PAD_CTRL0_PWEND | 368 SUN4I_HDMI_PAD_CTRL0_PWENC | 369 SUN4I_HDMI_PAD_CTRL0_LDODEN | 370 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 371 SUN4I_HDMI_PAD_CTRL0_BIASEN, 372 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 373 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 374 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 375 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 376 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 377 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 378 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 379 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 380 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 381 SUN4I_HDMI_PLL_CTRL_CS(7) | 382 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 383 SUN4I_HDMI_PLL_CTRL_S(7) | 384 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 385 SUN4I_HDMI_PLL_CTRL_SDIV2 | 386 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 387 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 388 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 389 SUN4I_HDMI_PLL_CTRL_BWS | 390 SUN4I_HDMI_PLL_CTRL_PLL_EN, 391 392 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 393 .ddc_clk_pre_divider = 2, 394 .ddc_clk_m_offset = 1, 395 396 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 397 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 398 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 399 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 400 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 401 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 402 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 403 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 404 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 405 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 406 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 407 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 408 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 409 410 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 411 .ddc_fifo_has_dir = true, 412 }; 413 414 static const struct sun4i_hdmi_variant sun6i_variant = { 415 .has_ddc_parent_clk = true, 416 .has_reset_control = true, 417 .pad_ctrl0_init_val = 0xff | 418 SUN4I_HDMI_PAD_CTRL0_TXEN | 419 SUN4I_HDMI_PAD_CTRL0_CKEN | 420 SUN4I_HDMI_PAD_CTRL0_PWENG | 421 SUN4I_HDMI_PAD_CTRL0_PWEND | 422 SUN4I_HDMI_PAD_CTRL0_PWENC | 423 SUN4I_HDMI_PAD_CTRL0_LDODEN | 424 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 425 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 426 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 427 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 428 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 429 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 430 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 431 SUN4I_HDMI_PAD_CTRL1_PWSDT | 432 SUN4I_HDMI_PAD_CTRL1_PWSCK | 433 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 434 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 435 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 436 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 437 SUN4I_HDMI_PLL_CTRL_CS(3) | 438 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 439 SUN4I_HDMI_PLL_CTRL_S(4) | 440 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 441 SUN4I_HDMI_PLL_CTRL_SDIV2 | 442 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 443 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 444 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 445 SUN4I_HDMI_PLL_CTRL_PLL_EN, 446 447 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 448 .ddc_clk_pre_divider = 1, 449 .ddc_clk_m_offset = 2, 450 451 .tmds_clk_div_offset = 1, 452 453 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 454 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 455 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 456 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 457 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 458 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 459 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 460 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 461 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 462 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 463 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 464 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 465 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 466 467 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 468 .ddc_fifo_thres_incl = true, 469 }; 470 471 static const struct regmap_config sun4i_hdmi_regmap_config = { 472 .reg_bits = 32, 473 .val_bits = 32, 474 .reg_stride = 4, 475 .max_register = 0x580, 476 }; 477 478 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 479 void *data) 480 { 481 struct platform_device *pdev = to_platform_device(dev); 482 struct drm_device *drm = data; 483 struct cec_connector_info conn_info; 484 struct sun4i_drv *drv = drm->dev_private; 485 struct sun4i_hdmi *hdmi; 486 u32 reg; 487 int ret; 488 489 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 490 if (!hdmi) 491 return -ENOMEM; 492 dev_set_drvdata(dev, hdmi); 493 hdmi->dev = dev; 494 hdmi->drv = drv; 495 496 hdmi->variant = of_device_get_match_data(dev); 497 if (!hdmi->variant) 498 return -EINVAL; 499 500 hdmi->base = devm_platform_ioremap_resource(pdev, 0); 501 if (IS_ERR(hdmi->base)) { 502 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 503 return PTR_ERR(hdmi->base); 504 } 505 506 if (hdmi->variant->has_reset_control) { 507 hdmi->reset = devm_reset_control_get(dev, NULL); 508 if (IS_ERR(hdmi->reset)) { 509 dev_err(dev, "Couldn't get the HDMI reset control\n"); 510 return PTR_ERR(hdmi->reset); 511 } 512 513 ret = reset_control_deassert(hdmi->reset); 514 if (ret) { 515 dev_err(dev, "Couldn't deassert HDMI reset\n"); 516 return ret; 517 } 518 } 519 520 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 521 if (IS_ERR(hdmi->bus_clk)) { 522 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 523 ret = PTR_ERR(hdmi->bus_clk); 524 goto err_assert_reset; 525 } 526 clk_prepare_enable(hdmi->bus_clk); 527 528 hdmi->mod_clk = devm_clk_get(dev, "mod"); 529 if (IS_ERR(hdmi->mod_clk)) { 530 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 531 ret = PTR_ERR(hdmi->mod_clk); 532 goto err_disable_bus_clk; 533 } 534 clk_prepare_enable(hdmi->mod_clk); 535 536 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 537 if (IS_ERR(hdmi->pll0_clk)) { 538 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 539 ret = PTR_ERR(hdmi->pll0_clk); 540 goto err_disable_mod_clk; 541 } 542 543 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 544 if (IS_ERR(hdmi->pll1_clk)) { 545 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 546 ret = PTR_ERR(hdmi->pll1_clk); 547 goto err_disable_mod_clk; 548 } 549 550 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 551 &sun4i_hdmi_regmap_config); 552 if (IS_ERR(hdmi->regmap)) { 553 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 554 ret = PTR_ERR(hdmi->regmap); 555 goto err_disable_mod_clk; 556 } 557 558 ret = sun4i_tmds_create(hdmi); 559 if (ret) { 560 dev_err(dev, "Couldn't create the TMDS clock\n"); 561 goto err_disable_mod_clk; 562 } 563 564 if (hdmi->variant->has_ddc_parent_clk) { 565 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 566 if (IS_ERR(hdmi->ddc_parent_clk)) { 567 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 568 ret = PTR_ERR(hdmi->ddc_parent_clk); 569 goto err_disable_mod_clk; 570 } 571 } else { 572 hdmi->ddc_parent_clk = hdmi->tmds_clk; 573 } 574 575 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 576 577 writel(hdmi->variant->pad_ctrl0_init_val, 578 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 579 580 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 581 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 582 reg |= hdmi->variant->pll_ctrl_init_val; 583 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 584 585 ret = sun4i_hdmi_i2c_create(dev, hdmi); 586 if (ret) { 587 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 588 goto err_disable_mod_clk; 589 } 590 591 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 592 if (IS_ERR(hdmi->ddc_i2c)) { 593 ret = PTR_ERR(hdmi->ddc_i2c); 594 if (ret == -ENODEV) 595 hdmi->ddc_i2c = NULL; 596 else 597 goto err_del_i2c_adapter; 598 } 599 600 drm_encoder_helper_add(&hdmi->encoder, 601 &sun4i_hdmi_helper_funcs); 602 ret = drm_simple_encoder_init(drm, &hdmi->encoder, 603 DRM_MODE_ENCODER_TMDS); 604 if (ret) { 605 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 606 goto err_put_ddc_i2c; 607 } 608 609 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 610 dev->of_node); 611 if (!hdmi->encoder.possible_crtcs) { 612 ret = -EPROBE_DEFER; 613 goto err_put_ddc_i2c; 614 } 615 616 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 617 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 618 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 619 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 620 if (ret < 0) 621 goto err_cleanup_connector; 622 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 623 hdmi->base + SUN4I_HDMI_CEC); 624 #endif 625 626 drm_connector_helper_add(&hdmi->connector, 627 &sun4i_hdmi_connector_helper_funcs); 628 ret = drm_connector_init_with_ddc(drm, &hdmi->connector, 629 &sun4i_hdmi_connector_funcs, 630 DRM_MODE_CONNECTOR_HDMIA, 631 hdmi->ddc_i2c); 632 if (ret) { 633 dev_err(dev, 634 "Couldn't initialise the HDMI connector\n"); 635 goto err_cleanup_connector; 636 } 637 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 638 cec_s_conn_info(hdmi->cec_adap, &conn_info); 639 640 /* There is no HPD interrupt, so we need to poll the controller */ 641 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 642 DRM_CONNECTOR_POLL_DISCONNECT; 643 644 ret = cec_register_adapter(hdmi->cec_adap, dev); 645 if (ret < 0) 646 goto err_cleanup_connector; 647 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 648 649 return 0; 650 651 err_cleanup_connector: 652 cec_delete_adapter(hdmi->cec_adap); 653 drm_encoder_cleanup(&hdmi->encoder); 654 err_put_ddc_i2c: 655 i2c_put_adapter(hdmi->ddc_i2c); 656 err_del_i2c_adapter: 657 i2c_del_adapter(hdmi->i2c); 658 err_disable_mod_clk: 659 clk_disable_unprepare(hdmi->mod_clk); 660 err_disable_bus_clk: 661 clk_disable_unprepare(hdmi->bus_clk); 662 err_assert_reset: 663 reset_control_assert(hdmi->reset); 664 return ret; 665 } 666 667 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 668 void *data) 669 { 670 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 671 672 cec_unregister_adapter(hdmi->cec_adap); 673 i2c_del_adapter(hdmi->i2c); 674 i2c_put_adapter(hdmi->ddc_i2c); 675 clk_disable_unprepare(hdmi->mod_clk); 676 clk_disable_unprepare(hdmi->bus_clk); 677 } 678 679 static const struct component_ops sun4i_hdmi_ops = { 680 .bind = sun4i_hdmi_bind, 681 .unbind = sun4i_hdmi_unbind, 682 }; 683 684 static int sun4i_hdmi_probe(struct platform_device *pdev) 685 { 686 return component_add(&pdev->dev, &sun4i_hdmi_ops); 687 } 688 689 static void sun4i_hdmi_remove(struct platform_device *pdev) 690 { 691 component_del(&pdev->dev, &sun4i_hdmi_ops); 692 } 693 694 static const struct of_device_id sun4i_hdmi_of_table[] = { 695 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 696 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 697 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 698 { } 699 }; 700 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 701 702 static struct platform_driver sun4i_hdmi_driver = { 703 .probe = sun4i_hdmi_probe, 704 .remove_new = sun4i_hdmi_remove, 705 .driver = { 706 .name = "sun4i-hdmi", 707 .of_match_table = sun4i_hdmi_of_table, 708 }, 709 }; 710 module_platform_driver(sun4i_hdmi_driver); 711 712 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 713 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 714 MODULE_LICENSE("GPL"); 715