1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #include <drm/drmP.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_probe_helper.h> 15 #include <drm/drm_edid.h> 16 #include <drm/drm_encoder.h> 17 #include <drm/drm_of.h> 18 #include <drm/drm_panel.h> 19 20 #include <linux/clk.h> 21 #include <linux/component.h> 22 #include <linux/iopoll.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/reset.h> 28 29 #include "sun4i_backend.h" 30 #include "sun4i_crtc.h" 31 #include "sun4i_drv.h" 32 #include "sun4i_hdmi.h" 33 34 static inline struct sun4i_hdmi * 35 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) 36 { 37 return container_of(encoder, struct sun4i_hdmi, 38 encoder); 39 } 40 41 static inline struct sun4i_hdmi * 42 drm_connector_to_sun4i_hdmi(struct drm_connector *connector) 43 { 44 return container_of(connector, struct sun4i_hdmi, 45 connector); 46 } 47 48 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 49 struct drm_display_mode *mode) 50 { 51 struct hdmi_avi_infoframe frame; 52 u8 buffer[17]; 53 int i, ret; 54 55 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 56 &hdmi->connector, mode); 57 if (ret < 0) { 58 DRM_ERROR("Failed to get infoframes from mode\n"); 59 return ret; 60 } 61 62 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 63 if (ret < 0) { 64 DRM_ERROR("Failed to pack infoframes\n"); 65 return ret; 66 } 67 68 for (i = 0; i < sizeof(buffer); i++) 69 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 70 71 return 0; 72 } 73 74 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder, 75 struct drm_crtc_state *crtc_state, 76 struct drm_connector_state *conn_state) 77 { 78 struct drm_display_mode *mode = &crtc_state->mode; 79 80 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 static void sun4i_hdmi_disable(struct drm_encoder *encoder) 87 { 88 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 89 u32 val; 90 91 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 92 93 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 94 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 95 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 96 97 clk_disable_unprepare(hdmi->tmds_clk); 98 } 99 100 static void sun4i_hdmi_enable(struct drm_encoder *encoder) 101 { 102 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 103 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 104 u32 val = 0; 105 106 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 107 108 clk_prepare_enable(hdmi->tmds_clk); 109 110 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 111 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 112 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 113 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 114 115 val = SUN4I_HDMI_VID_CTRL_ENABLE; 116 if (hdmi->hdmi_monitor) 117 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 118 119 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 120 } 121 122 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder, 123 struct drm_display_mode *mode, 124 struct drm_display_mode *adjusted_mode) 125 { 126 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 127 unsigned int x, y; 128 u32 val; 129 130 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 131 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 132 133 /* Set input sync enable */ 134 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 135 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 136 137 /* 138 * Setup output pad (?) controls 139 * 140 * This is done here instead of at probe/bind time because 141 * the controller seems to toggle some of the bits on its own. 142 * 143 * We can't just initialize the register there, we need to 144 * protect the clock bits that have already been read out and 145 * cached by the clock framework. 146 */ 147 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 148 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 149 val |= hdmi->variant->pad_ctrl1_init_val; 150 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 151 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 152 153 /* Setup timing registers */ 154 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 155 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 156 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 157 158 x = mode->htotal - mode->hsync_start; 159 y = mode->vtotal - mode->vsync_start; 160 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 161 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 162 163 x = mode->hsync_start - mode->hdisplay; 164 y = mode->vsync_start - mode->vdisplay; 165 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 166 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 167 168 x = mode->hsync_end - mode->hsync_start; 169 y = mode->vsync_end - mode->vsync_start; 170 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 171 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 172 173 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 174 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 175 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 176 177 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 178 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 179 180 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 181 } 182 183 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder, 184 const struct drm_display_mode *mode) 185 { 186 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 187 unsigned long rate = mode->clock * 1000; 188 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ 189 long rounded_rate; 190 191 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 192 if (rate > 165000000) 193 return MODE_CLOCK_HIGH; 194 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); 195 if (rounded_rate > 0 && 196 max_t(unsigned long, rounded_rate, rate) - 197 min_t(unsigned long, rounded_rate, rate) < diff) 198 return MODE_OK; 199 return MODE_NOCLOCK; 200 } 201 202 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 203 .atomic_check = sun4i_hdmi_atomic_check, 204 .disable = sun4i_hdmi_disable, 205 .enable = sun4i_hdmi_enable, 206 .mode_set = sun4i_hdmi_mode_set, 207 .mode_valid = sun4i_hdmi_mode_valid, 208 }; 209 210 static const struct drm_encoder_funcs sun4i_hdmi_funcs = { 211 .destroy = drm_encoder_cleanup, 212 }; 213 214 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 215 { 216 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 217 struct edid *edid; 218 int ret; 219 220 edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c); 221 if (!edid) 222 return 0; 223 224 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid); 225 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 226 hdmi->hdmi_monitor ? "an HDMI" : "a DVI"); 227 228 drm_connector_update_edid_property(connector, edid); 229 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); 230 ret = drm_add_edid_modes(connector, edid); 231 kfree(edid); 232 233 return ret; 234 } 235 236 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 237 { 238 struct device_node *phandle, *remote; 239 struct i2c_adapter *ddc; 240 241 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 242 if (!remote) 243 return ERR_PTR(-EINVAL); 244 245 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 246 of_node_put(remote); 247 if (!phandle) 248 return ERR_PTR(-ENODEV); 249 250 ddc = of_get_i2c_adapter_by_node(phandle); 251 of_node_put(phandle); 252 if (!ddc) 253 return ERR_PTR(-EPROBE_DEFER); 254 255 return ddc; 256 } 257 258 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 259 .get_modes = sun4i_hdmi_get_modes, 260 }; 261 262 static enum drm_connector_status 263 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 264 { 265 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 266 unsigned long reg; 267 268 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, 269 reg & SUN4I_HDMI_HPD_HIGH, 270 0, 500000)) { 271 cec_phys_addr_invalidate(hdmi->cec_adap); 272 return connector_status_disconnected; 273 } 274 275 return connector_status_connected; 276 } 277 278 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 279 .detect = sun4i_hdmi_connector_detect, 280 .fill_modes = drm_helper_probe_single_connector_modes, 281 .destroy = drm_connector_cleanup, 282 .reset = drm_atomic_helper_connector_reset, 283 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 284 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 285 }; 286 287 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 288 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 289 { 290 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 291 292 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 293 } 294 295 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 296 { 297 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 298 299 /* Start driving the CEC pin low */ 300 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 301 } 302 303 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 304 { 305 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 306 307 /* 308 * Stop driving the CEC pin, the pull up will take over 309 * unless another CEC device is driving the pin low. 310 */ 311 writel(0, hdmi->base + SUN4I_HDMI_CEC); 312 } 313 314 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 315 .read = sun4i_hdmi_cec_pin_read, 316 .low = sun4i_hdmi_cec_pin_low, 317 .high = sun4i_hdmi_cec_pin_high, 318 }; 319 #endif 320 321 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 322 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 323 324 /* Only difference from sun5i is AMP is 4 instead of 6 */ 325 static const struct sun4i_hdmi_variant sun4i_variant = { 326 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 327 SUN4I_HDMI_PAD_CTRL0_CKEN | 328 SUN4I_HDMI_PAD_CTRL0_PWENG | 329 SUN4I_HDMI_PAD_CTRL0_PWEND | 330 SUN4I_HDMI_PAD_CTRL0_PWENC | 331 SUN4I_HDMI_PAD_CTRL0_LDODEN | 332 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 333 SUN4I_HDMI_PAD_CTRL0_BIASEN, 334 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 335 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 336 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 337 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 338 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 339 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 340 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 341 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 342 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 343 SUN4I_HDMI_PLL_CTRL_CS(7) | 344 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 345 SUN4I_HDMI_PLL_CTRL_S(7) | 346 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 347 SUN4I_HDMI_PLL_CTRL_SDIV2 | 348 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 349 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 350 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 351 SUN4I_HDMI_PLL_CTRL_BWS | 352 SUN4I_HDMI_PLL_CTRL_PLL_EN, 353 354 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 355 .ddc_clk_pre_divider = 2, 356 .ddc_clk_m_offset = 1, 357 358 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 359 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 360 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 361 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 362 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 363 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 364 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 365 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 366 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 367 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 368 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 369 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 370 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 371 372 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 373 .ddc_fifo_has_dir = true, 374 }; 375 376 static const struct sun4i_hdmi_variant sun5i_variant = { 377 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 378 SUN4I_HDMI_PAD_CTRL0_CKEN | 379 SUN4I_HDMI_PAD_CTRL0_PWENG | 380 SUN4I_HDMI_PAD_CTRL0_PWEND | 381 SUN4I_HDMI_PAD_CTRL0_PWENC | 382 SUN4I_HDMI_PAD_CTRL0_LDODEN | 383 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 384 SUN4I_HDMI_PAD_CTRL0_BIASEN, 385 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 386 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 387 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 388 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 389 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 390 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 391 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 392 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 393 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 394 SUN4I_HDMI_PLL_CTRL_CS(7) | 395 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 396 SUN4I_HDMI_PLL_CTRL_S(7) | 397 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 398 SUN4I_HDMI_PLL_CTRL_SDIV2 | 399 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 400 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 401 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 402 SUN4I_HDMI_PLL_CTRL_BWS | 403 SUN4I_HDMI_PLL_CTRL_PLL_EN, 404 405 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 406 .ddc_clk_pre_divider = 2, 407 .ddc_clk_m_offset = 1, 408 409 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 410 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 411 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 412 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 413 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 414 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 415 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 416 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 417 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 418 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 419 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 420 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 421 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 422 423 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 424 .ddc_fifo_has_dir = true, 425 }; 426 427 static const struct sun4i_hdmi_variant sun6i_variant = { 428 .has_ddc_parent_clk = true, 429 .has_reset_control = true, 430 .pad_ctrl0_init_val = 0xff | 431 SUN4I_HDMI_PAD_CTRL0_TXEN | 432 SUN4I_HDMI_PAD_CTRL0_CKEN | 433 SUN4I_HDMI_PAD_CTRL0_PWENG | 434 SUN4I_HDMI_PAD_CTRL0_PWEND | 435 SUN4I_HDMI_PAD_CTRL0_PWENC | 436 SUN4I_HDMI_PAD_CTRL0_LDODEN | 437 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 438 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 439 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 440 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 441 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 442 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 443 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 444 SUN4I_HDMI_PAD_CTRL1_PWSDT | 445 SUN4I_HDMI_PAD_CTRL1_PWSCK | 446 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 447 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 448 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 449 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 450 SUN4I_HDMI_PLL_CTRL_CS(3) | 451 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 452 SUN4I_HDMI_PLL_CTRL_S(4) | 453 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 454 SUN4I_HDMI_PLL_CTRL_SDIV2 | 455 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 456 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 457 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 458 SUN4I_HDMI_PLL_CTRL_PLL_EN, 459 460 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 461 .ddc_clk_pre_divider = 1, 462 .ddc_clk_m_offset = 2, 463 464 .tmds_clk_div_offset = 1, 465 466 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 467 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 468 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 469 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 470 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 471 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 472 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 473 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 474 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 475 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 476 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 477 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 478 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 479 480 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 481 .ddc_fifo_thres_incl = true, 482 }; 483 484 static const struct regmap_config sun4i_hdmi_regmap_config = { 485 .reg_bits = 32, 486 .val_bits = 32, 487 .reg_stride = 4, 488 .max_register = 0x580, 489 }; 490 491 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 492 void *data) 493 { 494 struct platform_device *pdev = to_platform_device(dev); 495 struct drm_device *drm = data; 496 struct sun4i_drv *drv = drm->dev_private; 497 struct sun4i_hdmi *hdmi; 498 struct resource *res; 499 u32 reg; 500 int ret; 501 502 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 503 if (!hdmi) 504 return -ENOMEM; 505 dev_set_drvdata(dev, hdmi); 506 hdmi->dev = dev; 507 hdmi->drv = drv; 508 509 hdmi->variant = of_device_get_match_data(dev); 510 if (!hdmi->variant) 511 return -EINVAL; 512 513 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 514 hdmi->base = devm_ioremap_resource(dev, res); 515 if (IS_ERR(hdmi->base)) { 516 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 517 return PTR_ERR(hdmi->base); 518 } 519 520 if (hdmi->variant->has_reset_control) { 521 hdmi->reset = devm_reset_control_get(dev, NULL); 522 if (IS_ERR(hdmi->reset)) { 523 dev_err(dev, "Couldn't get the HDMI reset control\n"); 524 return PTR_ERR(hdmi->reset); 525 } 526 527 ret = reset_control_deassert(hdmi->reset); 528 if (ret) { 529 dev_err(dev, "Couldn't deassert HDMI reset\n"); 530 return ret; 531 } 532 } 533 534 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 535 if (IS_ERR(hdmi->bus_clk)) { 536 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 537 ret = PTR_ERR(hdmi->bus_clk); 538 goto err_assert_reset; 539 } 540 clk_prepare_enable(hdmi->bus_clk); 541 542 hdmi->mod_clk = devm_clk_get(dev, "mod"); 543 if (IS_ERR(hdmi->mod_clk)) { 544 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 545 ret = PTR_ERR(hdmi->mod_clk); 546 goto err_disable_bus_clk; 547 } 548 clk_prepare_enable(hdmi->mod_clk); 549 550 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 551 if (IS_ERR(hdmi->pll0_clk)) { 552 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 553 ret = PTR_ERR(hdmi->pll0_clk); 554 goto err_disable_mod_clk; 555 } 556 557 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 558 if (IS_ERR(hdmi->pll1_clk)) { 559 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 560 ret = PTR_ERR(hdmi->pll1_clk); 561 goto err_disable_mod_clk; 562 } 563 564 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 565 &sun4i_hdmi_regmap_config); 566 if (IS_ERR(hdmi->regmap)) { 567 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 568 ret = PTR_ERR(hdmi->regmap); 569 goto err_disable_mod_clk; 570 } 571 572 ret = sun4i_tmds_create(hdmi); 573 if (ret) { 574 dev_err(dev, "Couldn't create the TMDS clock\n"); 575 goto err_disable_mod_clk; 576 } 577 578 if (hdmi->variant->has_ddc_parent_clk) { 579 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 580 if (IS_ERR(hdmi->ddc_parent_clk)) { 581 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 582 ret = PTR_ERR(hdmi->ddc_parent_clk); 583 goto err_disable_mod_clk; 584 } 585 } else { 586 hdmi->ddc_parent_clk = hdmi->tmds_clk; 587 } 588 589 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 590 591 writel(hdmi->variant->pad_ctrl0_init_val, 592 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 593 594 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 595 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 596 reg |= hdmi->variant->pll_ctrl_init_val; 597 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 598 599 ret = sun4i_hdmi_i2c_create(dev, hdmi); 600 if (ret) { 601 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 602 goto err_disable_mod_clk; 603 } 604 605 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 606 if (IS_ERR(hdmi->ddc_i2c)) { 607 ret = PTR_ERR(hdmi->ddc_i2c); 608 if (ret == -ENODEV) 609 hdmi->ddc_i2c = NULL; 610 else 611 goto err_del_i2c_adapter; 612 } 613 614 drm_encoder_helper_add(&hdmi->encoder, 615 &sun4i_hdmi_helper_funcs); 616 ret = drm_encoder_init(drm, 617 &hdmi->encoder, 618 &sun4i_hdmi_funcs, 619 DRM_MODE_ENCODER_TMDS, 620 NULL); 621 if (ret) { 622 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 623 goto err_put_ddc_i2c; 624 } 625 626 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 627 dev->of_node); 628 if (!hdmi->encoder.possible_crtcs) { 629 ret = -EPROBE_DEFER; 630 goto err_put_ddc_i2c; 631 } 632 633 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 634 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 635 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS | 636 CEC_CAP_PASSTHROUGH | CEC_CAP_RC); 637 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 638 if (ret < 0) 639 goto err_cleanup_connector; 640 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 641 hdmi->base + SUN4I_HDMI_CEC); 642 #endif 643 644 drm_connector_helper_add(&hdmi->connector, 645 &sun4i_hdmi_connector_helper_funcs); 646 ret = drm_connector_init(drm, &hdmi->connector, 647 &sun4i_hdmi_connector_funcs, 648 DRM_MODE_CONNECTOR_HDMIA); 649 if (ret) { 650 dev_err(dev, 651 "Couldn't initialise the HDMI connector\n"); 652 goto err_cleanup_connector; 653 } 654 655 /* There is no HPD interrupt, so we need to poll the controller */ 656 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 657 DRM_CONNECTOR_POLL_DISCONNECT; 658 659 ret = cec_register_adapter(hdmi->cec_adap, dev); 660 if (ret < 0) 661 goto err_cleanup_connector; 662 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 663 664 return 0; 665 666 err_cleanup_connector: 667 cec_delete_adapter(hdmi->cec_adap); 668 drm_encoder_cleanup(&hdmi->encoder); 669 err_put_ddc_i2c: 670 i2c_put_adapter(hdmi->ddc_i2c); 671 err_del_i2c_adapter: 672 i2c_del_adapter(hdmi->i2c); 673 err_disable_mod_clk: 674 clk_disable_unprepare(hdmi->mod_clk); 675 err_disable_bus_clk: 676 clk_disable_unprepare(hdmi->bus_clk); 677 err_assert_reset: 678 reset_control_assert(hdmi->reset); 679 return ret; 680 } 681 682 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 683 void *data) 684 { 685 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 686 687 cec_unregister_adapter(hdmi->cec_adap); 688 drm_connector_cleanup(&hdmi->connector); 689 drm_encoder_cleanup(&hdmi->encoder); 690 i2c_del_adapter(hdmi->i2c); 691 i2c_put_adapter(hdmi->ddc_i2c); 692 clk_disable_unprepare(hdmi->mod_clk); 693 clk_disable_unprepare(hdmi->bus_clk); 694 } 695 696 static const struct component_ops sun4i_hdmi_ops = { 697 .bind = sun4i_hdmi_bind, 698 .unbind = sun4i_hdmi_unbind, 699 }; 700 701 static int sun4i_hdmi_probe(struct platform_device *pdev) 702 { 703 return component_add(&pdev->dev, &sun4i_hdmi_ops); 704 } 705 706 static int sun4i_hdmi_remove(struct platform_device *pdev) 707 { 708 component_del(&pdev->dev, &sun4i_hdmi_ops); 709 710 return 0; 711 } 712 713 static const struct of_device_id sun4i_hdmi_of_table[] = { 714 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 715 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 716 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 717 { } 718 }; 719 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 720 721 static struct platform_driver sun4i_hdmi_driver = { 722 .probe = sun4i_hdmi_probe, 723 .remove = sun4i_hdmi_remove, 724 .driver = { 725 .name = "sun4i-hdmi", 726 .of_match_table = sun4i_hdmi_of_table, 727 }, 728 }; 729 module_platform_driver(sun4i_hdmi_driver); 730 731 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 732 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 733 MODULE_LICENSE("GPL"); 734