1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 Maxime Ripard 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/component.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 #include <linux/of_device.h> 13 #include <linux/platform_device.h> 14 #include <linux/pm_runtime.h> 15 #include <linux/regmap.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_edid.h> 20 #include <drm/drm_encoder.h> 21 #include <drm/drm_of.h> 22 #include <drm/drm_panel.h> 23 #include <drm/drm_print.h> 24 #include <drm/drm_probe_helper.h> 25 26 #include "sun4i_backend.h" 27 #include "sun4i_crtc.h" 28 #include "sun4i_drv.h" 29 #include "sun4i_hdmi.h" 30 31 static inline struct sun4i_hdmi * 32 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) 33 { 34 return container_of(encoder, struct sun4i_hdmi, 35 encoder); 36 } 37 38 static inline struct sun4i_hdmi * 39 drm_connector_to_sun4i_hdmi(struct drm_connector *connector) 40 { 41 return container_of(connector, struct sun4i_hdmi, 42 connector); 43 } 44 45 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 46 struct drm_display_mode *mode) 47 { 48 struct hdmi_avi_infoframe frame; 49 u8 buffer[17]; 50 int i, ret; 51 52 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 53 &hdmi->connector, mode); 54 if (ret < 0) { 55 DRM_ERROR("Failed to get infoframes from mode\n"); 56 return ret; 57 } 58 59 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 60 if (ret < 0) { 61 DRM_ERROR("Failed to pack infoframes\n"); 62 return ret; 63 } 64 65 for (i = 0; i < sizeof(buffer); i++) 66 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 67 68 return 0; 69 } 70 71 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder, 72 struct drm_crtc_state *crtc_state, 73 struct drm_connector_state *conn_state) 74 { 75 struct drm_display_mode *mode = &crtc_state->mode; 76 77 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 78 return -EINVAL; 79 80 return 0; 81 } 82 83 static void sun4i_hdmi_disable(struct drm_encoder *encoder) 84 { 85 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 86 u32 val; 87 88 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 89 90 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 91 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 92 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 93 94 clk_disable_unprepare(hdmi->tmds_clk); 95 } 96 97 static void sun4i_hdmi_enable(struct drm_encoder *encoder) 98 { 99 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 100 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 101 u32 val = 0; 102 103 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 104 105 clk_prepare_enable(hdmi->tmds_clk); 106 107 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 108 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 109 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 110 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 111 112 val = SUN4I_HDMI_VID_CTRL_ENABLE; 113 if (hdmi->hdmi_monitor) 114 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 115 116 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 117 } 118 119 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder, 120 struct drm_display_mode *mode, 121 struct drm_display_mode *adjusted_mode) 122 { 123 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 124 unsigned int x, y; 125 u32 val; 126 127 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 128 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 129 130 /* Set input sync enable */ 131 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 132 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 133 134 /* 135 * Setup output pad (?) controls 136 * 137 * This is done here instead of at probe/bind time because 138 * the controller seems to toggle some of the bits on its own. 139 * 140 * We can't just initialize the register there, we need to 141 * protect the clock bits that have already been read out and 142 * cached by the clock framework. 143 */ 144 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 145 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 146 val |= hdmi->variant->pad_ctrl1_init_val; 147 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 148 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 149 150 /* Setup timing registers */ 151 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 152 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 153 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 154 155 x = mode->htotal - mode->hsync_start; 156 y = mode->vtotal - mode->vsync_start; 157 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 158 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 159 160 x = mode->hsync_start - mode->hdisplay; 161 y = mode->vsync_start - mode->vdisplay; 162 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 163 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 164 165 x = mode->hsync_end - mode->hsync_start; 166 y = mode->vsync_end - mode->vsync_start; 167 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 168 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 169 170 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 171 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 172 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 173 174 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 175 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 176 177 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 178 } 179 180 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder, 181 const struct drm_display_mode *mode) 182 { 183 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 184 unsigned long rate = mode->clock * 1000; 185 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ 186 long rounded_rate; 187 188 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 189 if (rate > 165000000) 190 return MODE_CLOCK_HIGH; 191 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); 192 if (rounded_rate > 0 && 193 max_t(unsigned long, rounded_rate, rate) - 194 min_t(unsigned long, rounded_rate, rate) < diff) 195 return MODE_OK; 196 return MODE_NOCLOCK; 197 } 198 199 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 200 .atomic_check = sun4i_hdmi_atomic_check, 201 .disable = sun4i_hdmi_disable, 202 .enable = sun4i_hdmi_enable, 203 .mode_set = sun4i_hdmi_mode_set, 204 .mode_valid = sun4i_hdmi_mode_valid, 205 }; 206 207 static const struct drm_encoder_funcs sun4i_hdmi_funcs = { 208 .destroy = drm_encoder_cleanup, 209 }; 210 211 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 212 { 213 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 214 struct edid *edid; 215 int ret; 216 217 edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c); 218 if (!edid) 219 return 0; 220 221 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid); 222 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 223 hdmi->hdmi_monitor ? "an HDMI" : "a DVI"); 224 225 drm_connector_update_edid_property(connector, edid); 226 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); 227 ret = drm_add_edid_modes(connector, edid); 228 kfree(edid); 229 230 return ret; 231 } 232 233 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev) 234 { 235 struct device_node *phandle, *remote; 236 struct i2c_adapter *ddc; 237 238 remote = of_graph_get_remote_node(dev->of_node, 1, -1); 239 if (!remote) 240 return ERR_PTR(-EINVAL); 241 242 phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0); 243 of_node_put(remote); 244 if (!phandle) 245 return ERR_PTR(-ENODEV); 246 247 ddc = of_get_i2c_adapter_by_node(phandle); 248 of_node_put(phandle); 249 if (!ddc) 250 return ERR_PTR(-EPROBE_DEFER); 251 252 return ddc; 253 } 254 255 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 256 .get_modes = sun4i_hdmi_get_modes, 257 }; 258 259 static enum drm_connector_status 260 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 261 { 262 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 263 unsigned long reg; 264 265 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, 266 reg & SUN4I_HDMI_HPD_HIGH, 267 0, 500000)) { 268 cec_phys_addr_invalidate(hdmi->cec_adap); 269 return connector_status_disconnected; 270 } 271 272 return connector_status_connected; 273 } 274 275 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 276 .detect = sun4i_hdmi_connector_detect, 277 .fill_modes = drm_helper_probe_single_connector_modes, 278 .destroy = drm_connector_cleanup, 279 .reset = drm_atomic_helper_connector_reset, 280 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 281 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 282 }; 283 284 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 285 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 286 { 287 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 288 289 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 290 } 291 292 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 293 { 294 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 295 296 /* Start driving the CEC pin low */ 297 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 298 } 299 300 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 301 { 302 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 303 304 /* 305 * Stop driving the CEC pin, the pull up will take over 306 * unless another CEC device is driving the pin low. 307 */ 308 writel(0, hdmi->base + SUN4I_HDMI_CEC); 309 } 310 311 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 312 .read = sun4i_hdmi_cec_pin_read, 313 .low = sun4i_hdmi_cec_pin_low, 314 .high = sun4i_hdmi_cec_pin_high, 315 }; 316 #endif 317 318 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 319 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 320 321 /* Only difference from sun5i is AMP is 4 instead of 6 */ 322 static const struct sun4i_hdmi_variant sun4i_variant = { 323 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 324 SUN4I_HDMI_PAD_CTRL0_CKEN | 325 SUN4I_HDMI_PAD_CTRL0_PWENG | 326 SUN4I_HDMI_PAD_CTRL0_PWEND | 327 SUN4I_HDMI_PAD_CTRL0_PWENC | 328 SUN4I_HDMI_PAD_CTRL0_LDODEN | 329 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 330 SUN4I_HDMI_PAD_CTRL0_BIASEN, 331 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 332 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 333 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 334 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 335 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 336 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 337 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 338 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 339 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 340 SUN4I_HDMI_PLL_CTRL_CS(7) | 341 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 342 SUN4I_HDMI_PLL_CTRL_S(7) | 343 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 344 SUN4I_HDMI_PLL_CTRL_SDIV2 | 345 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 346 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 347 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 348 SUN4I_HDMI_PLL_CTRL_BWS | 349 SUN4I_HDMI_PLL_CTRL_PLL_EN, 350 351 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 352 .ddc_clk_pre_divider = 2, 353 .ddc_clk_m_offset = 1, 354 355 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 356 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 357 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 358 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 359 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 360 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 361 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 362 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 363 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 364 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 365 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 366 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 367 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 368 369 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 370 .ddc_fifo_has_dir = true, 371 }; 372 373 static const struct sun4i_hdmi_variant sun5i_variant = { 374 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 375 SUN4I_HDMI_PAD_CTRL0_CKEN | 376 SUN4I_HDMI_PAD_CTRL0_PWENG | 377 SUN4I_HDMI_PAD_CTRL0_PWEND | 378 SUN4I_HDMI_PAD_CTRL0_PWENC | 379 SUN4I_HDMI_PAD_CTRL0_LDODEN | 380 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 381 SUN4I_HDMI_PAD_CTRL0_BIASEN, 382 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 383 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 384 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 385 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 386 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 387 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 388 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 389 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 390 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 391 SUN4I_HDMI_PLL_CTRL_CS(7) | 392 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 393 SUN4I_HDMI_PLL_CTRL_S(7) | 394 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 395 SUN4I_HDMI_PLL_CTRL_SDIV2 | 396 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 397 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 398 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 399 SUN4I_HDMI_PLL_CTRL_BWS | 400 SUN4I_HDMI_PLL_CTRL_PLL_EN, 401 402 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 403 .ddc_clk_pre_divider = 2, 404 .ddc_clk_m_offset = 1, 405 406 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 407 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 408 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 409 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 410 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 411 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 412 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 413 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 414 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 415 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 416 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 417 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 418 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 419 420 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 421 .ddc_fifo_has_dir = true, 422 }; 423 424 static const struct sun4i_hdmi_variant sun6i_variant = { 425 .has_ddc_parent_clk = true, 426 .has_reset_control = true, 427 .pad_ctrl0_init_val = 0xff | 428 SUN4I_HDMI_PAD_CTRL0_TXEN | 429 SUN4I_HDMI_PAD_CTRL0_CKEN | 430 SUN4I_HDMI_PAD_CTRL0_PWENG | 431 SUN4I_HDMI_PAD_CTRL0_PWEND | 432 SUN4I_HDMI_PAD_CTRL0_PWENC | 433 SUN4I_HDMI_PAD_CTRL0_LDODEN | 434 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 435 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 436 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 437 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 438 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 439 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 440 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 441 SUN4I_HDMI_PAD_CTRL1_PWSDT | 442 SUN4I_HDMI_PAD_CTRL1_PWSCK | 443 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 444 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 445 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 446 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 447 SUN4I_HDMI_PLL_CTRL_CS(3) | 448 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 449 SUN4I_HDMI_PLL_CTRL_S(4) | 450 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 451 SUN4I_HDMI_PLL_CTRL_SDIV2 | 452 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 453 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 454 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 455 SUN4I_HDMI_PLL_CTRL_PLL_EN, 456 457 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 458 .ddc_clk_pre_divider = 1, 459 .ddc_clk_m_offset = 2, 460 461 .tmds_clk_div_offset = 1, 462 463 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 464 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 465 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 466 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 467 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 468 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 469 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 470 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 471 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 472 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 473 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 474 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 475 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 476 477 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 478 .ddc_fifo_thres_incl = true, 479 }; 480 481 static const struct regmap_config sun4i_hdmi_regmap_config = { 482 .reg_bits = 32, 483 .val_bits = 32, 484 .reg_stride = 4, 485 .max_register = 0x580, 486 }; 487 488 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 489 void *data) 490 { 491 struct platform_device *pdev = to_platform_device(dev); 492 struct drm_device *drm = data; 493 struct cec_connector_info conn_info; 494 struct sun4i_drv *drv = drm->dev_private; 495 struct sun4i_hdmi *hdmi; 496 struct resource *res; 497 u32 reg; 498 int ret; 499 500 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 501 if (!hdmi) 502 return -ENOMEM; 503 dev_set_drvdata(dev, hdmi); 504 hdmi->dev = dev; 505 hdmi->drv = drv; 506 507 hdmi->variant = of_device_get_match_data(dev); 508 if (!hdmi->variant) 509 return -EINVAL; 510 511 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 512 hdmi->base = devm_ioremap_resource(dev, res); 513 if (IS_ERR(hdmi->base)) { 514 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 515 return PTR_ERR(hdmi->base); 516 } 517 518 if (hdmi->variant->has_reset_control) { 519 hdmi->reset = devm_reset_control_get(dev, NULL); 520 if (IS_ERR(hdmi->reset)) { 521 dev_err(dev, "Couldn't get the HDMI reset control\n"); 522 return PTR_ERR(hdmi->reset); 523 } 524 525 ret = reset_control_deassert(hdmi->reset); 526 if (ret) { 527 dev_err(dev, "Couldn't deassert HDMI reset\n"); 528 return ret; 529 } 530 } 531 532 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 533 if (IS_ERR(hdmi->bus_clk)) { 534 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 535 ret = PTR_ERR(hdmi->bus_clk); 536 goto err_assert_reset; 537 } 538 clk_prepare_enable(hdmi->bus_clk); 539 540 hdmi->mod_clk = devm_clk_get(dev, "mod"); 541 if (IS_ERR(hdmi->mod_clk)) { 542 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 543 ret = PTR_ERR(hdmi->mod_clk); 544 goto err_disable_bus_clk; 545 } 546 clk_prepare_enable(hdmi->mod_clk); 547 548 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 549 if (IS_ERR(hdmi->pll0_clk)) { 550 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 551 ret = PTR_ERR(hdmi->pll0_clk); 552 goto err_disable_mod_clk; 553 } 554 555 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 556 if (IS_ERR(hdmi->pll1_clk)) { 557 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 558 ret = PTR_ERR(hdmi->pll1_clk); 559 goto err_disable_mod_clk; 560 } 561 562 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 563 &sun4i_hdmi_regmap_config); 564 if (IS_ERR(hdmi->regmap)) { 565 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 566 ret = PTR_ERR(hdmi->regmap); 567 goto err_disable_mod_clk; 568 } 569 570 ret = sun4i_tmds_create(hdmi); 571 if (ret) { 572 dev_err(dev, "Couldn't create the TMDS clock\n"); 573 goto err_disable_mod_clk; 574 } 575 576 if (hdmi->variant->has_ddc_parent_clk) { 577 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 578 if (IS_ERR(hdmi->ddc_parent_clk)) { 579 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 580 ret = PTR_ERR(hdmi->ddc_parent_clk); 581 goto err_disable_mod_clk; 582 } 583 } else { 584 hdmi->ddc_parent_clk = hdmi->tmds_clk; 585 } 586 587 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 588 589 writel(hdmi->variant->pad_ctrl0_init_val, 590 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 591 592 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 593 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 594 reg |= hdmi->variant->pll_ctrl_init_val; 595 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 596 597 ret = sun4i_hdmi_i2c_create(dev, hdmi); 598 if (ret) { 599 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 600 goto err_disable_mod_clk; 601 } 602 603 hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev); 604 if (IS_ERR(hdmi->ddc_i2c)) { 605 ret = PTR_ERR(hdmi->ddc_i2c); 606 if (ret == -ENODEV) 607 hdmi->ddc_i2c = NULL; 608 else 609 goto err_del_i2c_adapter; 610 } 611 612 drm_encoder_helper_add(&hdmi->encoder, 613 &sun4i_hdmi_helper_funcs); 614 ret = drm_encoder_init(drm, 615 &hdmi->encoder, 616 &sun4i_hdmi_funcs, 617 DRM_MODE_ENCODER_TMDS, 618 NULL); 619 if (ret) { 620 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 621 goto err_put_ddc_i2c; 622 } 623 624 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 625 dev->of_node); 626 if (!hdmi->encoder.possible_crtcs) { 627 ret = -EPROBE_DEFER; 628 goto err_put_ddc_i2c; 629 } 630 631 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 632 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 633 hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO); 634 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 635 if (ret < 0) 636 goto err_cleanup_connector; 637 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 638 hdmi->base + SUN4I_HDMI_CEC); 639 #endif 640 641 drm_connector_helper_add(&hdmi->connector, 642 &sun4i_hdmi_connector_helper_funcs); 643 ret = drm_connector_init_with_ddc(drm, &hdmi->connector, 644 &sun4i_hdmi_connector_funcs, 645 DRM_MODE_CONNECTOR_HDMIA, 646 hdmi->ddc_i2c); 647 if (ret) { 648 dev_err(dev, 649 "Couldn't initialise the HDMI connector\n"); 650 goto err_cleanup_connector; 651 } 652 cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector); 653 cec_s_conn_info(hdmi->cec_adap, &conn_info); 654 655 /* There is no HPD interrupt, so we need to poll the controller */ 656 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 657 DRM_CONNECTOR_POLL_DISCONNECT; 658 659 ret = cec_register_adapter(hdmi->cec_adap, dev); 660 if (ret < 0) 661 goto err_cleanup_connector; 662 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 663 664 return 0; 665 666 err_cleanup_connector: 667 cec_delete_adapter(hdmi->cec_adap); 668 drm_encoder_cleanup(&hdmi->encoder); 669 err_put_ddc_i2c: 670 i2c_put_adapter(hdmi->ddc_i2c); 671 err_del_i2c_adapter: 672 i2c_del_adapter(hdmi->i2c); 673 err_disable_mod_clk: 674 clk_disable_unprepare(hdmi->mod_clk); 675 err_disable_bus_clk: 676 clk_disable_unprepare(hdmi->bus_clk); 677 err_assert_reset: 678 reset_control_assert(hdmi->reset); 679 return ret; 680 } 681 682 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 683 void *data) 684 { 685 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 686 687 cec_unregister_adapter(hdmi->cec_adap); 688 drm_connector_cleanup(&hdmi->connector); 689 drm_encoder_cleanup(&hdmi->encoder); 690 i2c_del_adapter(hdmi->i2c); 691 i2c_put_adapter(hdmi->ddc_i2c); 692 clk_disable_unprepare(hdmi->mod_clk); 693 clk_disable_unprepare(hdmi->bus_clk); 694 } 695 696 static const struct component_ops sun4i_hdmi_ops = { 697 .bind = sun4i_hdmi_bind, 698 .unbind = sun4i_hdmi_unbind, 699 }; 700 701 static int sun4i_hdmi_probe(struct platform_device *pdev) 702 { 703 return component_add(&pdev->dev, &sun4i_hdmi_ops); 704 } 705 706 static int sun4i_hdmi_remove(struct platform_device *pdev) 707 { 708 component_del(&pdev->dev, &sun4i_hdmi_ops); 709 710 return 0; 711 } 712 713 static const struct of_device_id sun4i_hdmi_of_table[] = { 714 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 715 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 716 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 717 { } 718 }; 719 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 720 721 static struct platform_driver sun4i_hdmi_driver = { 722 .probe = sun4i_hdmi_probe, 723 .remove = sun4i_hdmi_remove, 724 .driver = { 725 .name = "sun4i-hdmi", 726 .of_match_table = sun4i_hdmi_of_table, 727 }, 728 }; 729 module_platform_driver(sun4i_hdmi_driver); 730 731 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 732 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 733 MODULE_LICENSE("GPL"); 734