1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #include <drm/drmP.h> 13 #include <drm/drm_atomic_helper.h> 14 #include <drm/drm_crtc_helper.h> 15 #include <drm/drm_edid.h> 16 #include <drm/drm_encoder.h> 17 #include <drm/drm_of.h> 18 #include <drm/drm_panel.h> 19 20 #include <linux/clk.h> 21 #include <linux/component.h> 22 #include <linux/iopoll.h> 23 #include <linux/of_device.h> 24 #include <linux/platform_device.h> 25 #include <linux/pm_runtime.h> 26 #include <linux/regmap.h> 27 #include <linux/reset.h> 28 29 #include "sun4i_backend.h" 30 #include "sun4i_crtc.h" 31 #include "sun4i_drv.h" 32 #include "sun4i_hdmi.h" 33 34 static inline struct sun4i_hdmi * 35 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder) 36 { 37 return container_of(encoder, struct sun4i_hdmi, 38 encoder); 39 } 40 41 static inline struct sun4i_hdmi * 42 drm_connector_to_sun4i_hdmi(struct drm_connector *connector) 43 { 44 return container_of(connector, struct sun4i_hdmi, 45 connector); 46 } 47 48 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi, 49 struct drm_display_mode *mode) 50 { 51 struct hdmi_avi_infoframe frame; 52 u8 buffer[17]; 53 int i, ret; 54 55 ret = drm_hdmi_avi_infoframe_from_display_mode(&frame, 56 &hdmi->connector, mode); 57 if (ret < 0) { 58 DRM_ERROR("Failed to get infoframes from mode\n"); 59 return ret; 60 } 61 62 ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer)); 63 if (ret < 0) { 64 DRM_ERROR("Failed to pack infoframes\n"); 65 return ret; 66 } 67 68 for (i = 0; i < sizeof(buffer); i++) 69 writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i)); 70 71 return 0; 72 } 73 74 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder, 75 struct drm_crtc_state *crtc_state, 76 struct drm_connector_state *conn_state) 77 { 78 struct drm_display_mode *mode = &crtc_state->mode; 79 80 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 81 return -EINVAL; 82 83 return 0; 84 } 85 86 static void sun4i_hdmi_disable(struct drm_encoder *encoder) 87 { 88 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 89 u32 val; 90 91 DRM_DEBUG_DRIVER("Disabling the HDMI Output\n"); 92 93 val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 94 val &= ~SUN4I_HDMI_VID_CTRL_ENABLE; 95 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 96 } 97 98 static void sun4i_hdmi_enable(struct drm_encoder *encoder) 99 { 100 struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode; 101 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 102 u32 val = 0; 103 104 DRM_DEBUG_DRIVER("Enabling the HDMI Output\n"); 105 106 sun4i_hdmi_setup_avi_infoframes(hdmi, mode); 107 val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI); 108 val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END); 109 writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0)); 110 111 val = SUN4I_HDMI_VID_CTRL_ENABLE; 112 if (hdmi->hdmi_monitor) 113 val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE; 114 115 writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG); 116 } 117 118 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder, 119 struct drm_display_mode *mode, 120 struct drm_display_mode *adjusted_mode) 121 { 122 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 123 unsigned int x, y; 124 u32 val; 125 126 clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000); 127 clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000); 128 129 /* Set input sync enable */ 130 writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC, 131 hdmi->base + SUN4I_HDMI_UNKNOWN_REG); 132 133 /* 134 * Setup output pad (?) controls 135 * 136 * This is done here instead of at probe/bind time because 137 * the controller seems to toggle some of the bits on its own. 138 * 139 * We can't just initialize the register there, we need to 140 * protect the clock bits that have already been read out and 141 * cached by the clock framework. 142 */ 143 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 144 val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK; 145 val |= hdmi->variant->pad_ctrl1_init_val; 146 writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 147 val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG); 148 149 /* Setup timing registers */ 150 writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) | 151 SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay), 152 hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG); 153 154 x = mode->htotal - mode->hsync_start; 155 y = mode->vtotal - mode->vsync_start; 156 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 157 hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG); 158 159 x = mode->hsync_start - mode->hdisplay; 160 y = mode->vsync_start - mode->vdisplay; 161 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 162 hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG); 163 164 x = mode->hsync_end - mode->hsync_start; 165 y = mode->vsync_end - mode->vsync_start; 166 writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y), 167 hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG); 168 169 val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK; 170 if (mode->flags & DRM_MODE_FLAG_PHSYNC) 171 val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC; 172 173 if (mode->flags & DRM_MODE_FLAG_PVSYNC) 174 val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC; 175 176 writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG); 177 } 178 179 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder, 180 const struct drm_display_mode *mode) 181 { 182 struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder); 183 unsigned long rate = mode->clock * 1000; 184 unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */ 185 long rounded_rate; 186 187 /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */ 188 if (rate > 165000000) 189 return MODE_CLOCK_HIGH; 190 rounded_rate = clk_round_rate(hdmi->tmds_clk, rate); 191 if (rounded_rate > 0 && 192 max_t(unsigned long, rounded_rate, rate) - 193 min_t(unsigned long, rounded_rate, rate) < diff) 194 return MODE_OK; 195 return MODE_NOCLOCK; 196 } 197 198 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = { 199 .atomic_check = sun4i_hdmi_atomic_check, 200 .disable = sun4i_hdmi_disable, 201 .enable = sun4i_hdmi_enable, 202 .mode_set = sun4i_hdmi_mode_set, 203 .mode_valid = sun4i_hdmi_mode_valid, 204 }; 205 206 static const struct drm_encoder_funcs sun4i_hdmi_funcs = { 207 .destroy = drm_encoder_cleanup, 208 }; 209 210 static int sun4i_hdmi_get_modes(struct drm_connector *connector) 211 { 212 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 213 struct edid *edid; 214 int ret; 215 216 edid = drm_get_edid(connector, hdmi->i2c); 217 if (!edid) 218 return 0; 219 220 hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid); 221 DRM_DEBUG_DRIVER("Monitor is %s monitor\n", 222 hdmi->hdmi_monitor ? "an HDMI" : "a DVI"); 223 224 drm_connector_update_edid_property(connector, edid); 225 cec_s_phys_addr_from_edid(hdmi->cec_adap, edid); 226 ret = drm_add_edid_modes(connector, edid); 227 kfree(edid); 228 229 return ret; 230 } 231 232 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = { 233 .get_modes = sun4i_hdmi_get_modes, 234 }; 235 236 static enum drm_connector_status 237 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force) 238 { 239 struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector); 240 unsigned long reg; 241 242 if (readl_poll_timeout(hdmi->base + SUN4I_HDMI_HPD_REG, reg, 243 reg & SUN4I_HDMI_HPD_HIGH, 244 0, 500000)) { 245 cec_phys_addr_invalidate(hdmi->cec_adap); 246 return connector_status_disconnected; 247 } 248 249 return connector_status_connected; 250 } 251 252 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = { 253 .detect = sun4i_hdmi_connector_detect, 254 .fill_modes = drm_helper_probe_single_connector_modes, 255 .destroy = drm_connector_cleanup, 256 .reset = drm_atomic_helper_connector_reset, 257 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, 258 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 259 }; 260 261 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 262 static bool sun4i_hdmi_cec_pin_read(struct cec_adapter *adap) 263 { 264 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 265 266 return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX; 267 } 268 269 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap) 270 { 271 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 272 273 /* Start driving the CEC pin low */ 274 writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC); 275 } 276 277 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap) 278 { 279 struct sun4i_hdmi *hdmi = cec_get_drvdata(adap); 280 281 /* 282 * Stop driving the CEC pin, the pull up will take over 283 * unless another CEC device is driving the pin low. 284 */ 285 writel(0, hdmi->base + SUN4I_HDMI_CEC); 286 } 287 288 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = { 289 .read = sun4i_hdmi_cec_pin_read, 290 .low = sun4i_hdmi_cec_pin_low, 291 .high = sun4i_hdmi_cec_pin_high, 292 }; 293 #endif 294 295 #define SUN4I_HDMI_PAD_CTRL1_MASK (GENMASK(24, 7) | GENMASK(5, 0)) 296 #define SUN4I_HDMI_PLL_CTRL_MASK (GENMASK(31, 8) | GENMASK(3, 0)) 297 298 /* Only difference from sun5i is AMP is 4 instead of 6 */ 299 static const struct sun4i_hdmi_variant sun4i_variant = { 300 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 301 SUN4I_HDMI_PAD_CTRL0_CKEN | 302 SUN4I_HDMI_PAD_CTRL0_PWENG | 303 SUN4I_HDMI_PAD_CTRL0_PWEND | 304 SUN4I_HDMI_PAD_CTRL0_PWENC | 305 SUN4I_HDMI_PAD_CTRL0_LDODEN | 306 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 307 SUN4I_HDMI_PAD_CTRL0_BIASEN, 308 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) | 309 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 310 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 311 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 312 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 313 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 314 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 315 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 316 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 317 SUN4I_HDMI_PLL_CTRL_CS(7) | 318 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 319 SUN4I_HDMI_PLL_CTRL_S(7) | 320 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 321 SUN4I_HDMI_PLL_CTRL_SDIV2 | 322 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 323 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 324 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 325 SUN4I_HDMI_PLL_CTRL_BWS | 326 SUN4I_HDMI_PLL_CTRL_PLL_EN, 327 328 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 329 .ddc_clk_pre_divider = 2, 330 .ddc_clk_m_offset = 1, 331 332 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 333 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 334 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 335 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 336 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 337 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 338 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 339 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 340 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 341 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 342 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 343 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 344 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 345 346 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 347 .ddc_fifo_has_dir = true, 348 }; 349 350 static const struct sun4i_hdmi_variant sun5i_variant = { 351 .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN | 352 SUN4I_HDMI_PAD_CTRL0_CKEN | 353 SUN4I_HDMI_PAD_CTRL0_PWENG | 354 SUN4I_HDMI_PAD_CTRL0_PWEND | 355 SUN4I_HDMI_PAD_CTRL0_PWENC | 356 SUN4I_HDMI_PAD_CTRL0_LDODEN | 357 SUN4I_HDMI_PAD_CTRL0_LDOCEN | 358 SUN4I_HDMI_PAD_CTRL0_BIASEN, 359 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 360 SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) | 361 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 362 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 363 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 364 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 365 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 366 SUN4I_HDMI_PAD_CTRL1_AMP_OPT, 367 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 368 SUN4I_HDMI_PLL_CTRL_CS(7) | 369 SUN4I_HDMI_PLL_CTRL_CP_S(15) | 370 SUN4I_HDMI_PLL_CTRL_S(7) | 371 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 372 SUN4I_HDMI_PLL_CTRL_SDIV2 | 373 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 374 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 375 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 376 SUN4I_HDMI_PLL_CTRL_BWS | 377 SUN4I_HDMI_PLL_CTRL_PLL_EN, 378 379 .ddc_clk_reg = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6), 380 .ddc_clk_pre_divider = 2, 381 .ddc_clk_m_offset = 1, 382 383 .field_ddc_en = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31), 384 .field_ddc_start = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30), 385 .field_ddc_reset = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0), 386 .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31), 387 .field_ddc_slave_addr = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6), 388 .field_ddc_int_status = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8), 389 .field_ddc_fifo_clear = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31), 390 .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 391 .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 392 .field_ddc_byte_count = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9), 393 .field_ddc_cmd = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2), 394 .field_ddc_sda_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9), 395 .field_ddc_sck_en = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8), 396 397 .ddc_fifo_reg = SUN4I_HDMI_DDC_FIFO_DATA_REG, 398 .ddc_fifo_has_dir = true, 399 }; 400 401 static const struct sun4i_hdmi_variant sun6i_variant = { 402 .has_ddc_parent_clk = true, 403 .has_reset_control = true, 404 .pad_ctrl0_init_val = 0xff | 405 SUN4I_HDMI_PAD_CTRL0_TXEN | 406 SUN4I_HDMI_PAD_CTRL0_CKEN | 407 SUN4I_HDMI_PAD_CTRL0_PWENG | 408 SUN4I_HDMI_PAD_CTRL0_PWEND | 409 SUN4I_HDMI_PAD_CTRL0_PWENC | 410 SUN4I_HDMI_PAD_CTRL0_LDODEN | 411 SUN4I_HDMI_PAD_CTRL0_LDOCEN, 412 .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) | 413 SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) | 414 SUN4I_HDMI_PAD_CTRL1_REG_DENCK | 415 SUN4I_HDMI_PAD_CTRL1_REG_DEN | 416 SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT | 417 SUN4I_HDMI_PAD_CTRL1_EMP_OPT | 418 SUN4I_HDMI_PAD_CTRL1_PWSDT | 419 SUN4I_HDMI_PAD_CTRL1_PWSCK | 420 SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT | 421 SUN4I_HDMI_PAD_CTRL1_AMP_OPT | 422 SUN4I_HDMI_PAD_CTRL1_UNKNOWN, 423 .pll_ctrl_init_val = SUN4I_HDMI_PLL_CTRL_VCO_S(8) | 424 SUN4I_HDMI_PLL_CTRL_CS(3) | 425 SUN4I_HDMI_PLL_CTRL_CP_S(10) | 426 SUN4I_HDMI_PLL_CTRL_S(4) | 427 SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) | 428 SUN4I_HDMI_PLL_CTRL_SDIV2 | 429 SUN4I_HDMI_PLL_CTRL_LDO2_EN | 430 SUN4I_HDMI_PLL_CTRL_LDO1_EN | 431 SUN4I_HDMI_PLL_CTRL_HV_IS_33 | 432 SUN4I_HDMI_PLL_CTRL_PLL_EN, 433 434 .ddc_clk_reg = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6), 435 .ddc_clk_pre_divider = 1, 436 .ddc_clk_m_offset = 2, 437 438 .tmds_clk_div_offset = 1, 439 440 .field_ddc_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0), 441 .field_ddc_start = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27), 442 .field_ddc_reset = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31), 443 .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31), 444 .field_ddc_slave_addr = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7), 445 .field_ddc_int_status = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8), 446 .field_ddc_fifo_clear = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18), 447 .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7), 448 .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3), 449 .field_ddc_byte_count = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25), 450 .field_ddc_cmd = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2), 451 .field_ddc_sda_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6), 452 .field_ddc_sck_en = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4), 453 454 .ddc_fifo_reg = SUN6I_HDMI_DDC_FIFO_DATA_REG, 455 .ddc_fifo_thres_incl = true, 456 }; 457 458 static const struct regmap_config sun4i_hdmi_regmap_config = { 459 .reg_bits = 32, 460 .val_bits = 32, 461 .reg_stride = 4, 462 .max_register = 0x580, 463 }; 464 465 static int sun4i_hdmi_bind(struct device *dev, struct device *master, 466 void *data) 467 { 468 struct platform_device *pdev = to_platform_device(dev); 469 struct drm_device *drm = data; 470 struct sun4i_drv *drv = drm->dev_private; 471 struct sun4i_hdmi *hdmi; 472 struct resource *res; 473 u32 reg; 474 int ret; 475 476 hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL); 477 if (!hdmi) 478 return -ENOMEM; 479 dev_set_drvdata(dev, hdmi); 480 hdmi->dev = dev; 481 hdmi->drv = drv; 482 483 hdmi->variant = of_device_get_match_data(dev); 484 if (!hdmi->variant) 485 return -EINVAL; 486 487 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 488 hdmi->base = devm_ioremap_resource(dev, res); 489 if (IS_ERR(hdmi->base)) { 490 dev_err(dev, "Couldn't map the HDMI encoder registers\n"); 491 return PTR_ERR(hdmi->base); 492 } 493 494 if (hdmi->variant->has_reset_control) { 495 hdmi->reset = devm_reset_control_get(dev, NULL); 496 if (IS_ERR(hdmi->reset)) { 497 dev_err(dev, "Couldn't get the HDMI reset control\n"); 498 return PTR_ERR(hdmi->reset); 499 } 500 501 ret = reset_control_deassert(hdmi->reset); 502 if (ret) { 503 dev_err(dev, "Couldn't deassert HDMI reset\n"); 504 return ret; 505 } 506 } 507 508 hdmi->bus_clk = devm_clk_get(dev, "ahb"); 509 if (IS_ERR(hdmi->bus_clk)) { 510 dev_err(dev, "Couldn't get the HDMI bus clock\n"); 511 ret = PTR_ERR(hdmi->bus_clk); 512 goto err_assert_reset; 513 } 514 clk_prepare_enable(hdmi->bus_clk); 515 516 hdmi->mod_clk = devm_clk_get(dev, "mod"); 517 if (IS_ERR(hdmi->mod_clk)) { 518 dev_err(dev, "Couldn't get the HDMI mod clock\n"); 519 ret = PTR_ERR(hdmi->mod_clk); 520 goto err_disable_bus_clk; 521 } 522 clk_prepare_enable(hdmi->mod_clk); 523 524 hdmi->pll0_clk = devm_clk_get(dev, "pll-0"); 525 if (IS_ERR(hdmi->pll0_clk)) { 526 dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n"); 527 ret = PTR_ERR(hdmi->pll0_clk); 528 goto err_disable_mod_clk; 529 } 530 531 hdmi->pll1_clk = devm_clk_get(dev, "pll-1"); 532 if (IS_ERR(hdmi->pll1_clk)) { 533 dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n"); 534 ret = PTR_ERR(hdmi->pll1_clk); 535 goto err_disable_mod_clk; 536 } 537 538 hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base, 539 &sun4i_hdmi_regmap_config); 540 if (IS_ERR(hdmi->regmap)) { 541 dev_err(dev, "Couldn't create HDMI encoder regmap\n"); 542 ret = PTR_ERR(hdmi->regmap); 543 goto err_disable_mod_clk; 544 } 545 546 ret = sun4i_tmds_create(hdmi); 547 if (ret) { 548 dev_err(dev, "Couldn't create the TMDS clock\n"); 549 goto err_disable_mod_clk; 550 } 551 552 if (hdmi->variant->has_ddc_parent_clk) { 553 hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc"); 554 if (IS_ERR(hdmi->ddc_parent_clk)) { 555 dev_err(dev, "Couldn't get the HDMI DDC clock\n"); 556 ret = PTR_ERR(hdmi->ddc_parent_clk); 557 goto err_disable_mod_clk; 558 } 559 } else { 560 hdmi->ddc_parent_clk = hdmi->tmds_clk; 561 } 562 563 writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG); 564 565 writel(hdmi->variant->pad_ctrl0_init_val, 566 hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG); 567 568 reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 569 reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK; 570 reg |= hdmi->variant->pll_ctrl_init_val; 571 writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG); 572 573 ret = sun4i_hdmi_i2c_create(dev, hdmi); 574 if (ret) { 575 dev_err(dev, "Couldn't create the HDMI I2C adapter\n"); 576 goto err_disable_mod_clk; 577 } 578 579 drm_encoder_helper_add(&hdmi->encoder, 580 &sun4i_hdmi_helper_funcs); 581 ret = drm_encoder_init(drm, 582 &hdmi->encoder, 583 &sun4i_hdmi_funcs, 584 DRM_MODE_ENCODER_TMDS, 585 NULL); 586 if (ret) { 587 dev_err(dev, "Couldn't initialise the HDMI encoder\n"); 588 goto err_del_i2c_adapter; 589 } 590 591 hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, 592 dev->of_node); 593 if (!hdmi->encoder.possible_crtcs) { 594 ret = -EPROBE_DEFER; 595 goto err_del_i2c_adapter; 596 } 597 598 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC 599 hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops, 600 hdmi, "sun4i", CEC_CAP_TRANSMIT | CEC_CAP_LOG_ADDRS | 601 CEC_CAP_PASSTHROUGH | CEC_CAP_RC); 602 ret = PTR_ERR_OR_ZERO(hdmi->cec_adap); 603 if (ret < 0) 604 goto err_cleanup_connector; 605 writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX, 606 hdmi->base + SUN4I_HDMI_CEC); 607 #endif 608 609 drm_connector_helper_add(&hdmi->connector, 610 &sun4i_hdmi_connector_helper_funcs); 611 ret = drm_connector_init(drm, &hdmi->connector, 612 &sun4i_hdmi_connector_funcs, 613 DRM_MODE_CONNECTOR_HDMIA); 614 if (ret) { 615 dev_err(dev, 616 "Couldn't initialise the HDMI connector\n"); 617 goto err_cleanup_connector; 618 } 619 620 /* There is no HPD interrupt, so we need to poll the controller */ 621 hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT | 622 DRM_CONNECTOR_POLL_DISCONNECT; 623 624 ret = cec_register_adapter(hdmi->cec_adap, dev); 625 if (ret < 0) 626 goto err_cleanup_connector; 627 drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder); 628 629 return 0; 630 631 err_cleanup_connector: 632 cec_delete_adapter(hdmi->cec_adap); 633 drm_encoder_cleanup(&hdmi->encoder); 634 err_del_i2c_adapter: 635 i2c_del_adapter(hdmi->i2c); 636 err_disable_mod_clk: 637 clk_disable_unprepare(hdmi->mod_clk); 638 err_disable_bus_clk: 639 clk_disable_unprepare(hdmi->bus_clk); 640 err_assert_reset: 641 reset_control_assert(hdmi->reset); 642 return ret; 643 } 644 645 static void sun4i_hdmi_unbind(struct device *dev, struct device *master, 646 void *data) 647 { 648 struct sun4i_hdmi *hdmi = dev_get_drvdata(dev); 649 650 cec_unregister_adapter(hdmi->cec_adap); 651 drm_connector_cleanup(&hdmi->connector); 652 drm_encoder_cleanup(&hdmi->encoder); 653 i2c_del_adapter(hdmi->i2c); 654 clk_disable_unprepare(hdmi->mod_clk); 655 clk_disable_unprepare(hdmi->bus_clk); 656 } 657 658 static const struct component_ops sun4i_hdmi_ops = { 659 .bind = sun4i_hdmi_bind, 660 .unbind = sun4i_hdmi_unbind, 661 }; 662 663 static int sun4i_hdmi_probe(struct platform_device *pdev) 664 { 665 return component_add(&pdev->dev, &sun4i_hdmi_ops); 666 } 667 668 static int sun4i_hdmi_remove(struct platform_device *pdev) 669 { 670 component_del(&pdev->dev, &sun4i_hdmi_ops); 671 672 return 0; 673 } 674 675 static const struct of_device_id sun4i_hdmi_of_table[] = { 676 { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, }, 677 { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, }, 678 { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, }, 679 { } 680 }; 681 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table); 682 683 static struct platform_driver sun4i_hdmi_driver = { 684 .probe = sun4i_hdmi_probe, 685 .remove = sun4i_hdmi_remove, 686 .driver = { 687 .name = "sun4i-hdmi", 688 .of_match_table = sun4i_hdmi_of_table, 689 }, 690 }; 691 module_platform_driver(sun4i_hdmi_driver); 692 693 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 694 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver"); 695 MODULE_LICENSE("GPL"); 696