1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #ifndef _SUN4I_HDMI_H_ 13 #define _SUN4I_HDMI_H_ 14 15 #include <drm/drm_connector.h> 16 #include <drm/drm_encoder.h> 17 #include <linux/regmap.h> 18 19 #include <media/cec-pin.h> 20 21 #define SUN4I_HDMI_CTRL_REG 0x004 22 #define SUN4I_HDMI_CTRL_ENABLE BIT(31) 23 24 #define SUN4I_HDMI_IRQ_REG 0x008 25 #define SUN4I_HDMI_IRQ_STA_MASK 0x73 26 #define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) 27 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) 28 29 #define SUN4I_HDMI_HPD_REG 0x00c 30 #define SUN4I_HDMI_HPD_HIGH BIT(0) 31 32 #define SUN4I_HDMI_VID_CTRL_REG 0x010 33 #define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) 34 #define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) 35 36 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014 37 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018 38 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c 39 #define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020 40 41 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0))) 42 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16) 43 44 #define SUN4I_HDMI_VID_TIMING_POL_REG 0x024 45 #define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16) 46 #define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1) 47 #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0) 48 49 #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n)) 50 51 #define SUN4I_HDMI_PAD_CTRL0_REG 0x200 52 #define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31) 53 #define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30) 54 #define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29) 55 #define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28) 56 #define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27) 57 #define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26) 58 #define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25) 59 #define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) 60 61 #define SUN4I_HDMI_PAD_CTRL1_REG 0x204 62 #define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */ 63 #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) 64 #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) 65 #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) 66 #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) 67 #define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18) 68 #define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17) 69 #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) 70 #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) 71 #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10) 72 #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) 73 #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3) 74 75 /* These bits seem to invert the TMDS data channels */ 76 #define SUN4I_HDMI_PAD_CTRL1_INVERT_R BIT(2) 77 #define SUN4I_HDMI_PAD_CTRL1_INVERT_G BIT(1) 78 #define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0) 79 80 #define SUN4I_HDMI_PLL_CTRL_REG 0x208 81 #define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31) 82 #define SUN4I_HDMI_PLL_CTRL_BWS BIT(30) 83 #define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29) 84 #define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28) 85 #define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27) 86 #define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25) 87 #define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20) 88 #define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17) 89 #define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12) 90 #define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8) 91 #define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4) 92 #define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4) 93 #define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf) 94 95 #define SUN4I_HDMI_PLL_DBG0_REG 0x20c 96 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21) 97 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) 98 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 99 100 #define SUN4I_HDMI_CEC 0x214 101 #define SUN4I_HDMI_CEC_ENABLE BIT(11) 102 #define SUN4I_HDMI_CEC_TX BIT(9) 103 #define SUN4I_HDMI_CEC_RX BIT(8) 104 105 #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) 106 #define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) 107 108 #define SUN4I_HDMI_UNKNOWN_REG 0x300 109 #define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27) 110 111 #define SUN4I_HDMI_DDC_CTRL_REG 0x500 112 #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) 113 #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) 114 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) 115 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8) 116 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8) 117 #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) 118 119 #define SUN4I_HDMI_DDC_ADDR_REG 0x504 120 #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) 121 #define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) 122 #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) 123 #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff) 124 125 #define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c 126 #define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) 127 #define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) 128 #define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) 129 #define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) 130 #define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) 131 #define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) 132 #define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) 133 #define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) 134 135 #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510 136 #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) 137 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4) 138 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4) 139 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1) 140 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf) 141 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0) 142 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1) 143 144 #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 145 146 #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c 147 #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1) 148 149 #define SUN4I_HDMI_DDC_CMD_REG 0x520 150 #define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 151 #define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5 152 #define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3 153 154 #define SUN4I_HDMI_DDC_CLK_REG 0x528 155 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3) 156 #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7) 157 158 #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540 159 #define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9) 160 #define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8) 161 162 #define SUN4I_HDMI_DDC_FIFO_SIZE 16 163 164 /* A31 specific */ 165 #define SUN6I_HDMI_DDC_CTRL_REG 0x500 166 #define SUN6I_HDMI_DDC_CTRL_RESET BIT(31) 167 #define SUN6I_HDMI_DDC_CTRL_START_CMD BIT(27) 168 #define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6) 169 #define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4) 170 #define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0) 171 172 #define SUN6I_HDMI_DDC_CMD_REG 0x508 173 #define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count) ((count) << 16) 174 /* command types in lower 3 bits are the same as sun4i */ 175 176 #define SUN6I_HDMI_DDC_ADDR_REG 0x50c 177 #define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) 178 #define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) 179 #define SUN6I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) 180 #define SUN6I_HDMI_DDC_ADDR_SLAVE(addr) (((addr) & 0xff) << 1) 181 182 #define SUN6I_HDMI_DDC_INT_STATUS_REG 0x514 183 #define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT BIT(8) 184 /* lower 8 bits are the same as sun4i */ 185 186 #define SUN6I_HDMI_DDC_FIFO_CTRL_REG 0x518 187 #define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15) 188 /* lower 9 bits are the same as sun4i */ 189 190 #define SUN6I_HDMI_DDC_CLK_REG 0x520 191 /* DDC CLK bit fields are the same, but the formula is not */ 192 193 #define SUN6I_HDMI_DDC_FIFO_DATA_REG 0x580 194 195 enum sun4i_hdmi_pkt_type { 196 SUN4I_HDMI_PKT_AVI = 2, 197 SUN4I_HDMI_PKT_END = 15, 198 }; 199 200 struct sun4i_hdmi_variant { 201 bool has_ddc_parent_clk; 202 bool has_reset_control; 203 204 u32 pad_ctrl0_init_val; 205 u32 pad_ctrl1_init_val; 206 u32 pll_ctrl_init_val; 207 208 struct reg_field ddc_clk_reg; 209 u8 ddc_clk_pre_divider; 210 u8 ddc_clk_m_offset; 211 212 u8 tmds_clk_div_offset; 213 214 /* Register fields for I2C adapter */ 215 struct reg_field field_ddc_en; 216 struct reg_field field_ddc_start; 217 struct reg_field field_ddc_reset; 218 struct reg_field field_ddc_addr_reg; 219 struct reg_field field_ddc_slave_addr; 220 struct reg_field field_ddc_int_mask; 221 struct reg_field field_ddc_int_status; 222 struct reg_field field_ddc_fifo_clear; 223 struct reg_field field_ddc_fifo_rx_thres; 224 struct reg_field field_ddc_fifo_tx_thres; 225 struct reg_field field_ddc_byte_count; 226 struct reg_field field_ddc_cmd; 227 struct reg_field field_ddc_sda_en; 228 struct reg_field field_ddc_sck_en; 229 230 /* DDC FIFO register offset */ 231 u32 ddc_fifo_reg; 232 233 /* 234 * DDC FIFO threshold boundary conditions 235 * 236 * This is used to cope with the threshold boundary condition 237 * being slightly different on sun5i and sun6i. 238 * 239 * On sun5i the threshold is exclusive, i.e. does not include, 240 * the value of the threshold. ( > for RX; < for TX ) 241 * On sun6i the threshold is inclusive, i.e. includes, the 242 * value of the threshold. ( >= for RX; <= for TX ) 243 */ 244 bool ddc_fifo_thres_incl; 245 246 bool ddc_fifo_has_dir; 247 }; 248 249 struct sun4i_hdmi { 250 struct drm_connector connector; 251 struct drm_encoder encoder; 252 struct device *dev; 253 254 void __iomem *base; 255 struct regmap *regmap; 256 257 /* Reset control */ 258 struct reset_control *reset; 259 260 /* Parent clocks */ 261 struct clk *bus_clk; 262 struct clk *mod_clk; 263 struct clk *ddc_parent_clk; 264 struct clk *pll0_clk; 265 struct clk *pll1_clk; 266 267 /* And the clocks we create */ 268 struct clk *ddc_clk; 269 struct clk *tmds_clk; 270 271 struct i2c_adapter *i2c; 272 273 /* Regmap fields for I2C adapter */ 274 struct regmap_field *field_ddc_en; 275 struct regmap_field *field_ddc_start; 276 struct regmap_field *field_ddc_reset; 277 struct regmap_field *field_ddc_addr_reg; 278 struct regmap_field *field_ddc_slave_addr; 279 struct regmap_field *field_ddc_int_mask; 280 struct regmap_field *field_ddc_int_status; 281 struct regmap_field *field_ddc_fifo_clear; 282 struct regmap_field *field_ddc_fifo_rx_thres; 283 struct regmap_field *field_ddc_fifo_tx_thres; 284 struct regmap_field *field_ddc_byte_count; 285 struct regmap_field *field_ddc_cmd; 286 struct regmap_field *field_ddc_sda_en; 287 struct regmap_field *field_ddc_sck_en; 288 289 struct sun4i_drv *drv; 290 291 bool hdmi_monitor; 292 struct cec_adapter *cec_adap; 293 294 const struct sun4i_hdmi_variant *variant; 295 }; 296 297 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); 298 int sun4i_tmds_create(struct sun4i_hdmi *hdmi); 299 int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi); 300 301 #endif /* _SUN4I_HDMI_H_ */ 302