1 /* 2 * Copyright (C) 2016 Maxime Ripard 3 * 4 * Maxime Ripard <maxime.ripard@free-electrons.com> 5 * 6 * This program is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU General Public License as 8 * published by the Free Software Foundation; either version 2 of 9 * the License, or (at your option) any later version. 10 */ 11 12 #ifndef _SUN4I_HDMI_H_ 13 #define _SUN4I_HDMI_H_ 14 15 #include <drm/drm_connector.h> 16 #include <drm/drm_encoder.h> 17 #include <linux/regmap.h> 18 19 #include <media/cec-pin.h> 20 21 #define SUN4I_HDMI_CTRL_REG 0x004 22 #define SUN4I_HDMI_CTRL_ENABLE BIT(31) 23 24 #define SUN4I_HDMI_IRQ_REG 0x008 25 #define SUN4I_HDMI_IRQ_STA_MASK 0x73 26 #define SUN4I_HDMI_IRQ_STA_FIFO_OF BIT(1) 27 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0) 28 29 #define SUN4I_HDMI_HPD_REG 0x00c 30 #define SUN4I_HDMI_HPD_HIGH BIT(0) 31 32 #define SUN4I_HDMI_VID_CTRL_REG 0x010 33 #define SUN4I_HDMI_VID_CTRL_ENABLE BIT(31) 34 #define SUN4I_HDMI_VID_CTRL_HDMI_MODE BIT(30) 35 36 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014 37 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018 38 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c 39 #define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020 40 41 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0))) 42 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16) 43 44 #define SUN4I_HDMI_VID_TIMING_POL_REG 0x024 45 #define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16) 46 #define SUN4I_HDMI_VID_TIMING_POL_VSYNC BIT(1) 47 #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0) 48 49 #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n)) 50 51 #define SUN4I_HDMI_PAD_CTRL0_REG 0x200 52 #define SUN4I_HDMI_PAD_CTRL0_BIASEN BIT(31) 53 #define SUN4I_HDMI_PAD_CTRL0_LDOCEN BIT(30) 54 #define SUN4I_HDMI_PAD_CTRL0_LDODEN BIT(29) 55 #define SUN4I_HDMI_PAD_CTRL0_PWENC BIT(28) 56 #define SUN4I_HDMI_PAD_CTRL0_PWEND BIT(27) 57 #define SUN4I_HDMI_PAD_CTRL0_PWENG BIT(26) 58 #define SUN4I_HDMI_PAD_CTRL0_CKEN BIT(25) 59 #define SUN4I_HDMI_PAD_CTRL0_TXEN BIT(23) 60 61 #define SUN4I_HDMI_PAD_CTRL1_REG 0x204 62 #define SUN4I_HDMI_PAD_CTRL1_UNKNOWN BIT(24) /* set on A31 */ 63 #define SUN4I_HDMI_PAD_CTRL1_AMP_OPT BIT(23) 64 #define SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT BIT(22) 65 #define SUN4I_HDMI_PAD_CTRL1_EMP_OPT BIT(20) 66 #define SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT BIT(19) 67 #define SUN4I_HDMI_PAD_CTRL1_PWSCK BIT(18) 68 #define SUN4I_HDMI_PAD_CTRL1_PWSDT BIT(17) 69 #define SUN4I_HDMI_PAD_CTRL1_REG_DEN BIT(15) 70 #define SUN4I_HDMI_PAD_CTRL1_REG_DENCK BIT(14) 71 #define SUN4I_HDMI_PAD_CTRL1_REG_EMP(n) (((n) & 7) << 10) 72 #define SUN4I_HDMI_PAD_CTRL1_HALVE_CLK BIT(6) 73 #define SUN4I_HDMI_PAD_CTRL1_REG_AMP(n) (((n) & 7) << 3) 74 75 #define SUN4I_HDMI_PLL_CTRL_REG 0x208 76 #define SUN4I_HDMI_PLL_CTRL_PLL_EN BIT(31) 77 #define SUN4I_HDMI_PLL_CTRL_BWS BIT(30) 78 #define SUN4I_HDMI_PLL_CTRL_HV_IS_33 BIT(29) 79 #define SUN4I_HDMI_PLL_CTRL_LDO1_EN BIT(28) 80 #define SUN4I_HDMI_PLL_CTRL_LDO2_EN BIT(27) 81 #define SUN4I_HDMI_PLL_CTRL_SDIV2 BIT(25) 82 #define SUN4I_HDMI_PLL_CTRL_VCO_GAIN(n) (((n) & 7) << 20) 83 #define SUN4I_HDMI_PLL_CTRL_S(n) (((n) & 7) << 17) 84 #define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12) 85 #define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8) 86 #define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4) 87 #define SUN4I_HDMI_PLL_CTRL_DIV_MASK GENMASK(7, 4) 88 #define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf) 89 90 #define SUN4I_HDMI_PLL_DBG0_REG 0x20c 91 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT(n) (((n) & 1) << 21) 92 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_MASK BIT(21) 93 #define SUN4I_HDMI_PLL_DBG0_TMDS_PARENT_SHIFT 21 94 95 #define SUN4I_HDMI_CEC 0x214 96 #define SUN4I_HDMI_CEC_ENABLE BIT(11) 97 #define SUN4I_HDMI_CEC_TX BIT(9) 98 #define SUN4I_HDMI_CEC_RX BIT(8) 99 100 #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n))) 101 #define SUN4I_HDMI_PKT_CTRL_TYPE(n, t) ((t) << (((n) % 4) * 4)) 102 103 #define SUN4I_HDMI_UNKNOWN_REG 0x300 104 #define SUN4I_HDMI_UNKNOWN_INPUT_SYNC BIT(27) 105 106 #define SUN4I_HDMI_DDC_CTRL_REG 0x500 107 #define SUN4I_HDMI_DDC_CTRL_ENABLE BIT(31) 108 #define SUN4I_HDMI_DDC_CTRL_START_CMD BIT(30) 109 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_MASK BIT(8) 110 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_WRITE (1 << 8) 111 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8) 112 #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0) 113 114 #define SUN4I_HDMI_DDC_ADDR_REG 0x504 115 #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) 116 #define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) 117 #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) 118 #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff) 119 120 #define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c 121 #define SUN4I_HDMI_DDC_INT_STATUS_ILLEGAL_FIFO_OPERATION BIT(7) 122 #define SUN4I_HDMI_DDC_INT_STATUS_DDC_RX_FIFO_UNDERFLOW BIT(6) 123 #define SUN4I_HDMI_DDC_INT_STATUS_DDC_TX_FIFO_OVERFLOW BIT(5) 124 #define SUN4I_HDMI_DDC_INT_STATUS_FIFO_REQUEST BIT(4) 125 #define SUN4I_HDMI_DDC_INT_STATUS_ARBITRATION_ERROR BIT(3) 126 #define SUN4I_HDMI_DDC_INT_STATUS_ACK_ERROR BIT(2) 127 #define SUN4I_HDMI_DDC_INT_STATUS_BUS_ERROR BIT(1) 128 #define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0) 129 130 #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510 131 #define SUN4I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(31) 132 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4) 133 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MASK GENMASK(7, 4) 134 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES_MAX (BIT(4) - 1) 135 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf) 136 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0) 137 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MAX (BIT(4) - 1) 138 139 #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518 140 141 #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c 142 #define SUN4I_HDMI_DDC_BYTE_COUNT_MAX (BIT(10) - 1) 143 144 #define SUN4I_HDMI_DDC_CMD_REG 0x520 145 #define SUN4I_HDMI_DDC_CMD_EXPLICIT_EDDC_READ 6 146 #define SUN4I_HDMI_DDC_CMD_IMPLICIT_READ 5 147 #define SUN4I_HDMI_DDC_CMD_IMPLICIT_WRITE 3 148 149 #define SUN4I_HDMI_DDC_CLK_REG 0x528 150 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0x7) << 3) 151 #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7) 152 153 #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540 154 #define SUN4I_HDMI_DDC_LINE_CTRL_SDA_ENABLE BIT(9) 155 #define SUN4I_HDMI_DDC_LINE_CTRL_SCL_ENABLE BIT(8) 156 157 #define SUN4I_HDMI_DDC_FIFO_SIZE 16 158 159 /* A31 specific */ 160 #define SUN6I_HDMI_DDC_CTRL_REG 0x500 161 #define SUN6I_HDMI_DDC_CTRL_RESET BIT(31) 162 #define SUN6I_HDMI_DDC_CTRL_START_CMD BIT(27) 163 #define SUN6I_HDMI_DDC_CTRL_SDA_ENABLE BIT(6) 164 #define SUN6I_HDMI_DDC_CTRL_SCL_ENABLE BIT(4) 165 #define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0) 166 167 #define SUN6I_HDMI_DDC_CMD_REG 0x508 168 #define SUN6I_HDMI_DDC_CMD_BYTE_COUNT(count) ((count) << 16) 169 /* command types in lower 3 bits are the same as sun4i */ 170 171 #define SUN6I_HDMI_DDC_ADDR_REG 0x50c 172 #define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24) 173 #define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16) 174 #define SUN6I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8) 175 #define SUN6I_HDMI_DDC_ADDR_SLAVE(addr) (((addr) & 0xff) << 1) 176 177 #define SUN6I_HDMI_DDC_INT_STATUS_REG 0x514 178 #define SUN6I_HDMI_DDC_INT_STATUS_TIMEOUT BIT(8) 179 /* lower 8 bits are the same as sun4i */ 180 181 #define SUN6I_HDMI_DDC_FIFO_CTRL_REG 0x518 182 #define SUN6I_HDMI_DDC_FIFO_CTRL_CLEAR BIT(15) 183 /* lower 9 bits are the same as sun4i */ 184 185 #define SUN6I_HDMI_DDC_CLK_REG 0x520 186 /* DDC CLK bit fields are the same, but the formula is not */ 187 188 #define SUN6I_HDMI_DDC_FIFO_DATA_REG 0x580 189 190 enum sun4i_hdmi_pkt_type { 191 SUN4I_HDMI_PKT_AVI = 2, 192 SUN4I_HDMI_PKT_END = 15, 193 }; 194 195 struct sun4i_hdmi_variant { 196 bool has_ddc_parent_clk; 197 bool has_reset_control; 198 199 u32 pad_ctrl0_init_val; 200 u32 pad_ctrl1_init_val; 201 u32 pll_ctrl_init_val; 202 203 struct reg_field ddc_clk_reg; 204 u8 ddc_clk_pre_divider; 205 u8 ddc_clk_m_offset; 206 207 u8 tmds_clk_div_offset; 208 209 /* Register fields for I2C adapter */ 210 struct reg_field field_ddc_en; 211 struct reg_field field_ddc_start; 212 struct reg_field field_ddc_reset; 213 struct reg_field field_ddc_addr_reg; 214 struct reg_field field_ddc_slave_addr; 215 struct reg_field field_ddc_int_mask; 216 struct reg_field field_ddc_int_status; 217 struct reg_field field_ddc_fifo_clear; 218 struct reg_field field_ddc_fifo_rx_thres; 219 struct reg_field field_ddc_fifo_tx_thres; 220 struct reg_field field_ddc_byte_count; 221 struct reg_field field_ddc_cmd; 222 struct reg_field field_ddc_sda_en; 223 struct reg_field field_ddc_sck_en; 224 225 /* DDC FIFO register offset */ 226 u32 ddc_fifo_reg; 227 228 /* 229 * DDC FIFO threshold boundary conditions 230 * 231 * This is used to cope with the threshold boundary condition 232 * being slightly different on sun5i and sun6i. 233 * 234 * On sun5i the threshold is exclusive, i.e. does not include, 235 * the value of the threshold. ( > for RX; < for TX ) 236 * On sun6i the threshold is inclusive, i.e. includes, the 237 * value of the threshold. ( >= for RX; <= for TX ) 238 */ 239 bool ddc_fifo_thres_incl; 240 241 bool ddc_fifo_has_dir; 242 }; 243 244 struct sun4i_hdmi { 245 struct drm_connector connector; 246 struct drm_encoder encoder; 247 struct device *dev; 248 249 void __iomem *base; 250 struct regmap *regmap; 251 252 /* Reset control */ 253 struct reset_control *reset; 254 255 /* Parent clocks */ 256 struct clk *bus_clk; 257 struct clk *mod_clk; 258 struct clk *ddc_parent_clk; 259 struct clk *pll0_clk; 260 struct clk *pll1_clk; 261 262 /* And the clocks we create */ 263 struct clk *ddc_clk; 264 struct clk *tmds_clk; 265 266 struct i2c_adapter *i2c; 267 268 /* Regmap fields for I2C adapter */ 269 struct regmap_field *field_ddc_en; 270 struct regmap_field *field_ddc_start; 271 struct regmap_field *field_ddc_reset; 272 struct regmap_field *field_ddc_addr_reg; 273 struct regmap_field *field_ddc_slave_addr; 274 struct regmap_field *field_ddc_int_mask; 275 struct regmap_field *field_ddc_int_status; 276 struct regmap_field *field_ddc_fifo_clear; 277 struct regmap_field *field_ddc_fifo_rx_thres; 278 struct regmap_field *field_ddc_fifo_tx_thres; 279 struct regmap_field *field_ddc_byte_count; 280 struct regmap_field *field_ddc_cmd; 281 struct regmap_field *field_ddc_sda_en; 282 struct regmap_field *field_ddc_sck_en; 283 284 struct sun4i_drv *drv; 285 286 bool hdmi_monitor; 287 struct cec_adapter *cec_adap; 288 289 const struct sun4i_hdmi_variant *variant; 290 }; 291 292 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *clk); 293 int sun4i_tmds_create(struct sun4i_hdmi *hdmi); 294 int sun4i_hdmi_i2c_create(struct device *dev, struct sun4i_hdmi *hdmi); 295 296 #endif /* _SUN4I_HDMI_H_ */ 297