1 /* 2 * Copyright (C) 2015 Free Electrons 3 * Copyright (C) 2015 NextThing Co 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_crtc_helper.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_gem_cma_helper.h> 20 #include <drm/drm_plane_helper.h> 21 22 #include <linux/component.h> 23 #include <linux/list.h> 24 #include <linux/of_device.h> 25 #include <linux/of_graph.h> 26 #include <linux/reset.h> 27 28 #include "sun4i_backend.h" 29 #include "sun4i_drv.h" 30 #include "sun4i_frontend.h" 31 #include "sun4i_layer.h" 32 #include "sunxi_engine.h" 33 34 struct sun4i_backend_quirks { 35 /* backend <-> TCON muxing selection done in backend */ 36 bool needs_output_muxing; 37 38 /* alpha at the lowest z position is not always supported */ 39 bool supports_lowest_plane_alpha; 40 }; 41 42 static const u32 sunxi_rgb2yuv_coef[12] = { 43 0x00000107, 0x00000204, 0x00000064, 0x00000108, 44 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808, 45 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808 46 }; 47 48 /* 49 * These coefficients are taken from the A33 BSP from Allwinner. 50 * 51 * The formula is for each component, each coefficient being multiplied by 52 * 1024 and each constant being multiplied by 16: 53 * G = 1.164 * Y - 0.391 * U - 0.813 * V + 135 54 * R = 1.164 * Y + 1.596 * V - 222 55 * B = 1.164 * Y + 2.018 * U + 276 56 * 57 * This seems to be a conversion from Y[16:235] UV[16:240] to RGB[0:255], 58 * following the BT601 spec. 59 */ 60 static const u32 sunxi_bt601_yuv2rgb_coef[12] = { 61 0x000004a7, 0x00001e6f, 0x00001cbf, 0x00000877, 62 0x000004a7, 0x00000000, 0x00000662, 0x00003211, 63 0x000004a7, 0x00000812, 0x00000000, 0x00002eb1, 64 }; 65 66 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) 67 { 68 int i; 69 70 DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n"); 71 72 /* Set color correction */ 73 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, 74 SUN4I_BACKEND_OCCTL_ENABLE); 75 76 for (i = 0; i < 12; i++) 77 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), 78 sunxi_rgb2yuv_coef[i]); 79 } 80 81 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine) 82 { 83 DRM_DEBUG_DRIVER("Disabling color correction\n"); 84 85 /* Disable color correction */ 86 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, 87 SUN4I_BACKEND_OCCTL_ENABLE, 0); 88 } 89 90 static void sun4i_backend_commit(struct sunxi_engine *engine) 91 { 92 DRM_DEBUG_DRIVER("Committing changes\n"); 93 94 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, 95 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS | 96 SUN4I_BACKEND_REGBUFFCTL_LOADCTL); 97 } 98 99 void sun4i_backend_layer_enable(struct sun4i_backend *backend, 100 int layer, bool enable) 101 { 102 u32 val; 103 104 DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis", 105 layer); 106 107 if (enable) 108 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); 109 else 110 val = 0; 111 112 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, 113 SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); 114 } 115 116 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode) 117 { 118 switch (format) { 119 case DRM_FORMAT_ARGB8888: 120 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888; 121 break; 122 123 case DRM_FORMAT_ARGB4444: 124 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444; 125 break; 126 127 case DRM_FORMAT_ARGB1555: 128 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555; 129 break; 130 131 case DRM_FORMAT_RGBA5551: 132 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551; 133 break; 134 135 case DRM_FORMAT_RGBA4444: 136 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444; 137 break; 138 139 case DRM_FORMAT_XRGB8888: 140 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888; 141 break; 142 143 case DRM_FORMAT_RGB888: 144 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888; 145 break; 146 147 case DRM_FORMAT_RGB565: 148 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565; 149 break; 150 151 default: 152 return -EINVAL; 153 } 154 155 return 0; 156 } 157 158 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend, 159 int layer, struct drm_plane *plane) 160 { 161 struct drm_plane_state *state = plane->state; 162 163 DRM_DEBUG_DRIVER("Updating layer %d\n", layer); 164 165 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 166 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", 167 state->crtc_w, state->crtc_h); 168 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG, 169 SUN4I_BACKEND_DISSIZE(state->crtc_w, 170 state->crtc_h)); 171 } 172 173 /* Set height and width */ 174 DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n", 175 state->crtc_w, state->crtc_h); 176 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer), 177 SUN4I_BACKEND_LAYSIZE(state->crtc_w, 178 state->crtc_h)); 179 180 /* Set base coordinates */ 181 DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n", 182 state->crtc_x, state->crtc_y); 183 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer), 184 SUN4I_BACKEND_LAYCOOR(state->crtc_x, 185 state->crtc_y)); 186 187 return 0; 188 } 189 190 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend, 191 int layer, struct drm_plane *plane) 192 { 193 struct drm_plane_state *state = plane->state; 194 struct drm_framebuffer *fb = state->fb; 195 const struct drm_format_info *format = fb->format; 196 const uint32_t fmt = format->format; 197 u32 val = SUN4I_BACKEND_IYUVCTL_EN; 198 int i; 199 200 for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++) 201 regmap_write(backend->engine.regs, 202 SUN4I_BACKEND_YGCOEF_REG(i), 203 sunxi_bt601_yuv2rgb_coef[i]); 204 205 /* 206 * We should do that only for a single plane, but the 207 * framebuffer's atomic_check has our back on this. 208 */ 209 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), 210 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 211 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN); 212 213 /* TODO: Add support for the multi-planar YUV formats */ 214 if (format->num_planes == 1) 215 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422; 216 else 217 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt); 218 219 /* 220 * Allwinner seems to list the pixel sequence from right to left, while 221 * DRM lists it from left to right. 222 */ 223 switch (fmt) { 224 case DRM_FORMAT_YUYV: 225 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY; 226 break; 227 case DRM_FORMAT_YVYU: 228 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY; 229 break; 230 case DRM_FORMAT_UYVY: 231 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU; 232 break; 233 case DRM_FORMAT_VYUY: 234 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV; 235 break; 236 default: 237 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n", 238 fmt); 239 } 240 241 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val); 242 243 return 0; 244 } 245 246 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, 247 int layer, struct drm_plane *plane) 248 { 249 struct drm_plane_state *state = plane->state; 250 struct drm_framebuffer *fb = state->fb; 251 bool interlaced = false; 252 u32 val; 253 int ret; 254 255 /* Clear the YUV mode */ 256 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), 257 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); 258 259 if (plane->state->crtc) 260 interlaced = plane->state->crtc->state->adjusted_mode.flags 261 & DRM_MODE_FLAG_INTERLACE; 262 263 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, 264 SUN4I_BACKEND_MODCTL_ITLMOD_EN, 265 interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); 266 267 DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", 268 interlaced ? "on" : "off"); 269 270 val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8); 271 if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) 272 val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; 273 regmap_update_bits(backend->engine.regs, 274 SUN4I_BACKEND_ATTCTL_REG0(layer), 275 SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK | 276 SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN, 277 val); 278 279 if (fb->format->is_yuv) 280 return sun4i_backend_update_yuv_format(backend, layer, plane); 281 282 ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val); 283 if (ret) { 284 DRM_DEBUG_DRIVER("Invalid format\n"); 285 return ret; 286 } 287 288 regmap_update_bits(backend->engine.regs, 289 SUN4I_BACKEND_ATTCTL_REG1(layer), 290 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); 291 292 return 0; 293 } 294 295 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, 296 int layer, uint32_t fmt) 297 { 298 u32 val; 299 int ret; 300 301 ret = sun4i_backend_drm_format_to_layer(fmt, &val); 302 if (ret) { 303 DRM_DEBUG_DRIVER("Invalid format\n"); 304 return ret; 305 } 306 307 regmap_update_bits(backend->engine.regs, 308 SUN4I_BACKEND_ATTCTL_REG0(layer), 309 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN, 310 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN); 311 312 regmap_update_bits(backend->engine.regs, 313 SUN4I_BACKEND_ATTCTL_REG1(layer), 314 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); 315 316 return 0; 317 } 318 319 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend, 320 struct drm_framebuffer *fb, 321 dma_addr_t paddr) 322 { 323 /* TODO: Add support for the multi-planar YUV formats */ 324 DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr); 325 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr); 326 327 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); 328 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0), 329 fb->pitches[0] * 8); 330 331 return 0; 332 } 333 334 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, 335 int layer, struct drm_plane *plane) 336 { 337 struct drm_plane_state *state = plane->state; 338 struct drm_framebuffer *fb = state->fb; 339 u32 lo_paddr, hi_paddr; 340 dma_addr_t paddr; 341 342 /* Set the line width */ 343 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); 344 regmap_write(backend->engine.regs, 345 SUN4I_BACKEND_LAYLINEWIDTH_REG(layer), 346 fb->pitches[0] * 8); 347 348 /* Get the start of the displayed memory */ 349 paddr = drm_fb_cma_get_gem_addr(fb, state, 0); 350 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); 351 352 /* 353 * backend DMA accesses DRAM directly, bypassing the system 354 * bus. As such, the address range is different and the buffer 355 * address needs to be corrected. 356 */ 357 paddr -= PHYS_OFFSET; 358 359 if (fb->format->is_yuv) 360 return sun4i_backend_update_yuv_buffer(backend, fb, paddr); 361 362 /* Write the 32 lower bits of the address (in bits) */ 363 lo_paddr = paddr << 3; 364 DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr); 365 regmap_write(backend->engine.regs, 366 SUN4I_BACKEND_LAYFB_L32ADD_REG(layer), 367 lo_paddr); 368 369 /* And the upper bits */ 370 hi_paddr = paddr >> 29; 371 DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr); 372 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG, 373 SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer), 374 SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr)); 375 376 return 0; 377 } 378 379 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, 380 struct drm_plane *plane) 381 { 382 struct drm_plane_state *state = plane->state; 383 struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state); 384 unsigned int priority = state->normalized_zpos; 385 unsigned int pipe = p_state->pipe; 386 387 DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n", 388 layer, priority, pipe); 389 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), 390 SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK | 391 SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK, 392 SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) | 393 SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority)); 394 395 return 0; 396 } 397 398 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state) 399 { 400 u16 src_h = state->src_h >> 16; 401 u16 src_w = state->src_w >> 16; 402 403 DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n", 404 src_w, src_h, state->crtc_w, state->crtc_h); 405 406 if ((state->crtc_h != src_h) || (state->crtc_w != src_w)) 407 return true; 408 409 return false; 410 } 411 412 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state) 413 { 414 struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); 415 struct sun4i_backend *backend = layer->backend; 416 417 if (IS_ERR(backend->frontend)) 418 return false; 419 420 return sun4i_backend_plane_uses_scaler(state); 421 } 422 423 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine, 424 struct drm_crtc_state *old_state) 425 { 426 u32 val; 427 428 WARN_ON(regmap_read_poll_timeout(engine->regs, 429 SUN4I_BACKEND_REGBUFFCTL_REG, 430 val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL), 431 100, 50000)); 432 } 433 434 static int sun4i_backend_atomic_check(struct sunxi_engine *engine, 435 struct drm_crtc_state *crtc_state) 436 { 437 struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; 438 struct sun4i_backend *backend = engine_to_sun4i_backend(engine); 439 struct drm_atomic_state *state = crtc_state->state; 440 struct drm_device *drm = state->dev; 441 struct drm_plane *plane; 442 unsigned int num_planes = 0; 443 unsigned int num_alpha_planes = 0; 444 unsigned int num_frontend_planes = 0; 445 unsigned int num_alpha_planes_max = 1; 446 unsigned int num_yuv_planes = 0; 447 unsigned int current_pipe = 0; 448 unsigned int i; 449 450 DRM_DEBUG_DRIVER("Starting checking our planes\n"); 451 452 if (!crtc_state->planes_changed) 453 return 0; 454 455 drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { 456 struct drm_plane_state *plane_state = 457 drm_atomic_get_plane_state(state, plane); 458 struct sun4i_layer_state *layer_state = 459 state_to_sun4i_layer_state(plane_state); 460 struct drm_framebuffer *fb = plane_state->fb; 461 struct drm_format_name_buf format_name; 462 463 if (sun4i_backend_plane_uses_frontend(plane_state)) { 464 DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", 465 plane->index); 466 467 layer_state->uses_frontend = true; 468 num_frontend_planes++; 469 } else { 470 layer_state->uses_frontend = false; 471 } 472 473 DRM_DEBUG_DRIVER("Plane FB format is %s\n", 474 drm_get_format_name(fb->format->format, 475 &format_name)); 476 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) 477 num_alpha_planes++; 478 479 if (fb->format->is_yuv) { 480 DRM_DEBUG_DRIVER("Plane FB format is YUV\n"); 481 num_yuv_planes++; 482 } 483 484 DRM_DEBUG_DRIVER("Plane zpos is %d\n", 485 plane_state->normalized_zpos); 486 487 /* Sort our planes by Zpos */ 488 plane_states[plane_state->normalized_zpos] = plane_state; 489 490 num_planes++; 491 } 492 493 /* All our planes were disabled, bail out */ 494 if (!num_planes) 495 return 0; 496 497 /* 498 * The hardware is a bit unusual here. 499 * 500 * Even though it supports 4 layers, it does the composition 501 * in two separate steps. 502 * 503 * The first one is assigning a layer to one of its two 504 * pipes. If more that 1 layer is assigned to the same pipe, 505 * and if pixels overlaps, the pipe will take the pixel from 506 * the layer with the highest priority. 507 * 508 * The second step is the actual alpha blending, that takes 509 * the two pipes as input, and uses the potential alpha 510 * component to do the transparency between the two. 511 * 512 * This two-step scenario makes us unable to guarantee a 513 * robust alpha blending between the 4 layers in all 514 * situations, since this means that we need to have one layer 515 * with alpha at the lowest position of our two pipes. 516 * 517 * However, we cannot even do that on every platform, since 518 * the hardware has a bug where the lowest plane of the lowest 519 * pipe (pipe 0, priority 0), if it has any alpha, will 520 * discard the pixel data entirely and just display the pixels 521 * in the background color (black by default). 522 * 523 * This means that on the affected platforms, we effectively 524 * have only three valid configurations with alpha, all of 525 * them with the alpha being on pipe1 with the lowest 526 * position, which can be 1, 2 or 3 depending on the number of 527 * planes and their zpos. 528 */ 529 530 /* For platforms that are not affected by the issue described above. */ 531 if (backend->quirks->supports_lowest_plane_alpha) 532 num_alpha_planes_max++; 533 534 if (num_alpha_planes > num_alpha_planes_max) { 535 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n"); 536 return -EINVAL; 537 } 538 539 /* We can't have an alpha plane at the lowest position */ 540 if (!backend->quirks->supports_lowest_plane_alpha && 541 (plane_states[0]->fb->format->has_alpha || 542 (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))) 543 return -EINVAL; 544 545 for (i = 1; i < num_planes; i++) { 546 struct drm_plane_state *p_state = plane_states[i]; 547 struct drm_framebuffer *fb = p_state->fb; 548 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state); 549 550 /* 551 * The only alpha position is the lowest plane of the 552 * second pipe. 553 */ 554 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) 555 current_pipe++; 556 557 s_state->pipe = current_pipe; 558 } 559 560 /* We can only have a single YUV plane at a time */ 561 if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) { 562 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n"); 563 return -EINVAL; 564 } 565 566 if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { 567 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n"); 568 return -EINVAL; 569 } 570 571 DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n", 572 num_planes, num_alpha_planes, num_frontend_planes, 573 num_yuv_planes); 574 575 return 0; 576 } 577 578 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine) 579 { 580 struct sun4i_backend *backend = engine_to_sun4i_backend(engine); 581 struct sun4i_frontend *frontend = backend->frontend; 582 583 if (!frontend) 584 return; 585 586 /* 587 * In a teardown scenario with the frontend involved, we have 588 * to keep the frontend enabled until the next vblank, and 589 * only then disable it. 590 * 591 * This is due to the fact that the backend will not take into 592 * account the new configuration (with the plane that used to 593 * be fed by the frontend now disabled) until we write to the 594 * commit bit and the hardware fetches the new configuration 595 * during the next vblank. 596 * 597 * So we keep the frontend around in order to prevent any 598 * visual artifacts. 599 */ 600 spin_lock(&backend->frontend_lock); 601 if (backend->frontend_teardown) { 602 sun4i_frontend_exit(frontend); 603 backend->frontend_teardown = false; 604 } 605 spin_unlock(&backend->frontend_lock); 606 }; 607 608 static int sun4i_backend_init_sat(struct device *dev) { 609 struct sun4i_backend *backend = dev_get_drvdata(dev); 610 int ret; 611 612 backend->sat_reset = devm_reset_control_get(dev, "sat"); 613 if (IS_ERR(backend->sat_reset)) { 614 dev_err(dev, "Couldn't get the SAT reset line\n"); 615 return PTR_ERR(backend->sat_reset); 616 } 617 618 ret = reset_control_deassert(backend->sat_reset); 619 if (ret) { 620 dev_err(dev, "Couldn't deassert the SAT reset line\n"); 621 return ret; 622 } 623 624 backend->sat_clk = devm_clk_get(dev, "sat"); 625 if (IS_ERR(backend->sat_clk)) { 626 dev_err(dev, "Couldn't get our SAT clock\n"); 627 ret = PTR_ERR(backend->sat_clk); 628 goto err_assert_reset; 629 } 630 631 ret = clk_prepare_enable(backend->sat_clk); 632 if (ret) { 633 dev_err(dev, "Couldn't enable the SAT clock\n"); 634 return ret; 635 } 636 637 return 0; 638 639 err_assert_reset: 640 reset_control_assert(backend->sat_reset); 641 return ret; 642 } 643 644 static int sun4i_backend_free_sat(struct device *dev) { 645 struct sun4i_backend *backend = dev_get_drvdata(dev); 646 647 clk_disable_unprepare(backend->sat_clk); 648 reset_control_assert(backend->sat_reset); 649 650 return 0; 651 } 652 653 /* 654 * The display backend can take video output from the display frontend, or 655 * the display enhancement unit on the A80, as input for one it its layers. 656 * This relationship within the display pipeline is encoded in the device 657 * tree with of_graph, and we use it here to figure out which backend, if 658 * there are 2 or more, we are currently probing. The number would be in 659 * the "reg" property of the upstream output port endpoint. 660 */ 661 static int sun4i_backend_of_get_id(struct device_node *node) 662 { 663 struct device_node *port, *ep; 664 int ret = -EINVAL; 665 666 /* input is port 0 */ 667 port = of_graph_get_port_by_id(node, 0); 668 if (!port) 669 return -EINVAL; 670 671 /* try finding an upstream endpoint */ 672 for_each_available_child_of_node(port, ep) { 673 struct device_node *remote; 674 u32 reg; 675 676 remote = of_graph_get_remote_endpoint(ep); 677 if (!remote) 678 continue; 679 680 ret = of_property_read_u32(remote, "reg", ®); 681 if (ret) 682 continue; 683 684 ret = reg; 685 } 686 687 of_node_put(port); 688 689 return ret; 690 } 691 692 /* TODO: This needs to take multiple pipelines into account */ 693 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv, 694 struct device_node *node) 695 { 696 struct device_node *port, *ep, *remote; 697 struct sun4i_frontend *frontend; 698 699 port = of_graph_get_port_by_id(node, 0); 700 if (!port) 701 return ERR_PTR(-EINVAL); 702 703 for_each_available_child_of_node(port, ep) { 704 remote = of_graph_get_remote_port_parent(ep); 705 if (!remote) 706 continue; 707 708 /* does this node match any registered engines? */ 709 list_for_each_entry(frontend, &drv->frontend_list, list) { 710 if (remote == frontend->node) { 711 of_node_put(remote); 712 of_node_put(port); 713 return frontend; 714 } 715 } 716 } 717 718 return ERR_PTR(-EINVAL); 719 } 720 721 static const struct sunxi_engine_ops sun4i_backend_engine_ops = { 722 .atomic_begin = sun4i_backend_atomic_begin, 723 .atomic_check = sun4i_backend_atomic_check, 724 .commit = sun4i_backend_commit, 725 .layers_init = sun4i_layers_init, 726 .apply_color_correction = sun4i_backend_apply_color_correction, 727 .disable_color_correction = sun4i_backend_disable_color_correction, 728 .vblank_quirk = sun4i_backend_vblank_quirk, 729 }; 730 731 static struct regmap_config sun4i_backend_regmap_config = { 732 .reg_bits = 32, 733 .val_bits = 32, 734 .reg_stride = 4, 735 .max_register = 0x5800, 736 }; 737 738 static int sun4i_backend_bind(struct device *dev, struct device *master, 739 void *data) 740 { 741 struct platform_device *pdev = to_platform_device(dev); 742 struct drm_device *drm = data; 743 struct sun4i_drv *drv = drm->dev_private; 744 struct sun4i_backend *backend; 745 const struct sun4i_backend_quirks *quirks; 746 struct resource *res; 747 void __iomem *regs; 748 int i, ret; 749 750 backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL); 751 if (!backend) 752 return -ENOMEM; 753 dev_set_drvdata(dev, backend); 754 spin_lock_init(&backend->frontend_lock); 755 756 backend->engine.node = dev->of_node; 757 backend->engine.ops = &sun4i_backend_engine_ops; 758 backend->engine.id = sun4i_backend_of_get_id(dev->of_node); 759 if (backend->engine.id < 0) 760 return backend->engine.id; 761 762 backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node); 763 if (IS_ERR(backend->frontend)) 764 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n"); 765 766 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 767 regs = devm_ioremap_resource(dev, res); 768 if (IS_ERR(regs)) 769 return PTR_ERR(regs); 770 771 backend->reset = devm_reset_control_get(dev, NULL); 772 if (IS_ERR(backend->reset)) { 773 dev_err(dev, "Couldn't get our reset line\n"); 774 return PTR_ERR(backend->reset); 775 } 776 777 ret = reset_control_deassert(backend->reset); 778 if (ret) { 779 dev_err(dev, "Couldn't deassert our reset line\n"); 780 return ret; 781 } 782 783 backend->bus_clk = devm_clk_get(dev, "ahb"); 784 if (IS_ERR(backend->bus_clk)) { 785 dev_err(dev, "Couldn't get the backend bus clock\n"); 786 ret = PTR_ERR(backend->bus_clk); 787 goto err_assert_reset; 788 } 789 clk_prepare_enable(backend->bus_clk); 790 791 backend->mod_clk = devm_clk_get(dev, "mod"); 792 if (IS_ERR(backend->mod_clk)) { 793 dev_err(dev, "Couldn't get the backend module clock\n"); 794 ret = PTR_ERR(backend->mod_clk); 795 goto err_disable_bus_clk; 796 } 797 clk_prepare_enable(backend->mod_clk); 798 799 backend->ram_clk = devm_clk_get(dev, "ram"); 800 if (IS_ERR(backend->ram_clk)) { 801 dev_err(dev, "Couldn't get the backend RAM clock\n"); 802 ret = PTR_ERR(backend->ram_clk); 803 goto err_disable_mod_clk; 804 } 805 clk_prepare_enable(backend->ram_clk); 806 807 if (of_device_is_compatible(dev->of_node, 808 "allwinner,sun8i-a33-display-backend")) { 809 ret = sun4i_backend_init_sat(dev); 810 if (ret) { 811 dev_err(dev, "Couldn't init SAT resources\n"); 812 goto err_disable_ram_clk; 813 } 814 } 815 816 backend->engine.regs = devm_regmap_init_mmio(dev, regs, 817 &sun4i_backend_regmap_config); 818 if (IS_ERR(backend->engine.regs)) { 819 dev_err(dev, "Couldn't create the backend regmap\n"); 820 return PTR_ERR(backend->engine.regs); 821 } 822 823 list_add_tail(&backend->engine.list, &drv->engine_list); 824 825 /* 826 * Many of the backend's layer configuration registers have 827 * undefined default values. This poses a risk as we use 828 * regmap_update_bits in some places, and don't overwrite 829 * the whole register. 830 * 831 * Clear the registers here to have something predictable. 832 */ 833 for (i = 0x800; i < 0x1000; i += 4) 834 regmap_write(backend->engine.regs, i, 0); 835 836 /* Disable registers autoloading */ 837 regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG, 838 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS); 839 840 /* Enable the backend */ 841 regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, 842 SUN4I_BACKEND_MODCTL_DEBE_EN | 843 SUN4I_BACKEND_MODCTL_START_CTL); 844 845 /* Set output selection if needed */ 846 quirks = of_device_get_match_data(dev); 847 if (quirks->needs_output_muxing) { 848 /* 849 * We assume there is no dynamic muxing of backends 850 * and TCONs, so we select the backend with same ID. 851 * 852 * While dynamic selection might be interesting, since 853 * the CRTC is tied to the TCON, while the layers are 854 * tied to the backends, this means, we will need to 855 * switch between groups of layers. There might not be 856 * a way to represent this constraint in DRM. 857 */ 858 regmap_update_bits(backend->engine.regs, 859 SUN4I_BACKEND_MODCTL_REG, 860 SUN4I_BACKEND_MODCTL_OUT_SEL, 861 (backend->engine.id 862 ? SUN4I_BACKEND_MODCTL_OUT_LCD1 863 : SUN4I_BACKEND_MODCTL_OUT_LCD0)); 864 } 865 866 backend->quirks = quirks; 867 868 return 0; 869 870 err_disable_ram_clk: 871 clk_disable_unprepare(backend->ram_clk); 872 err_disable_mod_clk: 873 clk_disable_unprepare(backend->mod_clk); 874 err_disable_bus_clk: 875 clk_disable_unprepare(backend->bus_clk); 876 err_assert_reset: 877 reset_control_assert(backend->reset); 878 return ret; 879 } 880 881 static void sun4i_backend_unbind(struct device *dev, struct device *master, 882 void *data) 883 { 884 struct sun4i_backend *backend = dev_get_drvdata(dev); 885 886 list_del(&backend->engine.list); 887 888 if (of_device_is_compatible(dev->of_node, 889 "allwinner,sun8i-a33-display-backend")) 890 sun4i_backend_free_sat(dev); 891 892 clk_disable_unprepare(backend->ram_clk); 893 clk_disable_unprepare(backend->mod_clk); 894 clk_disable_unprepare(backend->bus_clk); 895 reset_control_assert(backend->reset); 896 } 897 898 static const struct component_ops sun4i_backend_ops = { 899 .bind = sun4i_backend_bind, 900 .unbind = sun4i_backend_unbind, 901 }; 902 903 static int sun4i_backend_probe(struct platform_device *pdev) 904 { 905 return component_add(&pdev->dev, &sun4i_backend_ops); 906 } 907 908 static int sun4i_backend_remove(struct platform_device *pdev) 909 { 910 component_del(&pdev->dev, &sun4i_backend_ops); 911 912 return 0; 913 } 914 915 static const struct sun4i_backend_quirks sun4i_backend_quirks = { 916 .needs_output_muxing = true, 917 }; 918 919 static const struct sun4i_backend_quirks sun5i_backend_quirks = { 920 }; 921 922 static const struct sun4i_backend_quirks sun6i_backend_quirks = { 923 }; 924 925 static const struct sun4i_backend_quirks sun7i_backend_quirks = { 926 .needs_output_muxing = true, 927 .supports_lowest_plane_alpha = true, 928 }; 929 930 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = { 931 .supports_lowest_plane_alpha = true, 932 }; 933 934 static const struct sun4i_backend_quirks sun9i_backend_quirks = { 935 }; 936 937 static const struct of_device_id sun4i_backend_of_table[] = { 938 { 939 .compatible = "allwinner,sun4i-a10-display-backend", 940 .data = &sun4i_backend_quirks, 941 }, 942 { 943 .compatible = "allwinner,sun5i-a13-display-backend", 944 .data = &sun5i_backend_quirks, 945 }, 946 { 947 .compatible = "allwinner,sun6i-a31-display-backend", 948 .data = &sun6i_backend_quirks, 949 }, 950 { 951 .compatible = "allwinner,sun7i-a20-display-backend", 952 .data = &sun7i_backend_quirks, 953 }, 954 { 955 .compatible = "allwinner,sun8i-a33-display-backend", 956 .data = &sun8i_a33_backend_quirks, 957 }, 958 { 959 .compatible = "allwinner,sun9i-a80-display-backend", 960 .data = &sun9i_backend_quirks, 961 }, 962 { } 963 }; 964 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table); 965 966 static struct platform_driver sun4i_backend_platform_driver = { 967 .probe = sun4i_backend_probe, 968 .remove = sun4i_backend_remove, 969 .driver = { 970 .name = "sun4i-backend", 971 .of_match_table = sun4i_backend_of_table, 972 }, 973 }; 974 module_platform_driver(sun4i_backend_platform_driver); 975 976 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 977 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver"); 978 MODULE_LICENSE("GPL"); 979