1 /* 2 * Copyright (C) 2015 Free Electrons 3 * Copyright (C) 2015 NextThing Co 4 * 5 * Maxime Ripard <maxime.ripard@free-electrons.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU General Public License as 9 * published by the Free Software Foundation; either version 2 of 10 * the License, or (at your option) any later version. 11 */ 12 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_crtc.h> 17 #include <drm/drm_fb_cma_helper.h> 18 #include <drm/drm_gem_cma_helper.h> 19 #include <drm/drm_plane_helper.h> 20 #include <drm/drm_probe_helper.h> 21 22 #include <linux/component.h> 23 #include <linux/list.h> 24 #include <linux/of_device.h> 25 #include <linux/of_graph.h> 26 #include <linux/reset.h> 27 28 #include "sun4i_backend.h" 29 #include "sun4i_drv.h" 30 #include "sun4i_frontend.h" 31 #include "sun4i_layer.h" 32 #include "sunxi_engine.h" 33 34 struct sun4i_backend_quirks { 35 /* backend <-> TCON muxing selection done in backend */ 36 bool needs_output_muxing; 37 38 /* alpha at the lowest z position is not always supported */ 39 bool supports_lowest_plane_alpha; 40 }; 41 42 static const u32 sunxi_rgb2yuv_coef[12] = { 43 0x00000107, 0x00000204, 0x00000064, 0x00000108, 44 0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808, 45 0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808 46 }; 47 48 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine) 49 { 50 int i; 51 52 DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n"); 53 54 /* Set color correction */ 55 regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG, 56 SUN4I_BACKEND_OCCTL_ENABLE); 57 58 for (i = 0; i < 12; i++) 59 regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i), 60 sunxi_rgb2yuv_coef[i]); 61 } 62 63 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine) 64 { 65 DRM_DEBUG_DRIVER("Disabling color correction\n"); 66 67 /* Disable color correction */ 68 regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG, 69 SUN4I_BACKEND_OCCTL_ENABLE, 0); 70 } 71 72 static void sun4i_backend_commit(struct sunxi_engine *engine) 73 { 74 DRM_DEBUG_DRIVER("Committing changes\n"); 75 76 regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG, 77 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS | 78 SUN4I_BACKEND_REGBUFFCTL_LOADCTL); 79 } 80 81 void sun4i_backend_layer_enable(struct sun4i_backend *backend, 82 int layer, bool enable) 83 { 84 u32 val; 85 86 DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis", 87 layer); 88 89 if (enable) 90 val = SUN4I_BACKEND_MODCTL_LAY_EN(layer); 91 else 92 val = 0; 93 94 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, 95 SUN4I_BACKEND_MODCTL_LAY_EN(layer), val); 96 } 97 98 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode) 99 { 100 switch (format) { 101 case DRM_FORMAT_ARGB8888: 102 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888; 103 break; 104 105 case DRM_FORMAT_ARGB4444: 106 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444; 107 break; 108 109 case DRM_FORMAT_ARGB1555: 110 *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555; 111 break; 112 113 case DRM_FORMAT_RGBA5551: 114 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551; 115 break; 116 117 case DRM_FORMAT_RGBA4444: 118 *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444; 119 break; 120 121 case DRM_FORMAT_XRGB8888: 122 *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888; 123 break; 124 125 case DRM_FORMAT_RGB888: 126 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888; 127 break; 128 129 case DRM_FORMAT_RGB565: 130 *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565; 131 break; 132 133 default: 134 return -EINVAL; 135 } 136 137 return 0; 138 } 139 140 static const uint32_t sun4i_backend_formats[] = { 141 DRM_FORMAT_ARGB1555, 142 DRM_FORMAT_ARGB4444, 143 DRM_FORMAT_ARGB8888, 144 DRM_FORMAT_RGB565, 145 DRM_FORMAT_RGB888, 146 DRM_FORMAT_RGBA4444, 147 DRM_FORMAT_RGBA5551, 148 DRM_FORMAT_UYVY, 149 DRM_FORMAT_VYUY, 150 DRM_FORMAT_XRGB8888, 151 DRM_FORMAT_YUYV, 152 DRM_FORMAT_YVYU, 153 }; 154 155 bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier) 156 { 157 unsigned int i; 158 159 if (modifier != DRM_FORMAT_MOD_LINEAR) 160 return false; 161 162 for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++) 163 if (sun4i_backend_formats[i] == fmt) 164 return true; 165 166 return false; 167 } 168 169 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend, 170 int layer, struct drm_plane *plane) 171 { 172 struct drm_plane_state *state = plane->state; 173 174 DRM_DEBUG_DRIVER("Updating layer %d\n", layer); 175 176 if (plane->type == DRM_PLANE_TYPE_PRIMARY) { 177 DRM_DEBUG_DRIVER("Primary layer, updating global size W: %u H: %u\n", 178 state->crtc_w, state->crtc_h); 179 regmap_write(backend->engine.regs, SUN4I_BACKEND_DISSIZE_REG, 180 SUN4I_BACKEND_DISSIZE(state->crtc_w, 181 state->crtc_h)); 182 } 183 184 /* Set height and width */ 185 DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n", 186 state->crtc_w, state->crtc_h); 187 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer), 188 SUN4I_BACKEND_LAYSIZE(state->crtc_w, 189 state->crtc_h)); 190 191 /* Set base coordinates */ 192 DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n", 193 state->crtc_x, state->crtc_y); 194 regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer), 195 SUN4I_BACKEND_LAYCOOR(state->crtc_x, 196 state->crtc_y)); 197 198 return 0; 199 } 200 201 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend, 202 int layer, struct drm_plane *plane) 203 { 204 struct drm_plane_state *state = plane->state; 205 struct drm_framebuffer *fb = state->fb; 206 const struct drm_format_info *format = fb->format; 207 const uint32_t fmt = format->format; 208 u32 val = SUN4I_BACKEND_IYUVCTL_EN; 209 int i; 210 211 for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++) 212 regmap_write(backend->engine.regs, 213 SUN4I_BACKEND_YGCOEF_REG(i), 214 sunxi_bt601_yuv2rgb_coef[i]); 215 216 /* 217 * We should do that only for a single plane, but the 218 * framebuffer's atomic_check has our back on this. 219 */ 220 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), 221 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 222 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN); 223 224 /* TODO: Add support for the multi-planar YUV formats */ 225 if (drm_format_info_is_yuv_packed(format) && 226 drm_format_info_is_yuv_sampling_422(format)) 227 val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422; 228 else 229 DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt); 230 231 /* 232 * Allwinner seems to list the pixel sequence from right to left, while 233 * DRM lists it from left to right. 234 */ 235 switch (fmt) { 236 case DRM_FORMAT_YUYV: 237 val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY; 238 break; 239 case DRM_FORMAT_YVYU: 240 val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY; 241 break; 242 case DRM_FORMAT_UYVY: 243 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU; 244 break; 245 case DRM_FORMAT_VYUY: 246 val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV; 247 break; 248 default: 249 DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n", 250 fmt); 251 } 252 253 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val); 254 255 return 0; 256 } 257 258 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend, 259 int layer, struct drm_plane *plane) 260 { 261 struct drm_plane_state *state = plane->state; 262 struct drm_framebuffer *fb = state->fb; 263 bool interlaced = false; 264 u32 val; 265 int ret; 266 267 /* Clear the YUV mode */ 268 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), 269 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); 270 271 if (plane->state->crtc) 272 interlaced = plane->state->crtc->state->adjusted_mode.flags 273 & DRM_MODE_FLAG_INTERLACE; 274 275 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, 276 SUN4I_BACKEND_MODCTL_ITLMOD_EN, 277 interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0); 278 279 DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n", 280 interlaced ? "on" : "off"); 281 282 val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8); 283 if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) 284 val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN; 285 regmap_update_bits(backend->engine.regs, 286 SUN4I_BACKEND_ATTCTL_REG0(layer), 287 SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK | 288 SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN, 289 val); 290 291 if (fb->format->is_yuv) 292 return sun4i_backend_update_yuv_format(backend, layer, plane); 293 294 ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val); 295 if (ret) { 296 DRM_DEBUG_DRIVER("Invalid format\n"); 297 return ret; 298 } 299 300 regmap_update_bits(backend->engine.regs, 301 SUN4I_BACKEND_ATTCTL_REG1(layer), 302 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); 303 304 return 0; 305 } 306 307 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend, 308 int layer, uint32_t fmt) 309 { 310 u32 val; 311 int ret; 312 313 ret = sun4i_backend_drm_format_to_layer(fmt, &val); 314 if (ret) { 315 DRM_DEBUG_DRIVER("Invalid format\n"); 316 return ret; 317 } 318 319 regmap_update_bits(backend->engine.regs, 320 SUN4I_BACKEND_ATTCTL_REG0(layer), 321 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN, 322 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN); 323 324 regmap_update_bits(backend->engine.regs, 325 SUN4I_BACKEND_ATTCTL_REG1(layer), 326 SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val); 327 328 return 0; 329 } 330 331 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend, 332 struct drm_framebuffer *fb, 333 dma_addr_t paddr) 334 { 335 /* TODO: Add support for the multi-planar YUV formats */ 336 DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr); 337 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr); 338 339 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); 340 regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0), 341 fb->pitches[0] * 8); 342 343 return 0; 344 } 345 346 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend, 347 int layer, struct drm_plane *plane) 348 { 349 struct drm_plane_state *state = plane->state; 350 struct drm_framebuffer *fb = state->fb; 351 u32 lo_paddr, hi_paddr; 352 dma_addr_t paddr; 353 354 /* Set the line width */ 355 DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8); 356 regmap_write(backend->engine.regs, 357 SUN4I_BACKEND_LAYLINEWIDTH_REG(layer), 358 fb->pitches[0] * 8); 359 360 /* Get the start of the displayed memory */ 361 paddr = drm_fb_cma_get_gem_addr(fb, state, 0); 362 DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr); 363 364 if (fb->format->is_yuv) 365 return sun4i_backend_update_yuv_buffer(backend, fb, paddr); 366 367 /* Write the 32 lower bits of the address (in bits) */ 368 lo_paddr = paddr << 3; 369 DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr); 370 regmap_write(backend->engine.regs, 371 SUN4I_BACKEND_LAYFB_L32ADD_REG(layer), 372 lo_paddr); 373 374 /* And the upper bits */ 375 hi_paddr = paddr >> 29; 376 DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr); 377 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG, 378 SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer), 379 SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr)); 380 381 return 0; 382 } 383 384 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer, 385 struct drm_plane *plane) 386 { 387 struct drm_plane_state *state = plane->state; 388 struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state); 389 unsigned int priority = state->normalized_zpos; 390 unsigned int pipe = p_state->pipe; 391 392 DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n", 393 layer, priority, pipe); 394 regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer), 395 SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK | 396 SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK, 397 SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) | 398 SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority)); 399 400 return 0; 401 } 402 403 void sun4i_backend_cleanup_layer(struct sun4i_backend *backend, 404 int layer) 405 { 406 regmap_update_bits(backend->engine.regs, 407 SUN4I_BACKEND_ATTCTL_REG0(layer), 408 SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN | 409 SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0); 410 } 411 412 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state) 413 { 414 u16 src_h = state->src_h >> 16; 415 u16 src_w = state->src_w >> 16; 416 417 DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n", 418 src_w, src_h, state->crtc_w, state->crtc_h); 419 420 if ((state->crtc_h != src_h) || (state->crtc_w != src_w)) 421 return true; 422 423 return false; 424 } 425 426 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state) 427 { 428 struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane); 429 struct sun4i_backend *backend = layer->backend; 430 uint32_t format = state->fb->format->format; 431 uint64_t modifier = state->fb->modifier; 432 433 if (IS_ERR(backend->frontend)) 434 return false; 435 436 if (!sun4i_frontend_format_is_supported(format, modifier)) 437 return false; 438 439 if (!sun4i_backend_format_is_supported(format, modifier)) 440 return true; 441 442 /* 443 * TODO: The backend alone allows 2x and 4x integer scaling, including 444 * support for an alpha component (which the frontend doesn't support). 445 * Use the backend directly instead of the frontend in this case, with 446 * another test to return false. 447 */ 448 449 if (sun4i_backend_plane_uses_scaler(state)) 450 return true; 451 452 /* 453 * Here the format is supported by both the frontend and the backend 454 * and no frontend scaling is required, so use the backend directly. 455 */ 456 return false; 457 } 458 459 static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state, 460 bool *uses_frontend) 461 { 462 if (sun4i_backend_plane_uses_frontend(state)) { 463 *uses_frontend = true; 464 return true; 465 } 466 467 *uses_frontend = false; 468 469 /* Scaling is not supported without the frontend. */ 470 if (sun4i_backend_plane_uses_scaler(state)) 471 return false; 472 473 return true; 474 } 475 476 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine, 477 struct drm_crtc_state *old_state) 478 { 479 u32 val; 480 481 WARN_ON(regmap_read_poll_timeout(engine->regs, 482 SUN4I_BACKEND_REGBUFFCTL_REG, 483 val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL), 484 100, 50000)); 485 } 486 487 static int sun4i_backend_atomic_check(struct sunxi_engine *engine, 488 struct drm_crtc_state *crtc_state) 489 { 490 struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 }; 491 struct sun4i_backend *backend = engine_to_sun4i_backend(engine); 492 struct drm_atomic_state *state = crtc_state->state; 493 struct drm_device *drm = state->dev; 494 struct drm_plane *plane; 495 unsigned int num_planes = 0; 496 unsigned int num_alpha_planes = 0; 497 unsigned int num_frontend_planes = 0; 498 unsigned int num_alpha_planes_max = 1; 499 unsigned int num_yuv_planes = 0; 500 unsigned int current_pipe = 0; 501 unsigned int i; 502 503 DRM_DEBUG_DRIVER("Starting checking our planes\n"); 504 505 if (!crtc_state->planes_changed) 506 return 0; 507 508 drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) { 509 struct drm_plane_state *plane_state = 510 drm_atomic_get_plane_state(state, plane); 511 struct sun4i_layer_state *layer_state = 512 state_to_sun4i_layer_state(plane_state); 513 struct drm_framebuffer *fb = plane_state->fb; 514 struct drm_format_name_buf format_name; 515 516 if (!sun4i_backend_plane_is_supported(plane_state, 517 &layer_state->uses_frontend)) 518 return -EINVAL; 519 520 if (layer_state->uses_frontend) { 521 DRM_DEBUG_DRIVER("Using the frontend for plane %d\n", 522 plane->index); 523 num_frontend_planes++; 524 } else { 525 if (fb->format->is_yuv) { 526 DRM_DEBUG_DRIVER("Plane FB format is YUV\n"); 527 num_yuv_planes++; 528 } 529 } 530 531 DRM_DEBUG_DRIVER("Plane FB format is %s\n", 532 drm_get_format_name(fb->format->format, 533 &format_name)); 534 if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) 535 num_alpha_planes++; 536 537 DRM_DEBUG_DRIVER("Plane zpos is %d\n", 538 plane_state->normalized_zpos); 539 540 /* Sort our planes by Zpos */ 541 plane_states[plane_state->normalized_zpos] = plane_state; 542 543 num_planes++; 544 } 545 546 /* All our planes were disabled, bail out */ 547 if (!num_planes) 548 return 0; 549 550 /* 551 * The hardware is a bit unusual here. 552 * 553 * Even though it supports 4 layers, it does the composition 554 * in two separate steps. 555 * 556 * The first one is assigning a layer to one of its two 557 * pipes. If more that 1 layer is assigned to the same pipe, 558 * and if pixels overlaps, the pipe will take the pixel from 559 * the layer with the highest priority. 560 * 561 * The second step is the actual alpha blending, that takes 562 * the two pipes as input, and uses the potential alpha 563 * component to do the transparency between the two. 564 * 565 * This two-step scenario makes us unable to guarantee a 566 * robust alpha blending between the 4 layers in all 567 * situations, since this means that we need to have one layer 568 * with alpha at the lowest position of our two pipes. 569 * 570 * However, we cannot even do that on every platform, since 571 * the hardware has a bug where the lowest plane of the lowest 572 * pipe (pipe 0, priority 0), if it has any alpha, will 573 * discard the pixel data entirely and just display the pixels 574 * in the background color (black by default). 575 * 576 * This means that on the affected platforms, we effectively 577 * have only three valid configurations with alpha, all of 578 * them with the alpha being on pipe1 with the lowest 579 * position, which can be 1, 2 or 3 depending on the number of 580 * planes and their zpos. 581 */ 582 583 /* For platforms that are not affected by the issue described above. */ 584 if (backend->quirks->supports_lowest_plane_alpha) 585 num_alpha_planes_max++; 586 587 if (num_alpha_planes > num_alpha_planes_max) { 588 DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n"); 589 return -EINVAL; 590 } 591 592 /* We can't have an alpha plane at the lowest position */ 593 if (!backend->quirks->supports_lowest_plane_alpha && 594 (plane_states[0]->fb->format->has_alpha || 595 (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))) 596 return -EINVAL; 597 598 for (i = 1; i < num_planes; i++) { 599 struct drm_plane_state *p_state = plane_states[i]; 600 struct drm_framebuffer *fb = p_state->fb; 601 struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state); 602 603 /* 604 * The only alpha position is the lowest plane of the 605 * second pipe. 606 */ 607 if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE)) 608 current_pipe++; 609 610 s_state->pipe = current_pipe; 611 } 612 613 /* We can only have a single YUV plane at a time */ 614 if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) { 615 DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n"); 616 return -EINVAL; 617 } 618 619 if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) { 620 DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n"); 621 return -EINVAL; 622 } 623 624 DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n", 625 num_planes, num_alpha_planes, num_frontend_planes, 626 num_yuv_planes); 627 628 return 0; 629 } 630 631 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine) 632 { 633 struct sun4i_backend *backend = engine_to_sun4i_backend(engine); 634 struct sun4i_frontend *frontend = backend->frontend; 635 636 if (!frontend) 637 return; 638 639 /* 640 * In a teardown scenario with the frontend involved, we have 641 * to keep the frontend enabled until the next vblank, and 642 * only then disable it. 643 * 644 * This is due to the fact that the backend will not take into 645 * account the new configuration (with the plane that used to 646 * be fed by the frontend now disabled) until we write to the 647 * commit bit and the hardware fetches the new configuration 648 * during the next vblank. 649 * 650 * So we keep the frontend around in order to prevent any 651 * visual artifacts. 652 */ 653 spin_lock(&backend->frontend_lock); 654 if (backend->frontend_teardown) { 655 sun4i_frontend_exit(frontend); 656 backend->frontend_teardown = false; 657 } 658 spin_unlock(&backend->frontend_lock); 659 }; 660 661 static int sun4i_backend_init_sat(struct device *dev) { 662 struct sun4i_backend *backend = dev_get_drvdata(dev); 663 int ret; 664 665 backend->sat_reset = devm_reset_control_get(dev, "sat"); 666 if (IS_ERR(backend->sat_reset)) { 667 dev_err(dev, "Couldn't get the SAT reset line\n"); 668 return PTR_ERR(backend->sat_reset); 669 } 670 671 ret = reset_control_deassert(backend->sat_reset); 672 if (ret) { 673 dev_err(dev, "Couldn't deassert the SAT reset line\n"); 674 return ret; 675 } 676 677 backend->sat_clk = devm_clk_get(dev, "sat"); 678 if (IS_ERR(backend->sat_clk)) { 679 dev_err(dev, "Couldn't get our SAT clock\n"); 680 ret = PTR_ERR(backend->sat_clk); 681 goto err_assert_reset; 682 } 683 684 ret = clk_prepare_enable(backend->sat_clk); 685 if (ret) { 686 dev_err(dev, "Couldn't enable the SAT clock\n"); 687 return ret; 688 } 689 690 return 0; 691 692 err_assert_reset: 693 reset_control_assert(backend->sat_reset); 694 return ret; 695 } 696 697 static int sun4i_backend_free_sat(struct device *dev) { 698 struct sun4i_backend *backend = dev_get_drvdata(dev); 699 700 clk_disable_unprepare(backend->sat_clk); 701 reset_control_assert(backend->sat_reset); 702 703 return 0; 704 } 705 706 /* 707 * The display backend can take video output from the display frontend, or 708 * the display enhancement unit on the A80, as input for one it its layers. 709 * This relationship within the display pipeline is encoded in the device 710 * tree with of_graph, and we use it here to figure out which backend, if 711 * there are 2 or more, we are currently probing. The number would be in 712 * the "reg" property of the upstream output port endpoint. 713 */ 714 static int sun4i_backend_of_get_id(struct device_node *node) 715 { 716 struct device_node *ep, *remote; 717 struct of_endpoint of_ep; 718 719 /* Input port is 0, and we want the first endpoint. */ 720 ep = of_graph_get_endpoint_by_regs(node, 0, -1); 721 if (!ep) 722 return -EINVAL; 723 724 remote = of_graph_get_remote_endpoint(ep); 725 of_node_put(ep); 726 if (!remote) 727 return -EINVAL; 728 729 of_graph_parse_endpoint(remote, &of_ep); 730 of_node_put(remote); 731 return of_ep.id; 732 } 733 734 /* TODO: This needs to take multiple pipelines into account */ 735 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv, 736 struct device_node *node) 737 { 738 struct device_node *port, *ep, *remote; 739 struct sun4i_frontend *frontend; 740 741 port = of_graph_get_port_by_id(node, 0); 742 if (!port) 743 return ERR_PTR(-EINVAL); 744 745 for_each_available_child_of_node(port, ep) { 746 remote = of_graph_get_remote_port_parent(ep); 747 if (!remote) 748 continue; 749 of_node_put(remote); 750 751 /* does this node match any registered engines? */ 752 list_for_each_entry(frontend, &drv->frontend_list, list) { 753 if (remote == frontend->node) { 754 of_node_put(port); 755 of_node_put(ep); 756 return frontend; 757 } 758 } 759 } 760 of_node_put(port); 761 return ERR_PTR(-EINVAL); 762 } 763 764 static const struct sunxi_engine_ops sun4i_backend_engine_ops = { 765 .atomic_begin = sun4i_backend_atomic_begin, 766 .atomic_check = sun4i_backend_atomic_check, 767 .commit = sun4i_backend_commit, 768 .layers_init = sun4i_layers_init, 769 .apply_color_correction = sun4i_backend_apply_color_correction, 770 .disable_color_correction = sun4i_backend_disable_color_correction, 771 .vblank_quirk = sun4i_backend_vblank_quirk, 772 }; 773 774 static struct regmap_config sun4i_backend_regmap_config = { 775 .reg_bits = 32, 776 .val_bits = 32, 777 .reg_stride = 4, 778 .max_register = 0x5800, 779 }; 780 781 static int sun4i_backend_bind(struct device *dev, struct device *master, 782 void *data) 783 { 784 struct platform_device *pdev = to_platform_device(dev); 785 struct drm_device *drm = data; 786 struct sun4i_drv *drv = drm->dev_private; 787 struct sun4i_backend *backend; 788 const struct sun4i_backend_quirks *quirks; 789 struct resource *res; 790 void __iomem *regs; 791 int i, ret; 792 793 backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL); 794 if (!backend) 795 return -ENOMEM; 796 dev_set_drvdata(dev, backend); 797 spin_lock_init(&backend->frontend_lock); 798 799 if (of_find_property(dev->of_node, "interconnects", NULL)) { 800 /* 801 * This assume we have the same DMA constraints for all our the 802 * devices in our pipeline (all the backends, but also the 803 * frontends). This sounds bad, but it has always been the case 804 * for us, and DRM doesn't do per-device allocation either, so 805 * we would need to fix DRM first... 806 */ 807 ret = of_dma_configure(drm->dev, dev->of_node, true); 808 if (ret) 809 return ret; 810 } else { 811 /* 812 * If we don't have the interconnect property, most likely 813 * because of an old DT, we need to set the DMA offset by hand 814 * on our device since the RAM mapping is at 0 for the DMA bus, 815 * unlike the CPU. 816 */ 817 drm->dev->dma_pfn_offset = PHYS_PFN_OFFSET; 818 } 819 820 backend->engine.node = dev->of_node; 821 backend->engine.ops = &sun4i_backend_engine_ops; 822 backend->engine.id = sun4i_backend_of_get_id(dev->of_node); 823 if (backend->engine.id < 0) 824 return backend->engine.id; 825 826 backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node); 827 if (IS_ERR(backend->frontend)) 828 dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n"); 829 830 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 831 regs = devm_ioremap_resource(dev, res); 832 if (IS_ERR(regs)) 833 return PTR_ERR(regs); 834 835 backend->reset = devm_reset_control_get(dev, NULL); 836 if (IS_ERR(backend->reset)) { 837 dev_err(dev, "Couldn't get our reset line\n"); 838 return PTR_ERR(backend->reset); 839 } 840 841 ret = reset_control_deassert(backend->reset); 842 if (ret) { 843 dev_err(dev, "Couldn't deassert our reset line\n"); 844 return ret; 845 } 846 847 backend->bus_clk = devm_clk_get(dev, "ahb"); 848 if (IS_ERR(backend->bus_clk)) { 849 dev_err(dev, "Couldn't get the backend bus clock\n"); 850 ret = PTR_ERR(backend->bus_clk); 851 goto err_assert_reset; 852 } 853 clk_prepare_enable(backend->bus_clk); 854 855 backend->mod_clk = devm_clk_get(dev, "mod"); 856 if (IS_ERR(backend->mod_clk)) { 857 dev_err(dev, "Couldn't get the backend module clock\n"); 858 ret = PTR_ERR(backend->mod_clk); 859 goto err_disable_bus_clk; 860 } 861 clk_prepare_enable(backend->mod_clk); 862 863 backend->ram_clk = devm_clk_get(dev, "ram"); 864 if (IS_ERR(backend->ram_clk)) { 865 dev_err(dev, "Couldn't get the backend RAM clock\n"); 866 ret = PTR_ERR(backend->ram_clk); 867 goto err_disable_mod_clk; 868 } 869 clk_prepare_enable(backend->ram_clk); 870 871 if (of_device_is_compatible(dev->of_node, 872 "allwinner,sun8i-a33-display-backend")) { 873 ret = sun4i_backend_init_sat(dev); 874 if (ret) { 875 dev_err(dev, "Couldn't init SAT resources\n"); 876 goto err_disable_ram_clk; 877 } 878 } 879 880 backend->engine.regs = devm_regmap_init_mmio(dev, regs, 881 &sun4i_backend_regmap_config); 882 if (IS_ERR(backend->engine.regs)) { 883 dev_err(dev, "Couldn't create the backend regmap\n"); 884 return PTR_ERR(backend->engine.regs); 885 } 886 887 list_add_tail(&backend->engine.list, &drv->engine_list); 888 889 /* 890 * Many of the backend's layer configuration registers have 891 * undefined default values. This poses a risk as we use 892 * regmap_update_bits in some places, and don't overwrite 893 * the whole register. 894 * 895 * Clear the registers here to have something predictable. 896 */ 897 for (i = 0x800; i < 0x1000; i += 4) 898 regmap_write(backend->engine.regs, i, 0); 899 900 /* Disable registers autoloading */ 901 regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG, 902 SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS); 903 904 /* Enable the backend */ 905 regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG, 906 SUN4I_BACKEND_MODCTL_DEBE_EN | 907 SUN4I_BACKEND_MODCTL_START_CTL); 908 909 /* Set output selection if needed */ 910 quirks = of_device_get_match_data(dev); 911 if (quirks->needs_output_muxing) { 912 /* 913 * We assume there is no dynamic muxing of backends 914 * and TCONs, so we select the backend with same ID. 915 * 916 * While dynamic selection might be interesting, since 917 * the CRTC is tied to the TCON, while the layers are 918 * tied to the backends, this means, we will need to 919 * switch between groups of layers. There might not be 920 * a way to represent this constraint in DRM. 921 */ 922 regmap_update_bits(backend->engine.regs, 923 SUN4I_BACKEND_MODCTL_REG, 924 SUN4I_BACKEND_MODCTL_OUT_SEL, 925 (backend->engine.id 926 ? SUN4I_BACKEND_MODCTL_OUT_LCD1 927 : SUN4I_BACKEND_MODCTL_OUT_LCD0)); 928 } 929 930 backend->quirks = quirks; 931 932 return 0; 933 934 err_disable_ram_clk: 935 clk_disable_unprepare(backend->ram_clk); 936 err_disable_mod_clk: 937 clk_disable_unprepare(backend->mod_clk); 938 err_disable_bus_clk: 939 clk_disable_unprepare(backend->bus_clk); 940 err_assert_reset: 941 reset_control_assert(backend->reset); 942 return ret; 943 } 944 945 static void sun4i_backend_unbind(struct device *dev, struct device *master, 946 void *data) 947 { 948 struct sun4i_backend *backend = dev_get_drvdata(dev); 949 950 list_del(&backend->engine.list); 951 952 if (of_device_is_compatible(dev->of_node, 953 "allwinner,sun8i-a33-display-backend")) 954 sun4i_backend_free_sat(dev); 955 956 clk_disable_unprepare(backend->ram_clk); 957 clk_disable_unprepare(backend->mod_clk); 958 clk_disable_unprepare(backend->bus_clk); 959 reset_control_assert(backend->reset); 960 } 961 962 static const struct component_ops sun4i_backend_ops = { 963 .bind = sun4i_backend_bind, 964 .unbind = sun4i_backend_unbind, 965 }; 966 967 static int sun4i_backend_probe(struct platform_device *pdev) 968 { 969 return component_add(&pdev->dev, &sun4i_backend_ops); 970 } 971 972 static int sun4i_backend_remove(struct platform_device *pdev) 973 { 974 component_del(&pdev->dev, &sun4i_backend_ops); 975 976 return 0; 977 } 978 979 static const struct sun4i_backend_quirks sun4i_backend_quirks = { 980 .needs_output_muxing = true, 981 }; 982 983 static const struct sun4i_backend_quirks sun5i_backend_quirks = { 984 }; 985 986 static const struct sun4i_backend_quirks sun6i_backend_quirks = { 987 }; 988 989 static const struct sun4i_backend_quirks sun7i_backend_quirks = { 990 .needs_output_muxing = true, 991 .supports_lowest_plane_alpha = true, 992 }; 993 994 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = { 995 .supports_lowest_plane_alpha = true, 996 }; 997 998 static const struct sun4i_backend_quirks sun9i_backend_quirks = { 999 }; 1000 1001 static const struct of_device_id sun4i_backend_of_table[] = { 1002 { 1003 .compatible = "allwinner,sun4i-a10-display-backend", 1004 .data = &sun4i_backend_quirks, 1005 }, 1006 { 1007 .compatible = "allwinner,sun5i-a13-display-backend", 1008 .data = &sun5i_backend_quirks, 1009 }, 1010 { 1011 .compatible = "allwinner,sun6i-a31-display-backend", 1012 .data = &sun6i_backend_quirks, 1013 }, 1014 { 1015 .compatible = "allwinner,sun7i-a20-display-backend", 1016 .data = &sun7i_backend_quirks, 1017 }, 1018 { 1019 .compatible = "allwinner,sun8i-a23-display-backend", 1020 .data = &sun8i_a33_backend_quirks, 1021 }, 1022 { 1023 .compatible = "allwinner,sun8i-a33-display-backend", 1024 .data = &sun8i_a33_backend_quirks, 1025 }, 1026 { 1027 .compatible = "allwinner,sun9i-a80-display-backend", 1028 .data = &sun9i_backend_quirks, 1029 }, 1030 { } 1031 }; 1032 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table); 1033 1034 static struct platform_driver sun4i_backend_platform_driver = { 1035 .probe = sun4i_backend_probe, 1036 .remove = sun4i_backend_remove, 1037 .driver = { 1038 .name = "sun4i-backend", 1039 .of_match_table = sun4i_backend_of_table, 1040 }, 1041 }; 1042 module_platform_driver(sun4i_backend_platform_driver); 1043 1044 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 1045 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver"); 1046 MODULE_LICENSE("GPL"); 1047