1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #ifndef _LTDC_H_ 12 #define _LTDC_H_ 13 14 struct ltdc_caps { 15 u32 hw_version; /* hardware version */ 16 u32 nb_layers; /* number of supported layers */ 17 u32 reg_ofs; /* register offset for applicable regs */ 18 u32 bus_width; /* bus width (32 or 64 bits) */ 19 const u32 *pix_fmt_hw; /* supported pixel formats */ 20 bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */ 21 int pad_max_freq_hz; /* max frequency supported by pad */ 22 int nb_irq; /* number of hardware interrupts */ 23 }; 24 25 #define LTDC_MAX_LAYER 4 26 27 struct fps_info { 28 unsigned int counter; 29 ktime_t last_timestamp; 30 }; 31 32 struct ltdc_device { 33 void __iomem *regs; 34 struct clk *pixel_clk; /* lcd pixel clock */ 35 struct mutex err_lock; /* protecting error_status */ 36 struct ltdc_caps caps; 37 u32 error_status; 38 u32 irq_status; 39 struct fps_info plane_fpsi[LTDC_MAX_LAYER]; 40 struct drm_atomic_state *suspend_state; 41 }; 42 43 int ltdc_load(struct drm_device *ddev); 44 void ltdc_unload(struct drm_device *ddev); 45 void ltdc_suspend(struct drm_device *ddev); 46 int ltdc_resume(struct drm_device *ddev); 47 48 #endif 49