1 /* 2 * Copyright (C) STMicroelectronics SA 2017 3 * 4 * Authors: Philippe Cornu <philippe.cornu@st.com> 5 * Yannick Fertre <yannick.fertre@st.com> 6 * Fabien Dessenne <fabien.dessenne@st.com> 7 * Mickael Reulier <mickael.reulier@st.com> 8 * 9 * License terms: GNU General Public License (GPL), version 2 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/component.h> 14 #include <linux/of_address.h> 15 #include <linux/of_graph.h> 16 #include <linux/reset.h> 17 18 #include <drm/drm_atomic.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_crtc_helper.h> 21 #include <drm/drm_fb_cma_helper.h> 22 #include <drm/drm_gem_cma_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_plane_helper.h> 26 27 #include <video/videomode.h> 28 29 #include "ltdc.h" 30 31 #define NB_CRTC 1 32 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 33 34 #define MAX_IRQ 4 35 36 #define MAX_ENDPOINTS 2 37 38 #define HWVER_10200 0x010200 39 #define HWVER_10300 0x010300 40 #define HWVER_20101 0x020101 41 42 /* 43 * The address of some registers depends on the HW version: such registers have 44 * an extra offset specified with reg_ofs. 45 */ 46 #define REG_OFS_NONE 0 47 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 48 #define REG_OFS (ldev->caps.reg_ofs) 49 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 50 51 /* Global register offsets */ 52 #define LTDC_IDR 0x0000 /* IDentification */ 53 #define LTDC_LCR 0x0004 /* Layer Count */ 54 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 55 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 56 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 57 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 58 #define LTDC_GCR 0x0018 /* Global Control */ 59 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 60 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 61 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 62 #define LTDC_GACR 0x0028 /* GAmma Correction */ 63 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 64 #define LTDC_IER 0x0034 /* Interrupt Enable */ 65 #define LTDC_ISR 0x0038 /* Interrupt Status */ 66 #define LTDC_ICR 0x003C /* Interrupt Clear */ 67 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 68 #define LTDC_CPSR 0x0044 /* Current Position Status */ 69 #define LTDC_CDSR 0x0048 /* Current Display Status */ 70 71 /* Layer register offsets */ 72 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 73 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 74 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 75 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 76 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 77 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 78 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 79 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 80 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 81 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 82 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 83 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 84 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 85 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 86 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 87 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 88 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 89 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 90 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 91 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 92 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 93 94 /* Bit definitions */ 95 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 96 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 97 98 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 99 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 100 101 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 102 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 103 104 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 105 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 106 107 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 108 #define GCR_DEN BIT(16) /* Dither ENable */ 109 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 110 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 111 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 112 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 113 114 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 115 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 116 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 117 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 118 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 119 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 120 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 121 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 122 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 123 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 124 #define GC1R_TP BIT(25) /* Timing Programmable */ 125 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 126 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 127 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 128 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 129 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 130 131 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 132 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 133 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 134 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 135 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 136 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 137 138 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 139 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 140 141 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 142 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 143 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 144 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 145 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 146 147 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 148 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 149 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 150 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 151 152 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 153 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 154 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 155 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 156 157 #define LXCR_LEN BIT(0) /* Layer ENable */ 158 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 159 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 160 161 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 162 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 163 164 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 165 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 166 167 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 168 169 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 170 171 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 172 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 173 174 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 175 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 176 177 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 178 179 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 180 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 181 #define BF1_CA 0x400 /* Constant Alpha */ 182 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 183 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 184 185 #define NB_PF 8 /* Max nb of HW pixel format */ 186 187 enum ltdc_pix_fmt { 188 PF_NONE, 189 /* RGB formats */ 190 PF_ARGB8888, /* ARGB [32 bits] */ 191 PF_RGBA8888, /* RGBA [32 bits] */ 192 PF_RGB888, /* RGB [24 bits] */ 193 PF_RGB565, /* RGB [16 bits] */ 194 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 195 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 196 /* Indexed formats */ 197 PF_L8, /* Indexed 8 bits [8 bits] */ 198 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 199 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 200 }; 201 202 /* The index gives the encoding of the pixel format for an HW version */ 203 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 204 PF_ARGB8888, /* 0x00 */ 205 PF_RGB888, /* 0x01 */ 206 PF_RGB565, /* 0x02 */ 207 PF_ARGB1555, /* 0x03 */ 208 PF_ARGB4444, /* 0x04 */ 209 PF_L8, /* 0x05 */ 210 PF_AL44, /* 0x06 */ 211 PF_AL88 /* 0x07 */ 212 }; 213 214 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 215 PF_ARGB8888, /* 0x00 */ 216 PF_RGB888, /* 0x01 */ 217 PF_RGB565, /* 0x02 */ 218 PF_RGBA8888, /* 0x03 */ 219 PF_AL44, /* 0x04 */ 220 PF_L8, /* 0x05 */ 221 PF_ARGB1555, /* 0x06 */ 222 PF_ARGB4444 /* 0x07 */ 223 }; 224 225 static inline u32 reg_read(void __iomem *base, u32 reg) 226 { 227 return readl_relaxed(base + reg); 228 } 229 230 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 231 { 232 writel_relaxed(val, base + reg); 233 } 234 235 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 236 { 237 reg_write(base, reg, reg_read(base, reg) | mask); 238 } 239 240 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 241 { 242 reg_write(base, reg, reg_read(base, reg) & ~mask); 243 } 244 245 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 246 u32 val) 247 { 248 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 249 } 250 251 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 252 { 253 return (struct ltdc_device *)crtc->dev->dev_private; 254 } 255 256 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 257 { 258 return (struct ltdc_device *)plane->dev->dev_private; 259 } 260 261 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 262 { 263 return (struct ltdc_device *)enc->dev->dev_private; 264 } 265 266 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 267 { 268 enum ltdc_pix_fmt pf; 269 270 switch (drm_fmt) { 271 case DRM_FORMAT_ARGB8888: 272 case DRM_FORMAT_XRGB8888: 273 pf = PF_ARGB8888; 274 break; 275 case DRM_FORMAT_RGBA8888: 276 case DRM_FORMAT_RGBX8888: 277 pf = PF_RGBA8888; 278 break; 279 case DRM_FORMAT_RGB888: 280 pf = PF_RGB888; 281 break; 282 case DRM_FORMAT_RGB565: 283 pf = PF_RGB565; 284 break; 285 case DRM_FORMAT_ARGB1555: 286 case DRM_FORMAT_XRGB1555: 287 pf = PF_ARGB1555; 288 break; 289 case DRM_FORMAT_ARGB4444: 290 case DRM_FORMAT_XRGB4444: 291 pf = PF_ARGB4444; 292 break; 293 case DRM_FORMAT_C8: 294 pf = PF_L8; 295 break; 296 default: 297 pf = PF_NONE; 298 break; 299 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 300 } 301 302 return pf; 303 } 304 305 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 306 { 307 switch (pf) { 308 case PF_ARGB8888: 309 return DRM_FORMAT_ARGB8888; 310 case PF_RGBA8888: 311 return DRM_FORMAT_RGBA8888; 312 case PF_RGB888: 313 return DRM_FORMAT_RGB888; 314 case PF_RGB565: 315 return DRM_FORMAT_RGB565; 316 case PF_ARGB1555: 317 return DRM_FORMAT_ARGB1555; 318 case PF_ARGB4444: 319 return DRM_FORMAT_ARGB4444; 320 case PF_L8: 321 return DRM_FORMAT_C8; 322 case PF_AL44: /* No DRM support */ 323 case PF_AL88: /* No DRM support */ 324 case PF_NONE: 325 default: 326 return 0; 327 } 328 } 329 330 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 331 { 332 struct drm_device *ddev = arg; 333 struct ltdc_device *ldev = ddev->dev_private; 334 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 335 336 /* Line IRQ : trigger the vblank event */ 337 if (ldev->irq_status & ISR_LIF) 338 drm_crtc_handle_vblank(crtc); 339 340 /* Save FIFO Underrun & Transfer Error status */ 341 mutex_lock(&ldev->err_lock); 342 if (ldev->irq_status & ISR_FUIF) 343 ldev->error_status |= ISR_FUIF; 344 if (ldev->irq_status & ISR_TERRIF) 345 ldev->error_status |= ISR_TERRIF; 346 mutex_unlock(&ldev->err_lock); 347 348 return IRQ_HANDLED; 349 } 350 351 static irqreturn_t ltdc_irq(int irq, void *arg) 352 { 353 struct drm_device *ddev = arg; 354 struct ltdc_device *ldev = ddev->dev_private; 355 356 /* Read & Clear the interrupt status */ 357 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 358 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 359 360 return IRQ_WAKE_THREAD; 361 } 362 363 /* 364 * DRM_CRTC 365 */ 366 367 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 368 struct drm_crtc_state *old_state) 369 { 370 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 371 372 DRM_DEBUG_DRIVER("\n"); 373 374 /* Sets the background color value */ 375 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 376 377 /* Enable IRQ */ 378 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 379 380 /* Immediately commit the planes */ 381 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 382 383 /* Enable LTDC */ 384 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 385 386 drm_crtc_vblank_on(crtc); 387 } 388 389 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 390 struct drm_crtc_state *old_state) 391 { 392 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 393 394 DRM_DEBUG_DRIVER("\n"); 395 396 drm_crtc_vblank_off(crtc); 397 398 /* disable LTDC */ 399 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 400 401 /* disable IRQ */ 402 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 403 404 /* immediately commit disable of layers before switching off LTDC */ 405 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 406 } 407 408 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 409 { 410 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 411 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 412 struct videomode vm; 413 int rate = mode->clock * 1000; 414 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 415 u32 total_width, total_height; 416 u32 val; 417 418 drm_display_mode_to_videomode(mode, &vm); 419 420 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 421 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 422 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 423 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 424 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 425 426 /* Convert video timings to ltdc timings */ 427 hsync = vm.hsync_len - 1; 428 vsync = vm.vsync_len - 1; 429 accum_hbp = hsync + vm.hback_porch; 430 accum_vbp = vsync + vm.vback_porch; 431 accum_act_w = accum_hbp + vm.hactive; 432 accum_act_h = accum_vbp + vm.vactive; 433 total_width = accum_act_w + vm.hfront_porch; 434 total_height = accum_act_h + vm.vfront_porch; 435 436 clk_disable(ldev->pixel_clk); 437 438 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 439 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 440 return; 441 } 442 443 clk_enable(ldev->pixel_clk); 444 445 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 446 val = 0; 447 448 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 449 val |= GCR_HSPOL; 450 451 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 452 val |= GCR_VSPOL; 453 454 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 455 val |= GCR_DEPOL; 456 457 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 458 val |= GCR_PCPOL; 459 460 reg_update_bits(ldev->regs, LTDC_GCR, 461 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 462 463 /* Set Synchronization size */ 464 val = (hsync << 16) | vsync; 465 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 466 467 /* Set Accumulated Back porch */ 468 val = (accum_hbp << 16) | accum_vbp; 469 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 470 471 /* Set Accumulated Active Width */ 472 val = (accum_act_w << 16) | accum_act_h; 473 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 474 475 /* Set total width & height */ 476 val = (total_width << 16) | total_height; 477 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 478 479 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 480 } 481 482 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 483 struct drm_crtc_state *old_crtc_state) 484 { 485 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 486 struct drm_pending_vblank_event *event = crtc->state->event; 487 488 DRM_DEBUG_ATOMIC("\n"); 489 490 /* Commit shadow registers = update planes at next vblank */ 491 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 492 493 if (event) { 494 crtc->state->event = NULL; 495 496 spin_lock_irq(&crtc->dev->event_lock); 497 if (drm_crtc_vblank_get(crtc) == 0) 498 drm_crtc_arm_vblank_event(crtc, event); 499 else 500 drm_crtc_send_vblank_event(crtc, event); 501 spin_unlock_irq(&crtc->dev->event_lock); 502 } 503 } 504 505 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 506 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 507 .atomic_flush = ltdc_crtc_atomic_flush, 508 .atomic_enable = ltdc_crtc_atomic_enable, 509 .atomic_disable = ltdc_crtc_atomic_disable, 510 }; 511 512 int ltdc_crtc_enable_vblank(struct drm_device *ddev, unsigned int pipe) 513 { 514 struct ltdc_device *ldev = ddev->dev_private; 515 516 DRM_DEBUG_DRIVER("\n"); 517 reg_set(ldev->regs, LTDC_IER, IER_LIE); 518 519 return 0; 520 } 521 522 void ltdc_crtc_disable_vblank(struct drm_device *ddev, unsigned int pipe) 523 { 524 struct ltdc_device *ldev = ddev->dev_private; 525 526 DRM_DEBUG_DRIVER("\n"); 527 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 528 } 529 530 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 531 .destroy = drm_crtc_cleanup, 532 .set_config = drm_atomic_helper_set_config, 533 .page_flip = drm_atomic_helper_page_flip, 534 .reset = drm_atomic_helper_crtc_reset, 535 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 536 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 537 }; 538 539 /* 540 * DRM_PLANE 541 */ 542 543 static int ltdc_plane_atomic_check(struct drm_plane *plane, 544 struct drm_plane_state *state) 545 { 546 struct drm_framebuffer *fb = state->fb; 547 u32 src_x, src_y, src_w, src_h; 548 549 DRM_DEBUG_DRIVER("\n"); 550 551 if (!fb) 552 return 0; 553 554 /* convert src_ from 16:16 format */ 555 src_x = state->src_x >> 16; 556 src_y = state->src_y >> 16; 557 src_w = state->src_w >> 16; 558 src_h = state->src_h >> 16; 559 560 /* Reject scaling */ 561 if (src_w != state->crtc_w || src_h != state->crtc_h) { 562 DRM_ERROR("Scaling is not supported"); 563 return -EINVAL; 564 } 565 566 return 0; 567 } 568 569 static void ltdc_plane_atomic_update(struct drm_plane *plane, 570 struct drm_plane_state *oldstate) 571 { 572 struct ltdc_device *ldev = plane_to_ltdc(plane); 573 struct drm_plane_state *state = plane->state; 574 struct drm_framebuffer *fb = state->fb; 575 u32 lofs = plane->index * LAY_OFS; 576 u32 x0 = state->crtc_x; 577 u32 x1 = state->crtc_x + state->crtc_w - 1; 578 u32 y0 = state->crtc_y; 579 u32 y1 = state->crtc_y + state->crtc_h - 1; 580 u32 src_x, src_y, src_w, src_h; 581 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 582 enum ltdc_pix_fmt pf; 583 584 if (!state->crtc || !fb) { 585 DRM_DEBUG_DRIVER("fb or crtc NULL"); 586 return; 587 } 588 589 /* convert src_ from 16:16 format */ 590 src_x = state->src_x >> 16; 591 src_y = state->src_y >> 16; 592 src_w = state->src_w >> 16; 593 src_h = state->src_h >> 16; 594 595 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 596 plane->base.id, fb->base.id, 597 src_w, src_h, src_x, src_y, 598 state->crtc_w, state->crtc_h, 599 state->crtc_x, state->crtc_y); 600 601 bpcr = reg_read(ldev->regs, LTDC_BPCR); 602 ahbp = (bpcr & BPCR_AHBP) >> 16; 603 avbp = bpcr & BPCR_AVBP; 604 605 /* Configures the horizontal start and stop position */ 606 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 607 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 608 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 609 610 /* Configures the vertical start and stop position */ 611 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 612 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 613 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 614 615 /* Specifies the pixel format */ 616 pf = to_ltdc_pixelformat(fb->format->format); 617 for (val = 0; val < NB_PF; val++) 618 if (ldev->caps.pix_fmt_hw[val] == pf) 619 break; 620 621 if (val == NB_PF) { 622 DRM_ERROR("Pixel format %.4s not supported\n", 623 (char *)&fb->format->format); 624 val = 0; /* set by default ARGB 32 bits */ 625 } 626 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 627 628 /* Configures the color frame buffer pitch in bytes & line length */ 629 pitch_in_bytes = fb->pitches[0]; 630 line_length = drm_format_plane_cpp(fb->format->format, 0) * 631 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 632 val = ((pitch_in_bytes << 16) | line_length); 633 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 634 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 635 636 /* Specifies the constant alpha value */ 637 val = CONSTA_MAX; 638 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 639 640 /* Specifies the blending factors */ 641 val = BF1_PAXCA | BF2_1PAXCA; 642 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 643 LXBFCR_BF2 | LXBFCR_BF1, val); 644 645 /* Configures the frame buffer line number */ 646 val = y1 - y0 + 1; 647 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 648 649 /* Sets the FB address */ 650 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 651 652 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 653 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 654 655 /* Enable layer and CLUT if needed */ 656 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 657 val |= LXCR_LEN; 658 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 659 LXCR_LEN | LXCR_CLUTEN, val); 660 661 mutex_lock(&ldev->err_lock); 662 if (ldev->error_status & ISR_FUIF) { 663 DRM_DEBUG_DRIVER("Fifo underrun\n"); 664 ldev->error_status &= ~ISR_FUIF; 665 } 666 if (ldev->error_status & ISR_TERRIF) { 667 DRM_DEBUG_DRIVER("Transfer error\n"); 668 ldev->error_status &= ~ISR_TERRIF; 669 } 670 mutex_unlock(&ldev->err_lock); 671 } 672 673 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 674 struct drm_plane_state *oldstate) 675 { 676 struct ltdc_device *ldev = plane_to_ltdc(plane); 677 u32 lofs = plane->index * LAY_OFS; 678 679 /* disable layer */ 680 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 681 682 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 683 oldstate->crtc->base.id, plane->base.id); 684 } 685 686 static const struct drm_plane_funcs ltdc_plane_funcs = { 687 .update_plane = drm_atomic_helper_update_plane, 688 .disable_plane = drm_atomic_helper_disable_plane, 689 .destroy = drm_plane_cleanup, 690 .reset = drm_atomic_helper_plane_reset, 691 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 692 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 693 }; 694 695 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 696 .atomic_check = ltdc_plane_atomic_check, 697 .atomic_update = ltdc_plane_atomic_update, 698 .atomic_disable = ltdc_plane_atomic_disable, 699 }; 700 701 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 702 enum drm_plane_type type) 703 { 704 unsigned long possible_crtcs = CRTC_MASK; 705 struct ltdc_device *ldev = ddev->dev_private; 706 struct device *dev = ddev->dev; 707 struct drm_plane *plane; 708 unsigned int i, nb_fmt = 0; 709 u32 formats[NB_PF]; 710 u32 drm_fmt; 711 int ret; 712 713 /* Get supported pixel formats */ 714 for (i = 0; i < NB_PF; i++) { 715 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 716 if (!drm_fmt) 717 continue; 718 formats[nb_fmt++] = drm_fmt; 719 } 720 721 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 722 if (!plane) 723 return 0; 724 725 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 726 <dc_plane_funcs, formats, nb_fmt, 727 NULL, type, NULL); 728 if (ret < 0) 729 return 0; 730 731 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 732 733 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 734 735 return plane; 736 } 737 738 static void ltdc_plane_destroy_all(struct drm_device *ddev) 739 { 740 struct drm_plane *plane, *plane_temp; 741 742 list_for_each_entry_safe(plane, plane_temp, 743 &ddev->mode_config.plane_list, head) 744 drm_plane_cleanup(plane); 745 } 746 747 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 748 { 749 struct ltdc_device *ldev = ddev->dev_private; 750 struct drm_plane *primary, *overlay; 751 unsigned int i; 752 int ret; 753 754 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 755 if (!primary) { 756 DRM_ERROR("Can not create primary plane\n"); 757 return -EINVAL; 758 } 759 760 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 761 <dc_crtc_funcs, NULL); 762 if (ret) { 763 DRM_ERROR("Can not initialize CRTC\n"); 764 goto cleanup; 765 } 766 767 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 768 769 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 770 771 /* Add planes. Note : the first layer is used by primary plane */ 772 for (i = 1; i < ldev->caps.nb_layers; i++) { 773 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 774 if (!overlay) { 775 ret = -ENOMEM; 776 DRM_ERROR("Can not create overlay plane %d\n", i); 777 goto cleanup; 778 } 779 } 780 781 return 0; 782 783 cleanup: 784 ltdc_plane_destroy_all(ddev); 785 return ret; 786 } 787 788 /* 789 * DRM_ENCODER 790 */ 791 792 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 793 .destroy = drm_encoder_cleanup, 794 }; 795 796 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 797 { 798 struct drm_encoder *encoder; 799 int ret; 800 801 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 802 if (!encoder) 803 return -ENOMEM; 804 805 encoder->possible_crtcs = CRTC_MASK; 806 encoder->possible_clones = 0; /* No cloning support */ 807 808 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 809 DRM_MODE_ENCODER_DPI, NULL); 810 811 ret = drm_bridge_attach(encoder, bridge, NULL); 812 if (ret) { 813 drm_encoder_cleanup(encoder); 814 return -EINVAL; 815 } 816 817 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 818 819 return 0; 820 } 821 822 static int ltdc_get_caps(struct drm_device *ddev) 823 { 824 struct ltdc_device *ldev = ddev->dev_private; 825 u32 bus_width_log2, lcr, gc2r; 826 827 /* at least 1 layer must be managed */ 828 lcr = reg_read(ldev->regs, LTDC_LCR); 829 830 ldev->caps.nb_layers = max_t(int, lcr, 1); 831 832 /* set data bus width */ 833 gc2r = reg_read(ldev->regs, LTDC_GC2R); 834 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 835 ldev->caps.bus_width = 8 << bus_width_log2; 836 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 837 838 switch (ldev->caps.hw_version) { 839 case HWVER_10200: 840 case HWVER_10300: 841 ldev->caps.reg_ofs = REG_OFS_NONE; 842 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 843 break; 844 case HWVER_20101: 845 ldev->caps.reg_ofs = REG_OFS_4; 846 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 847 break; 848 default: 849 return -ENODEV; 850 } 851 852 return 0; 853 } 854 855 int ltdc_load(struct drm_device *ddev) 856 { 857 struct platform_device *pdev = to_platform_device(ddev->dev); 858 struct ltdc_device *ldev = ddev->dev_private; 859 struct device *dev = ddev->dev; 860 struct device_node *np = dev->of_node; 861 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 862 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 863 struct drm_crtc *crtc; 864 struct reset_control *rstc; 865 struct resource *res; 866 int irq, ret, i, endpoint_not_ready = -ENODEV; 867 868 DRM_DEBUG_DRIVER("\n"); 869 870 /* Get endpoints if any */ 871 for (i = 0; i < MAX_ENDPOINTS; i++) { 872 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 873 &bridge[i]); 874 875 /* 876 * If at least one endpoint is ready, continue probing, 877 * else if at least one endpoint is -EPROBE_DEFER and 878 * there is no previous ready endpoints, defer probing. 879 */ 880 if (!ret) 881 endpoint_not_ready = 0; 882 else if (ret == -EPROBE_DEFER && endpoint_not_ready) 883 endpoint_not_ready = -EPROBE_DEFER; 884 } 885 886 if (endpoint_not_ready) 887 return endpoint_not_ready; 888 889 rstc = devm_reset_control_get_exclusive(dev, NULL); 890 891 mutex_init(&ldev->err_lock); 892 893 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 894 if (IS_ERR(ldev->pixel_clk)) { 895 DRM_ERROR("Unable to get lcd clock\n"); 896 return -ENODEV; 897 } 898 899 if (clk_prepare_enable(ldev->pixel_clk)) { 900 DRM_ERROR("Unable to prepare pixel clock\n"); 901 return -ENODEV; 902 } 903 904 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 905 if (!res) { 906 DRM_ERROR("Unable to get resource\n"); 907 ret = -ENODEV; 908 goto err; 909 } 910 911 ldev->regs = devm_ioremap_resource(dev, res); 912 if (IS_ERR(ldev->regs)) { 913 DRM_ERROR("Unable to get ltdc registers\n"); 914 ret = PTR_ERR(ldev->regs); 915 goto err; 916 } 917 918 for (i = 0; i < MAX_IRQ; i++) { 919 irq = platform_get_irq(pdev, i); 920 if (irq < 0) 921 continue; 922 923 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 924 ltdc_irq_thread, IRQF_ONESHOT, 925 dev_name(dev), ddev); 926 if (ret) { 927 DRM_ERROR("Failed to register LTDC interrupt\n"); 928 goto err; 929 } 930 } 931 932 if (!IS_ERR(rstc)) 933 reset_control_deassert(rstc); 934 935 /* Disable interrupts */ 936 reg_clear(ldev->regs, LTDC_IER, 937 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 938 939 ret = ltdc_get_caps(ddev); 940 if (ret) { 941 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 942 ldev->caps.hw_version); 943 goto err; 944 } 945 946 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 947 948 /* Add endpoints panels or bridges if any */ 949 for (i = 0; i < MAX_ENDPOINTS; i++) { 950 if (panel[i]) { 951 bridge[i] = drm_panel_bridge_add(panel[i], 952 DRM_MODE_CONNECTOR_DPI); 953 if (IS_ERR(bridge[i])) { 954 DRM_ERROR("panel-bridge endpoint %d\n", i); 955 ret = PTR_ERR(bridge[i]); 956 goto err; 957 } 958 } 959 960 if (bridge[i]) { 961 ret = ltdc_encoder_init(ddev, bridge[i]); 962 if (ret) { 963 DRM_ERROR("init encoder endpoint %d\n", i); 964 goto err; 965 } 966 } 967 } 968 969 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 970 if (!crtc) { 971 DRM_ERROR("Failed to allocate crtc\n"); 972 ret = -ENOMEM; 973 goto err; 974 } 975 976 ret = ltdc_crtc_init(ddev, crtc); 977 if (ret) { 978 DRM_ERROR("Failed to init crtc\n"); 979 goto err; 980 } 981 982 ret = drm_vblank_init(ddev, NB_CRTC); 983 if (ret) { 984 DRM_ERROR("Failed calling drm_vblank_init()\n"); 985 goto err; 986 } 987 988 /* Allow usage of vblank without having to call drm_irq_install */ 989 ddev->irq_enabled = 1; 990 991 return 0; 992 993 err: 994 for (i = 0; i < MAX_ENDPOINTS; i++) 995 drm_panel_bridge_remove(bridge[i]); 996 997 clk_disable_unprepare(ldev->pixel_clk); 998 999 return ret; 1000 } 1001 1002 void ltdc_unload(struct drm_device *ddev) 1003 { 1004 struct ltdc_device *ldev = ddev->dev_private; 1005 int i; 1006 1007 DRM_DEBUG_DRIVER("\n"); 1008 1009 for (i = 0; i < MAX_ENDPOINTS; i++) 1010 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1011 1012 clk_disable_unprepare(ldev->pixel_clk); 1013 } 1014 1015 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1016 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1017 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1018 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1019 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1020 MODULE_LICENSE("GPL v2"); 1021