1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/of_address.h> 14 #include <linux/of_graph.h> 15 #include <linux/reset.h> 16 17 #include <drm/drm_atomic.h> 18 #include <drm/drm_atomic_helper.h> 19 #include <drm/drm_crtc_helper.h> 20 #include <drm/drm_fb_cma_helper.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_of.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_plane_helper.h> 25 26 #include <video/videomode.h> 27 28 #include "ltdc.h" 29 30 #define NB_CRTC 1 31 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 32 33 #define MAX_IRQ 4 34 35 #define MAX_ENDPOINTS 2 36 37 #define HWVER_10200 0x010200 38 #define HWVER_10300 0x010300 39 #define HWVER_20101 0x020101 40 41 /* 42 * The address of some registers depends on the HW version: such registers have 43 * an extra offset specified with reg_ofs. 44 */ 45 #define REG_OFS_NONE 0 46 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 47 #define REG_OFS (ldev->caps.reg_ofs) 48 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 49 50 /* Global register offsets */ 51 #define LTDC_IDR 0x0000 /* IDentification */ 52 #define LTDC_LCR 0x0004 /* Layer Count */ 53 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 54 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 55 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 56 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 57 #define LTDC_GCR 0x0018 /* Global Control */ 58 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 59 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 60 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 61 #define LTDC_GACR 0x0028 /* GAmma Correction */ 62 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 63 #define LTDC_IER 0x0034 /* Interrupt Enable */ 64 #define LTDC_ISR 0x0038 /* Interrupt Status */ 65 #define LTDC_ICR 0x003C /* Interrupt Clear */ 66 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 67 #define LTDC_CPSR 0x0044 /* Current Position Status */ 68 #define LTDC_CDSR 0x0048 /* Current Display Status */ 69 70 /* Layer register offsets */ 71 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 72 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 73 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 74 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 75 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 76 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 77 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 78 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 79 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 80 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 81 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 82 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 83 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 84 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 85 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 86 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 87 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 88 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 89 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 90 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 91 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 92 93 /* Bit definitions */ 94 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 95 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 96 97 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 98 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 99 100 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 101 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 102 103 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 104 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 105 106 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 107 #define GCR_DEN BIT(16) /* Dither ENable */ 108 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 109 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 110 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 111 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 112 113 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 114 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 115 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 116 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 117 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 118 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 119 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 120 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 121 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 122 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 123 #define GC1R_TP BIT(25) /* Timing Programmable */ 124 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 125 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 126 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 127 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 128 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 129 130 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 131 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 132 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 133 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 134 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 135 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 136 137 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 138 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 139 140 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 141 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 142 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 143 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 144 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 145 146 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 147 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 148 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 149 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 150 151 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 152 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 153 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 154 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 155 156 #define LXCR_LEN BIT(0) /* Layer ENable */ 157 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 158 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 159 160 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 161 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 162 163 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 164 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 165 166 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 167 168 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 169 170 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 171 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 172 173 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 174 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 175 176 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 177 178 #define CLUT_SIZE 256 179 180 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 181 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 182 #define BF1_CA 0x400 /* Constant Alpha */ 183 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 184 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 185 186 #define NB_PF 8 /* Max nb of HW pixel format */ 187 188 enum ltdc_pix_fmt { 189 PF_NONE, 190 /* RGB formats */ 191 PF_ARGB8888, /* ARGB [32 bits] */ 192 PF_RGBA8888, /* RGBA [32 bits] */ 193 PF_RGB888, /* RGB [24 bits] */ 194 PF_RGB565, /* RGB [16 bits] */ 195 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 196 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 197 /* Indexed formats */ 198 PF_L8, /* Indexed 8 bits [8 bits] */ 199 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 200 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 201 }; 202 203 /* The index gives the encoding of the pixel format for an HW version */ 204 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 205 PF_ARGB8888, /* 0x00 */ 206 PF_RGB888, /* 0x01 */ 207 PF_RGB565, /* 0x02 */ 208 PF_ARGB1555, /* 0x03 */ 209 PF_ARGB4444, /* 0x04 */ 210 PF_L8, /* 0x05 */ 211 PF_AL44, /* 0x06 */ 212 PF_AL88 /* 0x07 */ 213 }; 214 215 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 216 PF_ARGB8888, /* 0x00 */ 217 PF_RGB888, /* 0x01 */ 218 PF_RGB565, /* 0x02 */ 219 PF_RGBA8888, /* 0x03 */ 220 PF_AL44, /* 0x04 */ 221 PF_L8, /* 0x05 */ 222 PF_ARGB1555, /* 0x06 */ 223 PF_ARGB4444 /* 0x07 */ 224 }; 225 226 static inline u32 reg_read(void __iomem *base, u32 reg) 227 { 228 return readl_relaxed(base + reg); 229 } 230 231 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 232 { 233 writel_relaxed(val, base + reg); 234 } 235 236 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 237 { 238 reg_write(base, reg, reg_read(base, reg) | mask); 239 } 240 241 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 242 { 243 reg_write(base, reg, reg_read(base, reg) & ~mask); 244 } 245 246 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 247 u32 val) 248 { 249 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 250 } 251 252 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 253 { 254 return (struct ltdc_device *)crtc->dev->dev_private; 255 } 256 257 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 258 { 259 return (struct ltdc_device *)plane->dev->dev_private; 260 } 261 262 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 263 { 264 return (struct ltdc_device *)enc->dev->dev_private; 265 } 266 267 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 268 { 269 enum ltdc_pix_fmt pf; 270 271 switch (drm_fmt) { 272 case DRM_FORMAT_ARGB8888: 273 case DRM_FORMAT_XRGB8888: 274 pf = PF_ARGB8888; 275 break; 276 case DRM_FORMAT_RGBA8888: 277 case DRM_FORMAT_RGBX8888: 278 pf = PF_RGBA8888; 279 break; 280 case DRM_FORMAT_RGB888: 281 pf = PF_RGB888; 282 break; 283 case DRM_FORMAT_RGB565: 284 pf = PF_RGB565; 285 break; 286 case DRM_FORMAT_ARGB1555: 287 case DRM_FORMAT_XRGB1555: 288 pf = PF_ARGB1555; 289 break; 290 case DRM_FORMAT_ARGB4444: 291 case DRM_FORMAT_XRGB4444: 292 pf = PF_ARGB4444; 293 break; 294 case DRM_FORMAT_C8: 295 pf = PF_L8; 296 break; 297 default: 298 pf = PF_NONE; 299 break; 300 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 301 } 302 303 return pf; 304 } 305 306 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 307 { 308 switch (pf) { 309 case PF_ARGB8888: 310 return DRM_FORMAT_ARGB8888; 311 case PF_RGBA8888: 312 return DRM_FORMAT_RGBA8888; 313 case PF_RGB888: 314 return DRM_FORMAT_RGB888; 315 case PF_RGB565: 316 return DRM_FORMAT_RGB565; 317 case PF_ARGB1555: 318 return DRM_FORMAT_ARGB1555; 319 case PF_ARGB4444: 320 return DRM_FORMAT_ARGB4444; 321 case PF_L8: 322 return DRM_FORMAT_C8; 323 case PF_AL44: /* No DRM support */ 324 case PF_AL88: /* No DRM support */ 325 case PF_NONE: 326 default: 327 return 0; 328 } 329 } 330 331 static inline u32 get_pixelformat_without_alpha(u32 drm) 332 { 333 switch (drm) { 334 case DRM_FORMAT_ARGB4444: 335 return DRM_FORMAT_XRGB4444; 336 case DRM_FORMAT_RGBA4444: 337 return DRM_FORMAT_RGBX4444; 338 case DRM_FORMAT_ARGB1555: 339 return DRM_FORMAT_XRGB1555; 340 case DRM_FORMAT_RGBA5551: 341 return DRM_FORMAT_RGBX5551; 342 case DRM_FORMAT_ARGB8888: 343 return DRM_FORMAT_XRGB8888; 344 case DRM_FORMAT_RGBA8888: 345 return DRM_FORMAT_RGBX8888; 346 default: 347 return 0; 348 } 349 } 350 351 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 352 { 353 struct drm_device *ddev = arg; 354 struct ltdc_device *ldev = ddev->dev_private; 355 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 356 357 /* Line IRQ : trigger the vblank event */ 358 if (ldev->irq_status & ISR_LIF) 359 drm_crtc_handle_vblank(crtc); 360 361 /* Save FIFO Underrun & Transfer Error status */ 362 mutex_lock(&ldev->err_lock); 363 if (ldev->irq_status & ISR_FUIF) 364 ldev->error_status |= ISR_FUIF; 365 if (ldev->irq_status & ISR_TERRIF) 366 ldev->error_status |= ISR_TERRIF; 367 mutex_unlock(&ldev->err_lock); 368 369 return IRQ_HANDLED; 370 } 371 372 static irqreturn_t ltdc_irq(int irq, void *arg) 373 { 374 struct drm_device *ddev = arg; 375 struct ltdc_device *ldev = ddev->dev_private; 376 377 /* Read & Clear the interrupt status */ 378 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 379 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 380 381 return IRQ_WAKE_THREAD; 382 } 383 384 /* 385 * DRM_CRTC 386 */ 387 388 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 389 { 390 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 391 struct drm_color_lut *lut; 392 u32 val; 393 int i; 394 395 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 396 return; 397 398 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 399 400 for (i = 0; i < CLUT_SIZE; i++, lut++) { 401 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 402 (lut->blue >> 8) | (i << 24); 403 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 404 } 405 } 406 407 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 408 struct drm_crtc_state *old_state) 409 { 410 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 411 412 DRM_DEBUG_DRIVER("\n"); 413 414 /* Sets the background color value */ 415 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 416 417 /* Enable IRQ */ 418 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 419 420 /* Immediately commit the planes */ 421 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 422 423 /* Enable LTDC */ 424 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 425 426 drm_crtc_vblank_on(crtc); 427 } 428 429 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 430 struct drm_crtc_state *old_state) 431 { 432 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 433 434 DRM_DEBUG_DRIVER("\n"); 435 436 drm_crtc_vblank_off(crtc); 437 438 /* disable LTDC */ 439 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 440 441 /* disable IRQ */ 442 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 443 444 /* immediately commit disable of layers before switching off LTDC */ 445 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 446 } 447 448 #define CLK_TOLERANCE_HZ 50 449 450 static enum drm_mode_status 451 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 452 const struct drm_display_mode *mode) 453 { 454 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 455 int target = mode->clock * 1000; 456 int target_min = target - CLK_TOLERANCE_HZ; 457 int target_max = target + CLK_TOLERANCE_HZ; 458 int result; 459 460 /* 461 * Accept all "preferred" modes: 462 * - this is important for panels because panel clock tolerances are 463 * bigger than hdmi ones and there is no reason to not accept them 464 * (the fps may vary a little but it is not a problem). 465 * - the hdmi preferred mode will be accepted too, but userland will 466 * be able to use others hdmi "valid" modes if necessary. 467 */ 468 if (mode->type & DRM_MODE_TYPE_PREFERRED) 469 return MODE_OK; 470 471 result = clk_round_rate(ldev->pixel_clk, target); 472 473 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 474 475 /* 476 * Filter modes according to the clock value, particularly useful for 477 * hdmi modes that require precise pixel clocks. 478 */ 479 if (result < target_min || result > target_max) 480 return MODE_CLOCK_RANGE; 481 482 return MODE_OK; 483 } 484 485 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 486 const struct drm_display_mode *mode, 487 struct drm_display_mode *adjusted_mode) 488 { 489 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 490 int rate = mode->clock * 1000; 491 492 /* 493 * TODO clk_round_rate() does not work yet. When ready, it can 494 * be used instead of clk_set_rate() then clk_get_rate(). 495 */ 496 497 clk_disable(ldev->pixel_clk); 498 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 499 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 500 return false; 501 } 502 clk_enable(ldev->pixel_clk); 503 504 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 505 506 return true; 507 } 508 509 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 510 { 511 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 512 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 513 struct videomode vm; 514 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 515 u32 total_width, total_height; 516 u32 val; 517 518 drm_display_mode_to_videomode(mode, &vm); 519 520 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 521 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 522 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 523 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 524 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 525 526 /* Convert video timings to ltdc timings */ 527 hsync = vm.hsync_len - 1; 528 vsync = vm.vsync_len - 1; 529 accum_hbp = hsync + vm.hback_porch; 530 accum_vbp = vsync + vm.vback_porch; 531 accum_act_w = accum_hbp + vm.hactive; 532 accum_act_h = accum_vbp + vm.vactive; 533 total_width = accum_act_w + vm.hfront_porch; 534 total_height = accum_act_h + vm.vfront_porch; 535 536 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 537 val = 0; 538 539 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 540 val |= GCR_HSPOL; 541 542 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 543 val |= GCR_VSPOL; 544 545 if (vm.flags & DISPLAY_FLAGS_DE_HIGH) 546 val |= GCR_DEPOL; 547 548 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 549 val |= GCR_PCPOL; 550 551 reg_update_bits(ldev->regs, LTDC_GCR, 552 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 553 554 /* Set Synchronization size */ 555 val = (hsync << 16) | vsync; 556 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 557 558 /* Set Accumulated Back porch */ 559 val = (accum_hbp << 16) | accum_vbp; 560 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 561 562 /* Set Accumulated Active Width */ 563 val = (accum_act_w << 16) | accum_act_h; 564 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 565 566 /* Set total width & height */ 567 val = (total_width << 16) | total_height; 568 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 569 570 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 571 } 572 573 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 574 struct drm_crtc_state *old_crtc_state) 575 { 576 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 577 struct drm_pending_vblank_event *event = crtc->state->event; 578 579 DRM_DEBUG_ATOMIC("\n"); 580 581 ltdc_crtc_update_clut(crtc); 582 583 /* Commit shadow registers = update planes at next vblank */ 584 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 585 586 if (event) { 587 crtc->state->event = NULL; 588 589 spin_lock_irq(&crtc->dev->event_lock); 590 if (drm_crtc_vblank_get(crtc) == 0) 591 drm_crtc_arm_vblank_event(crtc, event); 592 else 593 drm_crtc_send_vblank_event(crtc, event); 594 spin_unlock_irq(&crtc->dev->event_lock); 595 } 596 } 597 598 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 599 .mode_valid = ltdc_crtc_mode_valid, 600 .mode_fixup = ltdc_crtc_mode_fixup, 601 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 602 .atomic_flush = ltdc_crtc_atomic_flush, 603 .atomic_enable = ltdc_crtc_atomic_enable, 604 .atomic_disable = ltdc_crtc_atomic_disable, 605 }; 606 607 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 608 { 609 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 610 611 DRM_DEBUG_DRIVER("\n"); 612 reg_set(ldev->regs, LTDC_IER, IER_LIE); 613 614 return 0; 615 } 616 617 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 618 { 619 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 620 621 DRM_DEBUG_DRIVER("\n"); 622 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 623 } 624 625 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 626 .destroy = drm_crtc_cleanup, 627 .set_config = drm_atomic_helper_set_config, 628 .page_flip = drm_atomic_helper_page_flip, 629 .reset = drm_atomic_helper_crtc_reset, 630 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 631 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 632 .enable_vblank = ltdc_crtc_enable_vblank, 633 .disable_vblank = ltdc_crtc_disable_vblank, 634 .gamma_set = drm_atomic_helper_legacy_gamma_set, 635 }; 636 637 /* 638 * DRM_PLANE 639 */ 640 641 static int ltdc_plane_atomic_check(struct drm_plane *plane, 642 struct drm_plane_state *state) 643 { 644 struct drm_framebuffer *fb = state->fb; 645 u32 src_x, src_y, src_w, src_h; 646 647 DRM_DEBUG_DRIVER("\n"); 648 649 if (!fb) 650 return 0; 651 652 /* convert src_ from 16:16 format */ 653 src_x = state->src_x >> 16; 654 src_y = state->src_y >> 16; 655 src_w = state->src_w >> 16; 656 src_h = state->src_h >> 16; 657 658 /* Reject scaling */ 659 if (src_w != state->crtc_w || src_h != state->crtc_h) { 660 DRM_ERROR("Scaling is not supported"); 661 return -EINVAL; 662 } 663 664 return 0; 665 } 666 667 static void ltdc_plane_atomic_update(struct drm_plane *plane, 668 struct drm_plane_state *oldstate) 669 { 670 struct ltdc_device *ldev = plane_to_ltdc(plane); 671 struct drm_plane_state *state = plane->state; 672 struct drm_framebuffer *fb = state->fb; 673 u32 lofs = plane->index * LAY_OFS; 674 u32 x0 = state->crtc_x; 675 u32 x1 = state->crtc_x + state->crtc_w - 1; 676 u32 y0 = state->crtc_y; 677 u32 y1 = state->crtc_y + state->crtc_h - 1; 678 u32 src_x, src_y, src_w, src_h; 679 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 680 enum ltdc_pix_fmt pf; 681 682 if (!state->crtc || !fb) { 683 DRM_DEBUG_DRIVER("fb or crtc NULL"); 684 return; 685 } 686 687 /* convert src_ from 16:16 format */ 688 src_x = state->src_x >> 16; 689 src_y = state->src_y >> 16; 690 src_w = state->src_w >> 16; 691 src_h = state->src_h >> 16; 692 693 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 694 plane->base.id, fb->base.id, 695 src_w, src_h, src_x, src_y, 696 state->crtc_w, state->crtc_h, 697 state->crtc_x, state->crtc_y); 698 699 bpcr = reg_read(ldev->regs, LTDC_BPCR); 700 ahbp = (bpcr & BPCR_AHBP) >> 16; 701 avbp = bpcr & BPCR_AVBP; 702 703 /* Configures the horizontal start and stop position */ 704 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 705 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 706 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 707 708 /* Configures the vertical start and stop position */ 709 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 710 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 711 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 712 713 /* Specifies the pixel format */ 714 pf = to_ltdc_pixelformat(fb->format->format); 715 for (val = 0; val < NB_PF; val++) 716 if (ldev->caps.pix_fmt_hw[val] == pf) 717 break; 718 719 if (val == NB_PF) { 720 DRM_ERROR("Pixel format %.4s not supported\n", 721 (char *)&fb->format->format); 722 val = 0; /* set by default ARGB 32 bits */ 723 } 724 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 725 726 /* Configures the color frame buffer pitch in bytes & line length */ 727 pitch_in_bytes = fb->pitches[0]; 728 line_length = drm_format_plane_cpp(fb->format->format, 0) * 729 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 730 val = ((pitch_in_bytes << 16) | line_length); 731 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 732 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 733 734 /* Specifies the constant alpha value */ 735 val = CONSTA_MAX; 736 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 737 738 /* Specifies the blending factors */ 739 val = BF1_PAXCA | BF2_1PAXCA; 740 if (!fb->format->has_alpha) 741 val = BF1_CA | BF2_1CA; 742 743 /* Manage hw-specific capabilities */ 744 if (ldev->caps.non_alpha_only_l1 && 745 plane->type != DRM_PLANE_TYPE_PRIMARY) 746 val = BF1_PAXCA | BF2_1PAXCA; 747 748 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 749 LXBFCR_BF2 | LXBFCR_BF1, val); 750 751 /* Configures the frame buffer line number */ 752 val = y1 - y0 + 1; 753 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 754 755 /* Sets the FB address */ 756 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 757 758 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 759 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 760 761 /* Enable layer and CLUT if needed */ 762 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 763 val |= LXCR_LEN; 764 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 765 LXCR_LEN | LXCR_CLUTEN, val); 766 767 ldev->plane_fpsi[plane->index].counter++; 768 769 mutex_lock(&ldev->err_lock); 770 if (ldev->error_status & ISR_FUIF) { 771 DRM_DEBUG_DRIVER("Fifo underrun\n"); 772 ldev->error_status &= ~ISR_FUIF; 773 } 774 if (ldev->error_status & ISR_TERRIF) { 775 DRM_DEBUG_DRIVER("Transfer error\n"); 776 ldev->error_status &= ~ISR_TERRIF; 777 } 778 mutex_unlock(&ldev->err_lock); 779 } 780 781 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 782 struct drm_plane_state *oldstate) 783 { 784 struct ltdc_device *ldev = plane_to_ltdc(plane); 785 u32 lofs = plane->index * LAY_OFS; 786 787 /* disable layer */ 788 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 789 790 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 791 oldstate->crtc->base.id, plane->base.id); 792 } 793 794 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 795 const struct drm_plane_state *state) 796 { 797 struct drm_plane *plane = state->plane; 798 struct ltdc_device *ldev = plane_to_ltdc(plane); 799 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 800 int ms_since_last; 801 ktime_t now; 802 803 now = ktime_get(); 804 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 805 806 drm_printf(p, "\tuser_updates=%dfps\n", 807 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 808 809 fpsi->last_timestamp = now; 810 fpsi->counter = 0; 811 } 812 813 static const struct drm_plane_funcs ltdc_plane_funcs = { 814 .update_plane = drm_atomic_helper_update_plane, 815 .disable_plane = drm_atomic_helper_disable_plane, 816 .destroy = drm_plane_cleanup, 817 .reset = drm_atomic_helper_plane_reset, 818 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 819 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 820 .atomic_print_state = ltdc_plane_atomic_print_state, 821 }; 822 823 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 824 .atomic_check = ltdc_plane_atomic_check, 825 .atomic_update = ltdc_plane_atomic_update, 826 .atomic_disable = ltdc_plane_atomic_disable, 827 }; 828 829 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 830 enum drm_plane_type type) 831 { 832 unsigned long possible_crtcs = CRTC_MASK; 833 struct ltdc_device *ldev = ddev->dev_private; 834 struct device *dev = ddev->dev; 835 struct drm_plane *plane; 836 unsigned int i, nb_fmt = 0; 837 u32 formats[NB_PF * 2]; 838 u32 drm_fmt, drm_fmt_no_alpha; 839 int ret; 840 841 /* Get supported pixel formats */ 842 for (i = 0; i < NB_PF; i++) { 843 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 844 if (!drm_fmt) 845 continue; 846 formats[nb_fmt++] = drm_fmt; 847 848 /* Add the no-alpha related format if any & supported */ 849 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 850 if (!drm_fmt_no_alpha) 851 continue; 852 853 /* Manage hw-specific capabilities */ 854 if (ldev->caps.non_alpha_only_l1 && 855 type != DRM_PLANE_TYPE_PRIMARY) 856 continue; 857 858 formats[nb_fmt++] = drm_fmt_no_alpha; 859 } 860 861 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 862 if (!plane) 863 return NULL; 864 865 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 866 <dc_plane_funcs, formats, nb_fmt, 867 NULL, type, NULL); 868 if (ret < 0) 869 return NULL; 870 871 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 872 873 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 874 875 return plane; 876 } 877 878 static void ltdc_plane_destroy_all(struct drm_device *ddev) 879 { 880 struct drm_plane *plane, *plane_temp; 881 882 list_for_each_entry_safe(plane, plane_temp, 883 &ddev->mode_config.plane_list, head) 884 drm_plane_cleanup(plane); 885 } 886 887 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 888 { 889 struct ltdc_device *ldev = ddev->dev_private; 890 struct drm_plane *primary, *overlay; 891 unsigned int i; 892 int ret; 893 894 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 895 if (!primary) { 896 DRM_ERROR("Can not create primary plane\n"); 897 return -EINVAL; 898 } 899 900 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 901 <dc_crtc_funcs, NULL); 902 if (ret) { 903 DRM_ERROR("Can not initialize CRTC\n"); 904 goto cleanup; 905 } 906 907 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 908 909 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 910 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 911 912 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 913 914 /* Add planes. Note : the first layer is used by primary plane */ 915 for (i = 1; i < ldev->caps.nb_layers; i++) { 916 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 917 if (!overlay) { 918 ret = -ENOMEM; 919 DRM_ERROR("Can not create overlay plane %d\n", i); 920 goto cleanup; 921 } 922 } 923 924 return 0; 925 926 cleanup: 927 ltdc_plane_destroy_all(ddev); 928 return ret; 929 } 930 931 /* 932 * DRM_ENCODER 933 */ 934 935 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 936 .destroy = drm_encoder_cleanup, 937 }; 938 939 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 940 { 941 struct drm_encoder *encoder; 942 int ret; 943 944 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 945 if (!encoder) 946 return -ENOMEM; 947 948 encoder->possible_crtcs = CRTC_MASK; 949 encoder->possible_clones = 0; /* No cloning support */ 950 951 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 952 DRM_MODE_ENCODER_DPI, NULL); 953 954 ret = drm_bridge_attach(encoder, bridge, NULL); 955 if (ret) { 956 drm_encoder_cleanup(encoder); 957 return -EINVAL; 958 } 959 960 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 961 962 return 0; 963 } 964 965 static int ltdc_get_caps(struct drm_device *ddev) 966 { 967 struct ltdc_device *ldev = ddev->dev_private; 968 u32 bus_width_log2, lcr, gc2r; 969 970 /* at least 1 layer must be managed */ 971 lcr = reg_read(ldev->regs, LTDC_LCR); 972 973 ldev->caps.nb_layers = max_t(int, lcr, 1); 974 975 /* set data bus width */ 976 gc2r = reg_read(ldev->regs, LTDC_GC2R); 977 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 978 ldev->caps.bus_width = 8 << bus_width_log2; 979 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 980 981 switch (ldev->caps.hw_version) { 982 case HWVER_10200: 983 case HWVER_10300: 984 ldev->caps.reg_ofs = REG_OFS_NONE; 985 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 986 /* 987 * Hw older versions support non-alpha color formats derived 988 * from native alpha color formats only on the primary layer. 989 * For instance, RG16 native format without alpha works fine 990 * on 2nd layer but XR24 (derived color format from AR24) 991 * does not work on 2nd layer. 992 */ 993 ldev->caps.non_alpha_only_l1 = true; 994 break; 995 case HWVER_20101: 996 ldev->caps.reg_ofs = REG_OFS_4; 997 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 998 ldev->caps.non_alpha_only_l1 = false; 999 break; 1000 default: 1001 return -ENODEV; 1002 } 1003 1004 return 0; 1005 } 1006 1007 int ltdc_load(struct drm_device *ddev) 1008 { 1009 struct platform_device *pdev = to_platform_device(ddev->dev); 1010 struct ltdc_device *ldev = ddev->dev_private; 1011 struct device *dev = ddev->dev; 1012 struct device_node *np = dev->of_node; 1013 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1014 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1015 struct drm_crtc *crtc; 1016 struct reset_control *rstc; 1017 struct resource *res; 1018 int irq, ret, i, endpoint_not_ready = -ENODEV; 1019 1020 DRM_DEBUG_DRIVER("\n"); 1021 1022 /* Get endpoints if any */ 1023 for (i = 0; i < MAX_ENDPOINTS; i++) { 1024 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1025 &bridge[i]); 1026 1027 /* 1028 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1029 * else if at least one endpoint is ready, continue probing. 1030 */ 1031 if (ret == -EPROBE_DEFER) 1032 return ret; 1033 else if (!ret) 1034 endpoint_not_ready = 0; 1035 } 1036 1037 if (endpoint_not_ready) 1038 return endpoint_not_ready; 1039 1040 rstc = devm_reset_control_get_exclusive(dev, NULL); 1041 1042 mutex_init(&ldev->err_lock); 1043 1044 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1045 if (IS_ERR(ldev->pixel_clk)) { 1046 DRM_ERROR("Unable to get lcd clock\n"); 1047 return -ENODEV; 1048 } 1049 1050 if (clk_prepare_enable(ldev->pixel_clk)) { 1051 DRM_ERROR("Unable to prepare pixel clock\n"); 1052 return -ENODEV; 1053 } 1054 1055 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1056 ldev->regs = devm_ioremap_resource(dev, res); 1057 if (IS_ERR(ldev->regs)) { 1058 DRM_ERROR("Unable to get ltdc registers\n"); 1059 ret = PTR_ERR(ldev->regs); 1060 goto err; 1061 } 1062 1063 for (i = 0; i < MAX_IRQ; i++) { 1064 irq = platform_get_irq(pdev, i); 1065 if (irq < 0) 1066 continue; 1067 1068 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1069 ltdc_irq_thread, IRQF_ONESHOT, 1070 dev_name(dev), ddev); 1071 if (ret) { 1072 DRM_ERROR("Failed to register LTDC interrupt\n"); 1073 goto err; 1074 } 1075 } 1076 1077 if (!IS_ERR(rstc)) 1078 reset_control_deassert(rstc); 1079 1080 /* Disable interrupts */ 1081 reg_clear(ldev->regs, LTDC_IER, 1082 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1083 1084 ret = ltdc_get_caps(ddev); 1085 if (ret) { 1086 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1087 ldev->caps.hw_version); 1088 goto err; 1089 } 1090 1091 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 1092 1093 /* Add endpoints panels or bridges if any */ 1094 for (i = 0; i < MAX_ENDPOINTS; i++) { 1095 if (panel[i]) { 1096 bridge[i] = drm_panel_bridge_add(panel[i], 1097 DRM_MODE_CONNECTOR_DPI); 1098 if (IS_ERR(bridge[i])) { 1099 DRM_ERROR("panel-bridge endpoint %d\n", i); 1100 ret = PTR_ERR(bridge[i]); 1101 goto err; 1102 } 1103 } 1104 1105 if (bridge[i]) { 1106 ret = ltdc_encoder_init(ddev, bridge[i]); 1107 if (ret) { 1108 DRM_ERROR("init encoder endpoint %d\n", i); 1109 goto err; 1110 } 1111 } 1112 } 1113 1114 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1115 if (!crtc) { 1116 DRM_ERROR("Failed to allocate crtc\n"); 1117 ret = -ENOMEM; 1118 goto err; 1119 } 1120 1121 ret = ltdc_crtc_init(ddev, crtc); 1122 if (ret) { 1123 DRM_ERROR("Failed to init crtc\n"); 1124 goto err; 1125 } 1126 1127 ret = drm_vblank_init(ddev, NB_CRTC); 1128 if (ret) { 1129 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1130 goto err; 1131 } 1132 1133 /* Allow usage of vblank without having to call drm_irq_install */ 1134 ddev->irq_enabled = 1; 1135 1136 return 0; 1137 1138 err: 1139 for (i = 0; i < MAX_ENDPOINTS; i++) 1140 drm_panel_bridge_remove(bridge[i]); 1141 1142 clk_disable_unprepare(ldev->pixel_clk); 1143 1144 return ret; 1145 } 1146 1147 void ltdc_unload(struct drm_device *ddev) 1148 { 1149 struct ltdc_device *ldev = ddev->dev_private; 1150 int i; 1151 1152 DRM_DEBUG_DRIVER("\n"); 1153 1154 for (i = 0; i < MAX_ENDPOINTS; i++) 1155 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1156 1157 clk_disable_unprepare(ldev->pixel_clk); 1158 } 1159 1160 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1161 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1162 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1163 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1164 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1165 MODULE_LICENSE("GPL v2"); 1166