1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_device.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_gem_cma_helper.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_plane_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_vblank.h> 32 33 #include <video/videomode.h> 34 35 #include "ltdc.h" 36 37 #define NB_CRTC 1 38 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 39 40 #define MAX_IRQ 4 41 42 #define MAX_ENDPOINTS 2 43 44 #define HWVER_10200 0x010200 45 #define HWVER_10300 0x010300 46 #define HWVER_20101 0x020101 47 48 /* 49 * The address of some registers depends on the HW version: such registers have 50 * an extra offset specified with reg_ofs. 51 */ 52 #define REG_OFS_NONE 0 53 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 54 #define REG_OFS (ldev->caps.reg_ofs) 55 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 56 57 /* Global register offsets */ 58 #define LTDC_IDR 0x0000 /* IDentification */ 59 #define LTDC_LCR 0x0004 /* Layer Count */ 60 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 61 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 62 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 63 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 64 #define LTDC_GCR 0x0018 /* Global Control */ 65 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 66 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 67 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 68 #define LTDC_GACR 0x0028 /* GAmma Correction */ 69 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 70 #define LTDC_IER 0x0034 /* Interrupt Enable */ 71 #define LTDC_ISR 0x0038 /* Interrupt Status */ 72 #define LTDC_ICR 0x003C /* Interrupt Clear */ 73 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 74 #define LTDC_CPSR 0x0044 /* Current Position Status */ 75 #define LTDC_CDSR 0x0048 /* Current Display Status */ 76 77 /* Layer register offsets */ 78 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 79 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 80 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 81 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 82 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 83 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 84 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 85 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 86 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 87 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 88 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 89 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 90 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 91 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 92 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 93 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 94 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 95 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 96 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 97 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 98 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 99 100 /* Bit definitions */ 101 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 102 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 103 104 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 105 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 106 107 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 108 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 109 110 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 111 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 112 113 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 114 #define GCR_DEN BIT(16) /* Dither ENable */ 115 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 116 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 117 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 118 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 119 120 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 121 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 122 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 123 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 124 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 125 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 126 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 127 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 128 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 129 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 130 #define GC1R_TP BIT(25) /* Timing Programmable */ 131 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 132 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 133 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 134 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 135 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 136 137 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 138 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 139 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 140 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 141 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 142 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 143 144 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 145 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 146 147 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 148 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 149 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 150 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 151 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 152 153 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 154 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 155 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 156 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 157 158 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 159 160 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 161 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 162 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 163 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 164 165 #define LXCR_LEN BIT(0) /* Layer ENable */ 166 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 167 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 168 169 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 170 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 171 172 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 173 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 174 175 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 176 177 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 178 179 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 180 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 181 182 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 183 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 184 185 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 186 187 #define CLUT_SIZE 256 188 189 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 190 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 191 #define BF1_CA 0x400 /* Constant Alpha */ 192 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 193 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 194 195 #define NB_PF 8 /* Max nb of HW pixel format */ 196 197 enum ltdc_pix_fmt { 198 PF_NONE, 199 /* RGB formats */ 200 PF_ARGB8888, /* ARGB [32 bits] */ 201 PF_RGBA8888, /* RGBA [32 bits] */ 202 PF_RGB888, /* RGB [24 bits] */ 203 PF_RGB565, /* RGB [16 bits] */ 204 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 205 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 206 /* Indexed formats */ 207 PF_L8, /* Indexed 8 bits [8 bits] */ 208 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 209 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 210 }; 211 212 /* The index gives the encoding of the pixel format for an HW version */ 213 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 214 PF_ARGB8888, /* 0x00 */ 215 PF_RGB888, /* 0x01 */ 216 PF_RGB565, /* 0x02 */ 217 PF_ARGB1555, /* 0x03 */ 218 PF_ARGB4444, /* 0x04 */ 219 PF_L8, /* 0x05 */ 220 PF_AL44, /* 0x06 */ 221 PF_AL88 /* 0x07 */ 222 }; 223 224 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 225 PF_ARGB8888, /* 0x00 */ 226 PF_RGB888, /* 0x01 */ 227 PF_RGB565, /* 0x02 */ 228 PF_RGBA8888, /* 0x03 */ 229 PF_AL44, /* 0x04 */ 230 PF_L8, /* 0x05 */ 231 PF_ARGB1555, /* 0x06 */ 232 PF_ARGB4444 /* 0x07 */ 233 }; 234 235 static const u64 ltdc_format_modifiers[] = { 236 DRM_FORMAT_MOD_LINEAR, 237 DRM_FORMAT_MOD_INVALID 238 }; 239 240 static inline u32 reg_read(void __iomem *base, u32 reg) 241 { 242 return readl_relaxed(base + reg); 243 } 244 245 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 246 { 247 writel_relaxed(val, base + reg); 248 } 249 250 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 251 { 252 reg_write(base, reg, reg_read(base, reg) | mask); 253 } 254 255 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 256 { 257 reg_write(base, reg, reg_read(base, reg) & ~mask); 258 } 259 260 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 261 u32 val) 262 { 263 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 264 } 265 266 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 267 { 268 return (struct ltdc_device *)crtc->dev->dev_private; 269 } 270 271 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 272 { 273 return (struct ltdc_device *)plane->dev->dev_private; 274 } 275 276 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 277 { 278 return (struct ltdc_device *)enc->dev->dev_private; 279 } 280 281 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 282 { 283 enum ltdc_pix_fmt pf; 284 285 switch (drm_fmt) { 286 case DRM_FORMAT_ARGB8888: 287 case DRM_FORMAT_XRGB8888: 288 pf = PF_ARGB8888; 289 break; 290 case DRM_FORMAT_RGBA8888: 291 case DRM_FORMAT_RGBX8888: 292 pf = PF_RGBA8888; 293 break; 294 case DRM_FORMAT_RGB888: 295 pf = PF_RGB888; 296 break; 297 case DRM_FORMAT_RGB565: 298 pf = PF_RGB565; 299 break; 300 case DRM_FORMAT_ARGB1555: 301 case DRM_FORMAT_XRGB1555: 302 pf = PF_ARGB1555; 303 break; 304 case DRM_FORMAT_ARGB4444: 305 case DRM_FORMAT_XRGB4444: 306 pf = PF_ARGB4444; 307 break; 308 case DRM_FORMAT_C8: 309 pf = PF_L8; 310 break; 311 default: 312 pf = PF_NONE; 313 break; 314 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 315 } 316 317 return pf; 318 } 319 320 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 321 { 322 switch (pf) { 323 case PF_ARGB8888: 324 return DRM_FORMAT_ARGB8888; 325 case PF_RGBA8888: 326 return DRM_FORMAT_RGBA8888; 327 case PF_RGB888: 328 return DRM_FORMAT_RGB888; 329 case PF_RGB565: 330 return DRM_FORMAT_RGB565; 331 case PF_ARGB1555: 332 return DRM_FORMAT_ARGB1555; 333 case PF_ARGB4444: 334 return DRM_FORMAT_ARGB4444; 335 case PF_L8: 336 return DRM_FORMAT_C8; 337 case PF_AL44: /* No DRM support */ 338 case PF_AL88: /* No DRM support */ 339 case PF_NONE: 340 default: 341 return 0; 342 } 343 } 344 345 static inline u32 get_pixelformat_without_alpha(u32 drm) 346 { 347 switch (drm) { 348 case DRM_FORMAT_ARGB4444: 349 return DRM_FORMAT_XRGB4444; 350 case DRM_FORMAT_RGBA4444: 351 return DRM_FORMAT_RGBX4444; 352 case DRM_FORMAT_ARGB1555: 353 return DRM_FORMAT_XRGB1555; 354 case DRM_FORMAT_RGBA5551: 355 return DRM_FORMAT_RGBX5551; 356 case DRM_FORMAT_ARGB8888: 357 return DRM_FORMAT_XRGB8888; 358 case DRM_FORMAT_RGBA8888: 359 return DRM_FORMAT_RGBX8888; 360 default: 361 return 0; 362 } 363 } 364 365 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 366 { 367 struct drm_device *ddev = arg; 368 struct ltdc_device *ldev = ddev->dev_private; 369 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 370 371 /* Line IRQ : trigger the vblank event */ 372 if (ldev->irq_status & ISR_LIF) 373 drm_crtc_handle_vblank(crtc); 374 375 /* Save FIFO Underrun & Transfer Error status */ 376 mutex_lock(&ldev->err_lock); 377 if (ldev->irq_status & ISR_FUIF) 378 ldev->error_status |= ISR_FUIF; 379 if (ldev->irq_status & ISR_TERRIF) 380 ldev->error_status |= ISR_TERRIF; 381 mutex_unlock(&ldev->err_lock); 382 383 return IRQ_HANDLED; 384 } 385 386 static irqreturn_t ltdc_irq(int irq, void *arg) 387 { 388 struct drm_device *ddev = arg; 389 struct ltdc_device *ldev = ddev->dev_private; 390 391 /* Read & Clear the interrupt status */ 392 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 393 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 394 395 return IRQ_WAKE_THREAD; 396 } 397 398 /* 399 * DRM_CRTC 400 */ 401 402 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 403 { 404 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 405 struct drm_color_lut *lut; 406 u32 val; 407 int i; 408 409 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 410 return; 411 412 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 413 414 for (i = 0; i < CLUT_SIZE; i++, lut++) { 415 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 416 (lut->blue >> 8) | (i << 24); 417 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 418 } 419 } 420 421 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 422 struct drm_crtc_state *old_state) 423 { 424 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 425 426 DRM_DEBUG_DRIVER("\n"); 427 428 /* Sets the background color value */ 429 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 430 431 /* Enable IRQ */ 432 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 433 434 /* Commit shadow registers = update planes at next vblank */ 435 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 436 437 /* Enable LTDC */ 438 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 439 440 drm_crtc_vblank_on(crtc); 441 } 442 443 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 444 struct drm_crtc_state *old_state) 445 { 446 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 447 448 DRM_DEBUG_DRIVER("\n"); 449 450 drm_crtc_vblank_off(crtc); 451 452 /* disable LTDC */ 453 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 454 455 /* disable IRQ */ 456 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 457 458 /* immediately commit disable of layers before switching off LTDC */ 459 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 460 } 461 462 #define CLK_TOLERANCE_HZ 50 463 464 static enum drm_mode_status 465 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 466 const struct drm_display_mode *mode) 467 { 468 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 469 int target = mode->clock * 1000; 470 int target_min = target - CLK_TOLERANCE_HZ; 471 int target_max = target + CLK_TOLERANCE_HZ; 472 int result; 473 474 result = clk_round_rate(ldev->pixel_clk, target); 475 476 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 477 478 /* Filter modes according to the max frequency supported by the pads */ 479 if (result > ldev->caps.pad_max_freq_hz) 480 return MODE_CLOCK_HIGH; 481 482 /* 483 * Accept all "preferred" modes: 484 * - this is important for panels because panel clock tolerances are 485 * bigger than hdmi ones and there is no reason to not accept them 486 * (the fps may vary a little but it is not a problem). 487 * - the hdmi preferred mode will be accepted too, but userland will 488 * be able to use others hdmi "valid" modes if necessary. 489 */ 490 if (mode->type & DRM_MODE_TYPE_PREFERRED) 491 return MODE_OK; 492 493 /* 494 * Filter modes according to the clock value, particularly useful for 495 * hdmi modes that require precise pixel clocks. 496 */ 497 if (result < target_min || result > target_max) 498 return MODE_CLOCK_RANGE; 499 500 return MODE_OK; 501 } 502 503 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 504 const struct drm_display_mode *mode, 505 struct drm_display_mode *adjusted_mode) 506 { 507 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 508 int rate = mode->clock * 1000; 509 510 clk_disable(ldev->pixel_clk); 511 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 512 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 513 return false; 514 } 515 clk_enable(ldev->pixel_clk); 516 517 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 518 519 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 520 mode->clock, adjusted_mode->clock); 521 522 return true; 523 } 524 525 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 526 { 527 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 528 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 529 struct videomode vm; 530 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 531 u32 total_width, total_height; 532 u32 val; 533 534 drm_display_mode_to_videomode(mode, &vm); 535 536 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 537 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 538 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 539 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 540 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 541 542 /* Convert video timings to ltdc timings */ 543 hsync = vm.hsync_len - 1; 544 vsync = vm.vsync_len - 1; 545 accum_hbp = hsync + vm.hback_porch; 546 accum_vbp = vsync + vm.vback_porch; 547 accum_act_w = accum_hbp + vm.hactive; 548 accum_act_h = accum_vbp + vm.vactive; 549 total_width = accum_act_w + vm.hfront_porch; 550 total_height = accum_act_h + vm.vfront_porch; 551 552 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 553 val = 0; 554 555 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 556 val |= GCR_HSPOL; 557 558 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 559 val |= GCR_VSPOL; 560 561 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 562 val |= GCR_DEPOL; 563 564 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 565 val |= GCR_PCPOL; 566 567 reg_update_bits(ldev->regs, LTDC_GCR, 568 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 569 570 /* Set Synchronization size */ 571 val = (hsync << 16) | vsync; 572 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 573 574 /* Set Accumulated Back porch */ 575 val = (accum_hbp << 16) | accum_vbp; 576 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 577 578 /* Set Accumulated Active Width */ 579 val = (accum_act_w << 16) | accum_act_h; 580 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 581 582 /* Set total width & height */ 583 val = (total_width << 16) | total_height; 584 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 585 586 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 587 } 588 589 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 590 struct drm_crtc_state *old_crtc_state) 591 { 592 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 593 struct drm_pending_vblank_event *event = crtc->state->event; 594 595 DRM_DEBUG_ATOMIC("\n"); 596 597 ltdc_crtc_update_clut(crtc); 598 599 /* Commit shadow registers = update planes at next vblank */ 600 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 601 602 if (event) { 603 crtc->state->event = NULL; 604 605 spin_lock_irq(&crtc->dev->event_lock); 606 if (drm_crtc_vblank_get(crtc) == 0) 607 drm_crtc_arm_vblank_event(crtc, event); 608 else 609 drm_crtc_send_vblank_event(crtc, event); 610 spin_unlock_irq(&crtc->dev->event_lock); 611 } 612 } 613 614 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 615 .mode_valid = ltdc_crtc_mode_valid, 616 .mode_fixup = ltdc_crtc_mode_fixup, 617 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 618 .atomic_flush = ltdc_crtc_atomic_flush, 619 .atomic_enable = ltdc_crtc_atomic_enable, 620 .atomic_disable = ltdc_crtc_atomic_disable, 621 }; 622 623 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 624 { 625 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 626 627 DRM_DEBUG_DRIVER("\n"); 628 reg_set(ldev->regs, LTDC_IER, IER_LIE); 629 630 return 0; 631 } 632 633 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 634 { 635 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 636 637 DRM_DEBUG_DRIVER("\n"); 638 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 639 } 640 641 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 642 bool in_vblank_irq, int *vpos, int *hpos, 643 ktime_t *stime, ktime_t *etime, 644 const struct drm_display_mode *mode) 645 { 646 struct ltdc_device *ldev = ddev->dev_private; 647 int line, vactive_start, vactive_end, vtotal; 648 649 if (stime) 650 *stime = ktime_get(); 651 652 /* The active area starts after vsync + front porch and ends 653 * at vsync + front porc + display size. 654 * The total height also include back porch. 655 * We have 3 possible cases to handle: 656 * - line < vactive_start: vpos = line - vactive_start and will be 657 * negative 658 * - vactive_start < line < vactive_end: vpos = line - vactive_start 659 * and will be positive 660 * - line > vactive_end: vpos = line - vtotal - vactive_start 661 * and will negative 662 * 663 * Computation for the two first cases are identical so we can 664 * simplify the code and only test if line > vactive_end 665 */ 666 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 667 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 668 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 669 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 670 671 if (line > vactive_end) 672 *vpos = line - vtotal - vactive_start; 673 else 674 *vpos = line - vactive_start; 675 676 *hpos = 0; 677 678 if (etime) 679 *etime = ktime_get(); 680 681 return true; 682 } 683 684 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 685 .destroy = drm_crtc_cleanup, 686 .set_config = drm_atomic_helper_set_config, 687 .page_flip = drm_atomic_helper_page_flip, 688 .reset = drm_atomic_helper_crtc_reset, 689 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 690 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 691 .enable_vblank = ltdc_crtc_enable_vblank, 692 .disable_vblank = ltdc_crtc_disable_vblank, 693 .gamma_set = drm_atomic_helper_legacy_gamma_set, 694 }; 695 696 /* 697 * DRM_PLANE 698 */ 699 700 static int ltdc_plane_atomic_check(struct drm_plane *plane, 701 struct drm_plane_state *state) 702 { 703 struct drm_framebuffer *fb = state->fb; 704 u32 src_w, src_h; 705 706 DRM_DEBUG_DRIVER("\n"); 707 708 if (!fb) 709 return 0; 710 711 /* convert src_ from 16:16 format */ 712 src_w = state->src_w >> 16; 713 src_h = state->src_h >> 16; 714 715 /* Reject scaling */ 716 if (src_w != state->crtc_w || src_h != state->crtc_h) { 717 DRM_ERROR("Scaling is not supported"); 718 return -EINVAL; 719 } 720 721 return 0; 722 } 723 724 static void ltdc_plane_atomic_update(struct drm_plane *plane, 725 struct drm_plane_state *oldstate) 726 { 727 struct ltdc_device *ldev = plane_to_ltdc(plane); 728 struct drm_plane_state *state = plane->state; 729 struct drm_framebuffer *fb = state->fb; 730 u32 lofs = plane->index * LAY_OFS; 731 u32 x0 = state->crtc_x; 732 u32 x1 = state->crtc_x + state->crtc_w - 1; 733 u32 y0 = state->crtc_y; 734 u32 y1 = state->crtc_y + state->crtc_h - 1; 735 u32 src_x, src_y, src_w, src_h; 736 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 737 enum ltdc_pix_fmt pf; 738 739 if (!state->crtc || !fb) { 740 DRM_DEBUG_DRIVER("fb or crtc NULL"); 741 return; 742 } 743 744 /* convert src_ from 16:16 format */ 745 src_x = state->src_x >> 16; 746 src_y = state->src_y >> 16; 747 src_w = state->src_w >> 16; 748 src_h = state->src_h >> 16; 749 750 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 751 plane->base.id, fb->base.id, 752 src_w, src_h, src_x, src_y, 753 state->crtc_w, state->crtc_h, 754 state->crtc_x, state->crtc_y); 755 756 bpcr = reg_read(ldev->regs, LTDC_BPCR); 757 ahbp = (bpcr & BPCR_AHBP) >> 16; 758 avbp = bpcr & BPCR_AVBP; 759 760 /* Configures the horizontal start and stop position */ 761 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 762 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 763 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 764 765 /* Configures the vertical start and stop position */ 766 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 767 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 768 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 769 770 /* Specifies the pixel format */ 771 pf = to_ltdc_pixelformat(fb->format->format); 772 for (val = 0; val < NB_PF; val++) 773 if (ldev->caps.pix_fmt_hw[val] == pf) 774 break; 775 776 if (val == NB_PF) { 777 DRM_ERROR("Pixel format %.4s not supported\n", 778 (char *)&fb->format->format); 779 val = 0; /* set by default ARGB 32 bits */ 780 } 781 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 782 783 /* Configures the color frame buffer pitch in bytes & line length */ 784 pitch_in_bytes = fb->pitches[0]; 785 line_length = fb->format->cpp[0] * 786 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 787 val = ((pitch_in_bytes << 16) | line_length); 788 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 789 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 790 791 /* Specifies the constant alpha value */ 792 val = CONSTA_MAX; 793 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 794 795 /* Specifies the blending factors */ 796 val = BF1_PAXCA | BF2_1PAXCA; 797 if (!fb->format->has_alpha) 798 val = BF1_CA | BF2_1CA; 799 800 /* Manage hw-specific capabilities */ 801 if (ldev->caps.non_alpha_only_l1 && 802 plane->type != DRM_PLANE_TYPE_PRIMARY) 803 val = BF1_PAXCA | BF2_1PAXCA; 804 805 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 806 LXBFCR_BF2 | LXBFCR_BF1, val); 807 808 /* Configures the frame buffer line number */ 809 val = y1 - y0 + 1; 810 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 811 812 /* Sets the FB address */ 813 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 814 815 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 816 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 817 818 /* Enable layer and CLUT if needed */ 819 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 820 val |= LXCR_LEN; 821 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 822 LXCR_LEN | LXCR_CLUTEN, val); 823 824 ldev->plane_fpsi[plane->index].counter++; 825 826 mutex_lock(&ldev->err_lock); 827 if (ldev->error_status & ISR_FUIF) { 828 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 829 ldev->error_status &= ~ISR_FUIF; 830 } 831 if (ldev->error_status & ISR_TERRIF) { 832 DRM_WARN("ltdc transfer error\n"); 833 ldev->error_status &= ~ISR_TERRIF; 834 } 835 mutex_unlock(&ldev->err_lock); 836 } 837 838 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 839 struct drm_plane_state *oldstate) 840 { 841 struct ltdc_device *ldev = plane_to_ltdc(plane); 842 u32 lofs = plane->index * LAY_OFS; 843 844 /* disable layer */ 845 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 846 847 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 848 oldstate->crtc->base.id, plane->base.id); 849 } 850 851 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 852 const struct drm_plane_state *state) 853 { 854 struct drm_plane *plane = state->plane; 855 struct ltdc_device *ldev = plane_to_ltdc(plane); 856 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 857 int ms_since_last; 858 ktime_t now; 859 860 now = ktime_get(); 861 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 862 863 drm_printf(p, "\tuser_updates=%dfps\n", 864 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 865 866 fpsi->last_timestamp = now; 867 fpsi->counter = 0; 868 } 869 870 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 871 u32 format, 872 u64 modifier) 873 { 874 if (modifier == DRM_FORMAT_MOD_LINEAR) 875 return true; 876 877 return false; 878 } 879 880 static const struct drm_plane_funcs ltdc_plane_funcs = { 881 .update_plane = drm_atomic_helper_update_plane, 882 .disable_plane = drm_atomic_helper_disable_plane, 883 .destroy = drm_plane_cleanup, 884 .reset = drm_atomic_helper_plane_reset, 885 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 886 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 887 .atomic_print_state = ltdc_plane_atomic_print_state, 888 .format_mod_supported = ltdc_plane_format_mod_supported, 889 }; 890 891 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 892 .atomic_check = ltdc_plane_atomic_check, 893 .atomic_update = ltdc_plane_atomic_update, 894 .atomic_disable = ltdc_plane_atomic_disable, 895 }; 896 897 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 898 enum drm_plane_type type) 899 { 900 unsigned long possible_crtcs = CRTC_MASK; 901 struct ltdc_device *ldev = ddev->dev_private; 902 struct device *dev = ddev->dev; 903 struct drm_plane *plane; 904 unsigned int i, nb_fmt = 0; 905 u32 formats[NB_PF * 2]; 906 u32 drm_fmt, drm_fmt_no_alpha; 907 const u64 *modifiers = ltdc_format_modifiers; 908 int ret; 909 910 /* Get supported pixel formats */ 911 for (i = 0; i < NB_PF; i++) { 912 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 913 if (!drm_fmt) 914 continue; 915 formats[nb_fmt++] = drm_fmt; 916 917 /* Add the no-alpha related format if any & supported */ 918 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 919 if (!drm_fmt_no_alpha) 920 continue; 921 922 /* Manage hw-specific capabilities */ 923 if (ldev->caps.non_alpha_only_l1 && 924 type != DRM_PLANE_TYPE_PRIMARY) 925 continue; 926 927 formats[nb_fmt++] = drm_fmt_no_alpha; 928 } 929 930 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 931 if (!plane) 932 return NULL; 933 934 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 935 <dc_plane_funcs, formats, nb_fmt, 936 modifiers, type, NULL); 937 if (ret < 0) 938 return NULL; 939 940 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 941 942 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 943 944 return plane; 945 } 946 947 static void ltdc_plane_destroy_all(struct drm_device *ddev) 948 { 949 struct drm_plane *plane, *plane_temp; 950 951 list_for_each_entry_safe(plane, plane_temp, 952 &ddev->mode_config.plane_list, head) 953 drm_plane_cleanup(plane); 954 } 955 956 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 957 { 958 struct ltdc_device *ldev = ddev->dev_private; 959 struct drm_plane *primary, *overlay; 960 unsigned int i; 961 int ret; 962 963 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 964 if (!primary) { 965 DRM_ERROR("Can not create primary plane\n"); 966 return -EINVAL; 967 } 968 969 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 970 <dc_crtc_funcs, NULL); 971 if (ret) { 972 DRM_ERROR("Can not initialize CRTC\n"); 973 goto cleanup; 974 } 975 976 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 977 978 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 979 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 980 981 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 982 983 /* Add planes. Note : the first layer is used by primary plane */ 984 for (i = 1; i < ldev->caps.nb_layers; i++) { 985 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 986 if (!overlay) { 987 ret = -ENOMEM; 988 DRM_ERROR("Can not create overlay plane %d\n", i); 989 goto cleanup; 990 } 991 } 992 993 return 0; 994 995 cleanup: 996 ltdc_plane_destroy_all(ddev); 997 return ret; 998 } 999 1000 /* 1001 * DRM_ENCODER 1002 */ 1003 1004 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1005 .destroy = drm_encoder_cleanup, 1006 }; 1007 1008 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1009 { 1010 struct drm_encoder *encoder; 1011 int ret; 1012 1013 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1014 if (!encoder) 1015 return -ENOMEM; 1016 1017 encoder->possible_crtcs = CRTC_MASK; 1018 encoder->possible_clones = 0; /* No cloning support */ 1019 1020 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1021 DRM_MODE_ENCODER_DPI, NULL); 1022 1023 ret = drm_bridge_attach(encoder, bridge, NULL); 1024 if (ret) { 1025 drm_encoder_cleanup(encoder); 1026 return -EINVAL; 1027 } 1028 1029 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1030 1031 return 0; 1032 } 1033 1034 static int ltdc_get_caps(struct drm_device *ddev) 1035 { 1036 struct ltdc_device *ldev = ddev->dev_private; 1037 u32 bus_width_log2, lcr, gc2r; 1038 1039 /* 1040 * at least 1 layer must be managed & the number of layers 1041 * must not exceed LTDC_MAX_LAYER 1042 */ 1043 lcr = reg_read(ldev->regs, LTDC_LCR); 1044 1045 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1046 1047 /* set data bus width */ 1048 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1049 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1050 ldev->caps.bus_width = 8 << bus_width_log2; 1051 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1052 1053 switch (ldev->caps.hw_version) { 1054 case HWVER_10200: 1055 case HWVER_10300: 1056 ldev->caps.reg_ofs = REG_OFS_NONE; 1057 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1058 /* 1059 * Hw older versions support non-alpha color formats derived 1060 * from native alpha color formats only on the primary layer. 1061 * For instance, RG16 native format without alpha works fine 1062 * on 2nd layer but XR24 (derived color format from AR24) 1063 * does not work on 2nd layer. 1064 */ 1065 ldev->caps.non_alpha_only_l1 = true; 1066 ldev->caps.pad_max_freq_hz = 90000000; 1067 if (ldev->caps.hw_version == HWVER_10200) 1068 ldev->caps.pad_max_freq_hz = 65000000; 1069 break; 1070 case HWVER_20101: 1071 ldev->caps.reg_ofs = REG_OFS_4; 1072 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1073 ldev->caps.non_alpha_only_l1 = false; 1074 ldev->caps.pad_max_freq_hz = 150000000; 1075 break; 1076 default: 1077 return -ENODEV; 1078 } 1079 1080 return 0; 1081 } 1082 1083 void ltdc_suspend(struct drm_device *ddev) 1084 { 1085 struct ltdc_device *ldev = ddev->dev_private; 1086 1087 DRM_DEBUG_DRIVER("\n"); 1088 clk_disable_unprepare(ldev->pixel_clk); 1089 } 1090 1091 int ltdc_resume(struct drm_device *ddev) 1092 { 1093 struct ltdc_device *ldev = ddev->dev_private; 1094 int ret; 1095 1096 DRM_DEBUG_DRIVER("\n"); 1097 1098 ret = clk_prepare_enable(ldev->pixel_clk); 1099 if (ret) { 1100 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1101 return ret; 1102 } 1103 1104 return 0; 1105 } 1106 1107 int ltdc_load(struct drm_device *ddev) 1108 { 1109 struct platform_device *pdev = to_platform_device(ddev->dev); 1110 struct ltdc_device *ldev = ddev->dev_private; 1111 struct device *dev = ddev->dev; 1112 struct device_node *np = dev->of_node; 1113 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1114 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1115 struct drm_crtc *crtc; 1116 struct reset_control *rstc; 1117 struct resource *res; 1118 int irq, ret, i, endpoint_not_ready = -ENODEV; 1119 1120 DRM_DEBUG_DRIVER("\n"); 1121 1122 /* Get endpoints if any */ 1123 for (i = 0; i < MAX_ENDPOINTS; i++) { 1124 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1125 &bridge[i]); 1126 1127 /* 1128 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1129 * else if at least one endpoint is ready, continue probing. 1130 */ 1131 if (ret == -EPROBE_DEFER) 1132 return ret; 1133 else if (!ret) 1134 endpoint_not_ready = 0; 1135 } 1136 1137 if (endpoint_not_ready) 1138 return endpoint_not_ready; 1139 1140 rstc = devm_reset_control_get_exclusive(dev, NULL); 1141 1142 mutex_init(&ldev->err_lock); 1143 1144 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1145 if (IS_ERR(ldev->pixel_clk)) { 1146 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1147 DRM_ERROR("Unable to get lcd clock\n"); 1148 return PTR_ERR(ldev->pixel_clk); 1149 } 1150 1151 if (clk_prepare_enable(ldev->pixel_clk)) { 1152 DRM_ERROR("Unable to prepare pixel clock\n"); 1153 return -ENODEV; 1154 } 1155 1156 if (!IS_ERR(rstc)) { 1157 reset_control_assert(rstc); 1158 usleep_range(10, 20); 1159 reset_control_deassert(rstc); 1160 } 1161 1162 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1163 ldev->regs = devm_ioremap_resource(dev, res); 1164 if (IS_ERR(ldev->regs)) { 1165 DRM_ERROR("Unable to get ltdc registers\n"); 1166 ret = PTR_ERR(ldev->regs); 1167 goto err; 1168 } 1169 1170 /* Disable interrupts */ 1171 reg_clear(ldev->regs, LTDC_IER, 1172 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1173 1174 for (i = 0; i < MAX_IRQ; i++) { 1175 irq = platform_get_irq(pdev, i); 1176 if (irq == -EPROBE_DEFER) 1177 goto err; 1178 1179 if (irq < 0) 1180 continue; 1181 1182 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1183 ltdc_irq_thread, IRQF_ONESHOT, 1184 dev_name(dev), ddev); 1185 if (ret) { 1186 DRM_ERROR("Failed to register LTDC interrupt\n"); 1187 goto err; 1188 } 1189 } 1190 1191 1192 ret = ltdc_get_caps(ddev); 1193 if (ret) { 1194 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1195 ldev->caps.hw_version); 1196 goto err; 1197 } 1198 1199 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 1200 1201 /* Add endpoints panels or bridges if any */ 1202 for (i = 0; i < MAX_ENDPOINTS; i++) { 1203 if (panel[i]) { 1204 bridge[i] = drm_panel_bridge_add(panel[i], 1205 DRM_MODE_CONNECTOR_DPI); 1206 if (IS_ERR(bridge[i])) { 1207 DRM_ERROR("panel-bridge endpoint %d\n", i); 1208 ret = PTR_ERR(bridge[i]); 1209 goto err; 1210 } 1211 } 1212 1213 if (bridge[i]) { 1214 ret = ltdc_encoder_init(ddev, bridge[i]); 1215 if (ret) { 1216 DRM_ERROR("init encoder endpoint %d\n", i); 1217 goto err; 1218 } 1219 } 1220 } 1221 1222 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1223 if (!crtc) { 1224 DRM_ERROR("Failed to allocate crtc\n"); 1225 ret = -ENOMEM; 1226 goto err; 1227 } 1228 1229 ddev->mode_config.allow_fb_modifiers = true; 1230 1231 ret = ltdc_crtc_init(ddev, crtc); 1232 if (ret) { 1233 DRM_ERROR("Failed to init crtc\n"); 1234 goto err; 1235 } 1236 1237 ret = drm_vblank_init(ddev, NB_CRTC); 1238 if (ret) { 1239 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1240 goto err; 1241 } 1242 1243 /* Allow usage of vblank without having to call drm_irq_install */ 1244 ddev->irq_enabled = 1; 1245 1246 return 0; 1247 1248 err: 1249 for (i = 0; i < MAX_ENDPOINTS; i++) 1250 drm_panel_bridge_remove(bridge[i]); 1251 1252 clk_disable_unprepare(ldev->pixel_clk); 1253 1254 return ret; 1255 } 1256 1257 void ltdc_unload(struct drm_device *ddev) 1258 { 1259 struct ltdc_device *ldev = ddev->dev_private; 1260 int i; 1261 1262 DRM_DEBUG_DRIVER("\n"); 1263 1264 for (i = 0; i < MAX_ENDPOINTS; i++) 1265 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1266 1267 clk_disable_unprepare(ldev->pixel_clk); 1268 } 1269 1270 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1271 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1272 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1273 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1274 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1275 MODULE_LICENSE("GPL v2"); 1276