1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_device.h> 26 #include <drm/drm_fb_cma_helper.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_gem_cma_helper.h> 29 #include <drm/drm_gem_framebuffer_helper.h> 30 #include <drm/drm_of.h> 31 #include <drm/drm_plane_helper.h> 32 #include <drm/drm_probe_helper.h> 33 #include <drm/drm_vblank.h> 34 35 #include <video/videomode.h> 36 37 #include "ltdc.h" 38 39 #define NB_CRTC 1 40 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 41 42 #define MAX_IRQ 4 43 44 #define MAX_ENDPOINTS 2 45 46 #define HWVER_10200 0x010200 47 #define HWVER_10300 0x010300 48 #define HWVER_20101 0x020101 49 50 /* 51 * The address of some registers depends on the HW version: such registers have 52 * an extra offset specified with reg_ofs. 53 */ 54 #define REG_OFS_NONE 0 55 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 56 #define REG_OFS (ldev->caps.reg_ofs) 57 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 58 59 /* Global register offsets */ 60 #define LTDC_IDR 0x0000 /* IDentification */ 61 #define LTDC_LCR 0x0004 /* Layer Count */ 62 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 63 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 64 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 65 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 66 #define LTDC_GCR 0x0018 /* Global Control */ 67 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 68 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 69 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 70 #define LTDC_GACR 0x0028 /* GAmma Correction */ 71 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 72 #define LTDC_IER 0x0034 /* Interrupt Enable */ 73 #define LTDC_ISR 0x0038 /* Interrupt Status */ 74 #define LTDC_ICR 0x003C /* Interrupt Clear */ 75 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 76 #define LTDC_CPSR 0x0044 /* Current Position Status */ 77 #define LTDC_CDSR 0x0048 /* Current Display Status */ 78 79 /* Layer register offsets */ 80 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 81 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 82 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 83 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 84 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 85 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 86 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 87 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 88 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 89 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 90 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 91 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 92 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 93 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 94 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 95 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 96 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 97 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 98 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 99 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 100 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 101 102 /* Bit definitions */ 103 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 104 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 105 106 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 107 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 108 109 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 110 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 111 112 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 113 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 114 115 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 116 #define GCR_DEN BIT(16) /* Dither ENable */ 117 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 118 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 119 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 120 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 121 122 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 123 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 124 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 125 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 126 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 127 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 128 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 129 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 130 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 131 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 132 #define GC1R_TP BIT(25) /* Timing Programmable */ 133 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 134 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 135 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 136 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 137 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 138 139 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 140 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 141 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 142 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 143 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 144 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 145 146 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 147 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 148 149 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 150 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 151 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 152 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 153 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 154 155 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 156 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 157 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 158 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 159 160 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 161 162 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 163 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 164 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 165 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 166 167 #define LXCR_LEN BIT(0) /* Layer ENable */ 168 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 169 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 170 171 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 172 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 173 174 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 175 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 176 177 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 178 179 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 180 181 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 182 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 183 184 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 185 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 186 187 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 188 189 #define CLUT_SIZE 256 190 191 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 192 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 193 #define BF1_CA 0x400 /* Constant Alpha */ 194 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 195 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 196 197 #define NB_PF 8 /* Max nb of HW pixel format */ 198 199 enum ltdc_pix_fmt { 200 PF_NONE, 201 /* RGB formats */ 202 PF_ARGB8888, /* ARGB [32 bits] */ 203 PF_RGBA8888, /* RGBA [32 bits] */ 204 PF_RGB888, /* RGB [24 bits] */ 205 PF_RGB565, /* RGB [16 bits] */ 206 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 207 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 208 /* Indexed formats */ 209 PF_L8, /* Indexed 8 bits [8 bits] */ 210 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 211 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 212 }; 213 214 /* The index gives the encoding of the pixel format for an HW version */ 215 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 216 PF_ARGB8888, /* 0x00 */ 217 PF_RGB888, /* 0x01 */ 218 PF_RGB565, /* 0x02 */ 219 PF_ARGB1555, /* 0x03 */ 220 PF_ARGB4444, /* 0x04 */ 221 PF_L8, /* 0x05 */ 222 PF_AL44, /* 0x06 */ 223 PF_AL88 /* 0x07 */ 224 }; 225 226 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 227 PF_ARGB8888, /* 0x00 */ 228 PF_RGB888, /* 0x01 */ 229 PF_RGB565, /* 0x02 */ 230 PF_RGBA8888, /* 0x03 */ 231 PF_AL44, /* 0x04 */ 232 PF_L8, /* 0x05 */ 233 PF_ARGB1555, /* 0x06 */ 234 PF_ARGB4444 /* 0x07 */ 235 }; 236 237 static const u64 ltdc_format_modifiers[] = { 238 DRM_FORMAT_MOD_LINEAR, 239 DRM_FORMAT_MOD_INVALID 240 }; 241 242 static inline u32 reg_read(void __iomem *base, u32 reg) 243 { 244 return readl_relaxed(base + reg); 245 } 246 247 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 248 { 249 writel_relaxed(val, base + reg); 250 } 251 252 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 253 { 254 reg_write(base, reg, reg_read(base, reg) | mask); 255 } 256 257 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 258 { 259 reg_write(base, reg, reg_read(base, reg) & ~mask); 260 } 261 262 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 263 u32 val) 264 { 265 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 266 } 267 268 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 269 { 270 return (struct ltdc_device *)crtc->dev->dev_private; 271 } 272 273 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 274 { 275 return (struct ltdc_device *)plane->dev->dev_private; 276 } 277 278 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 279 { 280 return (struct ltdc_device *)enc->dev->dev_private; 281 } 282 283 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 284 { 285 enum ltdc_pix_fmt pf; 286 287 switch (drm_fmt) { 288 case DRM_FORMAT_ARGB8888: 289 case DRM_FORMAT_XRGB8888: 290 pf = PF_ARGB8888; 291 break; 292 case DRM_FORMAT_RGBA8888: 293 case DRM_FORMAT_RGBX8888: 294 pf = PF_RGBA8888; 295 break; 296 case DRM_FORMAT_RGB888: 297 pf = PF_RGB888; 298 break; 299 case DRM_FORMAT_RGB565: 300 pf = PF_RGB565; 301 break; 302 case DRM_FORMAT_ARGB1555: 303 case DRM_FORMAT_XRGB1555: 304 pf = PF_ARGB1555; 305 break; 306 case DRM_FORMAT_ARGB4444: 307 case DRM_FORMAT_XRGB4444: 308 pf = PF_ARGB4444; 309 break; 310 case DRM_FORMAT_C8: 311 pf = PF_L8; 312 break; 313 default: 314 pf = PF_NONE; 315 break; 316 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 317 } 318 319 return pf; 320 } 321 322 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 323 { 324 switch (pf) { 325 case PF_ARGB8888: 326 return DRM_FORMAT_ARGB8888; 327 case PF_RGBA8888: 328 return DRM_FORMAT_RGBA8888; 329 case PF_RGB888: 330 return DRM_FORMAT_RGB888; 331 case PF_RGB565: 332 return DRM_FORMAT_RGB565; 333 case PF_ARGB1555: 334 return DRM_FORMAT_ARGB1555; 335 case PF_ARGB4444: 336 return DRM_FORMAT_ARGB4444; 337 case PF_L8: 338 return DRM_FORMAT_C8; 339 case PF_AL44: /* No DRM support */ 340 case PF_AL88: /* No DRM support */ 341 case PF_NONE: 342 default: 343 return 0; 344 } 345 } 346 347 static inline u32 get_pixelformat_without_alpha(u32 drm) 348 { 349 switch (drm) { 350 case DRM_FORMAT_ARGB4444: 351 return DRM_FORMAT_XRGB4444; 352 case DRM_FORMAT_RGBA4444: 353 return DRM_FORMAT_RGBX4444; 354 case DRM_FORMAT_ARGB1555: 355 return DRM_FORMAT_XRGB1555; 356 case DRM_FORMAT_RGBA5551: 357 return DRM_FORMAT_RGBX5551; 358 case DRM_FORMAT_ARGB8888: 359 return DRM_FORMAT_XRGB8888; 360 case DRM_FORMAT_RGBA8888: 361 return DRM_FORMAT_RGBX8888; 362 default: 363 return 0; 364 } 365 } 366 367 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 368 { 369 struct drm_device *ddev = arg; 370 struct ltdc_device *ldev = ddev->dev_private; 371 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 372 373 /* Line IRQ : trigger the vblank event */ 374 if (ldev->irq_status & ISR_LIF) 375 drm_crtc_handle_vblank(crtc); 376 377 /* Save FIFO Underrun & Transfer Error status */ 378 mutex_lock(&ldev->err_lock); 379 if (ldev->irq_status & ISR_FUIF) 380 ldev->error_status |= ISR_FUIF; 381 if (ldev->irq_status & ISR_TERRIF) 382 ldev->error_status |= ISR_TERRIF; 383 mutex_unlock(&ldev->err_lock); 384 385 return IRQ_HANDLED; 386 } 387 388 static irqreturn_t ltdc_irq(int irq, void *arg) 389 { 390 struct drm_device *ddev = arg; 391 struct ltdc_device *ldev = ddev->dev_private; 392 393 /* Read & Clear the interrupt status */ 394 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 395 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 396 397 return IRQ_WAKE_THREAD; 398 } 399 400 /* 401 * DRM_CRTC 402 */ 403 404 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 405 { 406 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 407 struct drm_color_lut *lut; 408 u32 val; 409 int i; 410 411 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 412 return; 413 414 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 415 416 for (i = 0; i < CLUT_SIZE; i++, lut++) { 417 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 418 (lut->blue >> 8) | (i << 24); 419 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 420 } 421 } 422 423 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 424 struct drm_crtc_state *old_state) 425 { 426 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 427 428 DRM_DEBUG_DRIVER("\n"); 429 430 /* Sets the background color value */ 431 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 432 433 /* Enable IRQ */ 434 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 435 436 /* Commit shadow registers = update planes at next vblank */ 437 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 438 439 /* Enable LTDC */ 440 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 441 442 drm_crtc_vblank_on(crtc); 443 } 444 445 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 446 struct drm_crtc_state *old_state) 447 { 448 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 449 struct drm_device *ddev = crtc->dev; 450 451 DRM_DEBUG_DRIVER("\n"); 452 453 drm_crtc_vblank_off(crtc); 454 455 /* disable LTDC */ 456 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 457 458 /* disable IRQ */ 459 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 460 461 /* immediately commit disable of layers before switching off LTDC */ 462 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 463 464 pm_runtime_put_sync(ddev->dev); 465 } 466 467 #define CLK_TOLERANCE_HZ 50 468 469 static enum drm_mode_status 470 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 471 const struct drm_display_mode *mode) 472 { 473 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 474 int target = mode->clock * 1000; 475 int target_min = target - CLK_TOLERANCE_HZ; 476 int target_max = target + CLK_TOLERANCE_HZ; 477 int result; 478 479 result = clk_round_rate(ldev->pixel_clk, target); 480 481 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 482 483 /* Filter modes according to the max frequency supported by the pads */ 484 if (result > ldev->caps.pad_max_freq_hz) 485 return MODE_CLOCK_HIGH; 486 487 /* 488 * Accept all "preferred" modes: 489 * - this is important for panels because panel clock tolerances are 490 * bigger than hdmi ones and there is no reason to not accept them 491 * (the fps may vary a little but it is not a problem). 492 * - the hdmi preferred mode will be accepted too, but userland will 493 * be able to use others hdmi "valid" modes if necessary. 494 */ 495 if (mode->type & DRM_MODE_TYPE_PREFERRED) 496 return MODE_OK; 497 498 /* 499 * Filter modes according to the clock value, particularly useful for 500 * hdmi modes that require precise pixel clocks. 501 */ 502 if (result < target_min || result > target_max) 503 return MODE_CLOCK_RANGE; 504 505 return MODE_OK; 506 } 507 508 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 509 const struct drm_display_mode *mode, 510 struct drm_display_mode *adjusted_mode) 511 { 512 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 513 struct drm_device *ddev = crtc->dev; 514 int rate = mode->clock * 1000; 515 bool runtime_active; 516 int ret; 517 518 runtime_active = pm_runtime_active(ddev->dev); 519 520 if (runtime_active) 521 pm_runtime_put_sync(ddev->dev); 522 523 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 524 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 525 return false; 526 } 527 528 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 529 530 if (runtime_active) { 531 ret = pm_runtime_get_sync(ddev->dev); 532 if (ret) { 533 DRM_ERROR("Failed to fixup mode, cannot get sync\n"); 534 return false; 535 } 536 } 537 538 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 539 mode->clock, adjusted_mode->clock); 540 541 return true; 542 } 543 544 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 545 { 546 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 547 struct drm_device *ddev = crtc->dev; 548 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 549 struct videomode vm; 550 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 551 u32 total_width, total_height; 552 u32 val; 553 int ret; 554 555 if (!pm_runtime_active(ddev->dev)) { 556 ret = pm_runtime_get_sync(ddev->dev); 557 if (ret) { 558 DRM_ERROR("Failed to set mode, cannot get sync\n"); 559 return; 560 } 561 } 562 563 drm_display_mode_to_videomode(mode, &vm); 564 565 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 566 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 567 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 568 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 569 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 570 571 /* Convert video timings to ltdc timings */ 572 hsync = vm.hsync_len - 1; 573 vsync = vm.vsync_len - 1; 574 accum_hbp = hsync + vm.hback_porch; 575 accum_vbp = vsync + vm.vback_porch; 576 accum_act_w = accum_hbp + vm.hactive; 577 accum_act_h = accum_vbp + vm.vactive; 578 total_width = accum_act_w + vm.hfront_porch; 579 total_height = accum_act_h + vm.vfront_porch; 580 581 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 582 val = 0; 583 584 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 585 val |= GCR_HSPOL; 586 587 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 588 val |= GCR_VSPOL; 589 590 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 591 val |= GCR_DEPOL; 592 593 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 594 val |= GCR_PCPOL; 595 596 reg_update_bits(ldev->regs, LTDC_GCR, 597 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 598 599 /* Set Synchronization size */ 600 val = (hsync << 16) | vsync; 601 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 602 603 /* Set Accumulated Back porch */ 604 val = (accum_hbp << 16) | accum_vbp; 605 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 606 607 /* Set Accumulated Active Width */ 608 val = (accum_act_w << 16) | accum_act_h; 609 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 610 611 /* Set total width & height */ 612 val = (total_width << 16) | total_height; 613 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 614 615 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 616 } 617 618 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 619 struct drm_crtc_state *old_crtc_state) 620 { 621 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 622 struct drm_device *ddev = crtc->dev; 623 struct drm_pending_vblank_event *event = crtc->state->event; 624 625 DRM_DEBUG_ATOMIC("\n"); 626 627 ltdc_crtc_update_clut(crtc); 628 629 /* Commit shadow registers = update planes at next vblank */ 630 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 631 632 if (event) { 633 crtc->state->event = NULL; 634 635 spin_lock_irq(&ddev->event_lock); 636 if (drm_crtc_vblank_get(crtc) == 0) 637 drm_crtc_arm_vblank_event(crtc, event); 638 else 639 drm_crtc_send_vblank_event(crtc, event); 640 spin_unlock_irq(&ddev->event_lock); 641 } 642 } 643 644 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 645 .mode_valid = ltdc_crtc_mode_valid, 646 .mode_fixup = ltdc_crtc_mode_fixup, 647 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 648 .atomic_flush = ltdc_crtc_atomic_flush, 649 .atomic_enable = ltdc_crtc_atomic_enable, 650 .atomic_disable = ltdc_crtc_atomic_disable, 651 }; 652 653 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 654 { 655 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 656 657 DRM_DEBUG_DRIVER("\n"); 658 reg_set(ldev->regs, LTDC_IER, IER_LIE); 659 660 return 0; 661 } 662 663 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 664 { 665 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 666 667 DRM_DEBUG_DRIVER("\n"); 668 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 669 } 670 671 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 672 bool in_vblank_irq, int *vpos, int *hpos, 673 ktime_t *stime, ktime_t *etime, 674 const struct drm_display_mode *mode) 675 { 676 struct ltdc_device *ldev = ddev->dev_private; 677 int line, vactive_start, vactive_end, vtotal; 678 679 if (stime) 680 *stime = ktime_get(); 681 682 /* The active area starts after vsync + front porch and ends 683 * at vsync + front porc + display size. 684 * The total height also include back porch. 685 * We have 3 possible cases to handle: 686 * - line < vactive_start: vpos = line - vactive_start and will be 687 * negative 688 * - vactive_start < line < vactive_end: vpos = line - vactive_start 689 * and will be positive 690 * - line > vactive_end: vpos = line - vtotal - vactive_start 691 * and will negative 692 * 693 * Computation for the two first cases are identical so we can 694 * simplify the code and only test if line > vactive_end 695 */ 696 if (pm_runtime_active(ddev->dev)) { 697 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 698 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 699 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 700 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 701 702 if (line > vactive_end) 703 *vpos = line - vtotal - vactive_start; 704 else 705 *vpos = line - vactive_start; 706 } else { 707 *vpos = 0; 708 } 709 710 *hpos = 0; 711 712 if (etime) 713 *etime = ktime_get(); 714 715 return true; 716 } 717 718 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 719 .destroy = drm_crtc_cleanup, 720 .set_config = drm_atomic_helper_set_config, 721 .page_flip = drm_atomic_helper_page_flip, 722 .reset = drm_atomic_helper_crtc_reset, 723 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 724 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 725 .enable_vblank = ltdc_crtc_enable_vblank, 726 .disable_vblank = ltdc_crtc_disable_vblank, 727 .gamma_set = drm_atomic_helper_legacy_gamma_set, 728 }; 729 730 /* 731 * DRM_PLANE 732 */ 733 734 static int ltdc_plane_atomic_check(struct drm_plane *plane, 735 struct drm_plane_state *state) 736 { 737 struct drm_framebuffer *fb = state->fb; 738 u32 src_w, src_h; 739 740 DRM_DEBUG_DRIVER("\n"); 741 742 if (!fb) 743 return 0; 744 745 /* convert src_ from 16:16 format */ 746 src_w = state->src_w >> 16; 747 src_h = state->src_h >> 16; 748 749 /* Reject scaling */ 750 if (src_w != state->crtc_w || src_h != state->crtc_h) { 751 DRM_ERROR("Scaling is not supported"); 752 return -EINVAL; 753 } 754 755 return 0; 756 } 757 758 static void ltdc_plane_atomic_update(struct drm_plane *plane, 759 struct drm_plane_state *oldstate) 760 { 761 struct ltdc_device *ldev = plane_to_ltdc(plane); 762 struct drm_plane_state *state = plane->state; 763 struct drm_framebuffer *fb = state->fb; 764 u32 lofs = plane->index * LAY_OFS; 765 u32 x0 = state->crtc_x; 766 u32 x1 = state->crtc_x + state->crtc_w - 1; 767 u32 y0 = state->crtc_y; 768 u32 y1 = state->crtc_y + state->crtc_h - 1; 769 u32 src_x, src_y, src_w, src_h; 770 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 771 enum ltdc_pix_fmt pf; 772 773 if (!state->crtc || !fb) { 774 DRM_DEBUG_DRIVER("fb or crtc NULL"); 775 return; 776 } 777 778 /* convert src_ from 16:16 format */ 779 src_x = state->src_x >> 16; 780 src_y = state->src_y >> 16; 781 src_w = state->src_w >> 16; 782 src_h = state->src_h >> 16; 783 784 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 785 plane->base.id, fb->base.id, 786 src_w, src_h, src_x, src_y, 787 state->crtc_w, state->crtc_h, 788 state->crtc_x, state->crtc_y); 789 790 bpcr = reg_read(ldev->regs, LTDC_BPCR); 791 ahbp = (bpcr & BPCR_AHBP) >> 16; 792 avbp = bpcr & BPCR_AVBP; 793 794 /* Configures the horizontal start and stop position */ 795 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 796 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 797 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 798 799 /* Configures the vertical start and stop position */ 800 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 801 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 802 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 803 804 /* Specifies the pixel format */ 805 pf = to_ltdc_pixelformat(fb->format->format); 806 for (val = 0; val < NB_PF; val++) 807 if (ldev->caps.pix_fmt_hw[val] == pf) 808 break; 809 810 if (val == NB_PF) { 811 DRM_ERROR("Pixel format %.4s not supported\n", 812 (char *)&fb->format->format); 813 val = 0; /* set by default ARGB 32 bits */ 814 } 815 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 816 817 /* Configures the color frame buffer pitch in bytes & line length */ 818 pitch_in_bytes = fb->pitches[0]; 819 line_length = fb->format->cpp[0] * 820 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 821 val = ((pitch_in_bytes << 16) | line_length); 822 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 823 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 824 825 /* Specifies the constant alpha value */ 826 val = CONSTA_MAX; 827 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 828 829 /* Specifies the blending factors */ 830 val = BF1_PAXCA | BF2_1PAXCA; 831 if (!fb->format->has_alpha) 832 val = BF1_CA | BF2_1CA; 833 834 /* Manage hw-specific capabilities */ 835 if (ldev->caps.non_alpha_only_l1 && 836 plane->type != DRM_PLANE_TYPE_PRIMARY) 837 val = BF1_PAXCA | BF2_1PAXCA; 838 839 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 840 LXBFCR_BF2 | LXBFCR_BF1, val); 841 842 /* Configures the frame buffer line number */ 843 val = y1 - y0 + 1; 844 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 845 846 /* Sets the FB address */ 847 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 848 849 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 850 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 851 852 /* Enable layer and CLUT if needed */ 853 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 854 val |= LXCR_LEN; 855 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 856 LXCR_LEN | LXCR_CLUTEN, val); 857 858 ldev->plane_fpsi[plane->index].counter++; 859 860 mutex_lock(&ldev->err_lock); 861 if (ldev->error_status & ISR_FUIF) { 862 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 863 ldev->error_status &= ~ISR_FUIF; 864 } 865 if (ldev->error_status & ISR_TERRIF) { 866 DRM_WARN("ltdc transfer error\n"); 867 ldev->error_status &= ~ISR_TERRIF; 868 } 869 mutex_unlock(&ldev->err_lock); 870 } 871 872 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 873 struct drm_plane_state *oldstate) 874 { 875 struct ltdc_device *ldev = plane_to_ltdc(plane); 876 u32 lofs = plane->index * LAY_OFS; 877 878 /* disable layer */ 879 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 880 881 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 882 oldstate->crtc->base.id, plane->base.id); 883 } 884 885 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 886 const struct drm_plane_state *state) 887 { 888 struct drm_plane *plane = state->plane; 889 struct ltdc_device *ldev = plane_to_ltdc(plane); 890 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 891 int ms_since_last; 892 ktime_t now; 893 894 now = ktime_get(); 895 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 896 897 drm_printf(p, "\tuser_updates=%dfps\n", 898 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 899 900 fpsi->last_timestamp = now; 901 fpsi->counter = 0; 902 } 903 904 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 905 u32 format, 906 u64 modifier) 907 { 908 if (modifier == DRM_FORMAT_MOD_LINEAR) 909 return true; 910 911 return false; 912 } 913 914 static const struct drm_plane_funcs ltdc_plane_funcs = { 915 .update_plane = drm_atomic_helper_update_plane, 916 .disable_plane = drm_atomic_helper_disable_plane, 917 .destroy = drm_plane_cleanup, 918 .reset = drm_atomic_helper_plane_reset, 919 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 920 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 921 .atomic_print_state = ltdc_plane_atomic_print_state, 922 .format_mod_supported = ltdc_plane_format_mod_supported, 923 }; 924 925 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 926 .prepare_fb = drm_gem_fb_prepare_fb, 927 .atomic_check = ltdc_plane_atomic_check, 928 .atomic_update = ltdc_plane_atomic_update, 929 .atomic_disable = ltdc_plane_atomic_disable, 930 }; 931 932 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 933 enum drm_plane_type type) 934 { 935 unsigned long possible_crtcs = CRTC_MASK; 936 struct ltdc_device *ldev = ddev->dev_private; 937 struct device *dev = ddev->dev; 938 struct drm_plane *plane; 939 unsigned int i, nb_fmt = 0; 940 u32 formats[NB_PF * 2]; 941 u32 drm_fmt, drm_fmt_no_alpha; 942 const u64 *modifiers = ltdc_format_modifiers; 943 int ret; 944 945 /* Get supported pixel formats */ 946 for (i = 0; i < NB_PF; i++) { 947 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 948 if (!drm_fmt) 949 continue; 950 formats[nb_fmt++] = drm_fmt; 951 952 /* Add the no-alpha related format if any & supported */ 953 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 954 if (!drm_fmt_no_alpha) 955 continue; 956 957 /* Manage hw-specific capabilities */ 958 if (ldev->caps.non_alpha_only_l1 && 959 type != DRM_PLANE_TYPE_PRIMARY) 960 continue; 961 962 formats[nb_fmt++] = drm_fmt_no_alpha; 963 } 964 965 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 966 if (!plane) 967 return NULL; 968 969 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 970 <dc_plane_funcs, formats, nb_fmt, 971 modifiers, type, NULL); 972 if (ret < 0) 973 return NULL; 974 975 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 976 977 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 978 979 return plane; 980 } 981 982 static void ltdc_plane_destroy_all(struct drm_device *ddev) 983 { 984 struct drm_plane *plane, *plane_temp; 985 986 list_for_each_entry_safe(plane, plane_temp, 987 &ddev->mode_config.plane_list, head) 988 drm_plane_cleanup(plane); 989 } 990 991 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 992 { 993 struct ltdc_device *ldev = ddev->dev_private; 994 struct drm_plane *primary, *overlay; 995 unsigned int i; 996 int ret; 997 998 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 999 if (!primary) { 1000 DRM_ERROR("Can not create primary plane\n"); 1001 return -EINVAL; 1002 } 1003 1004 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1005 <dc_crtc_funcs, NULL); 1006 if (ret) { 1007 DRM_ERROR("Can not initialize CRTC\n"); 1008 goto cleanup; 1009 } 1010 1011 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1012 1013 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1014 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1015 1016 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1017 1018 /* Add planes. Note : the first layer is used by primary plane */ 1019 for (i = 1; i < ldev->caps.nb_layers; i++) { 1020 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 1021 if (!overlay) { 1022 ret = -ENOMEM; 1023 DRM_ERROR("Can not create overlay plane %d\n", i); 1024 goto cleanup; 1025 } 1026 } 1027 1028 return 0; 1029 1030 cleanup: 1031 ltdc_plane_destroy_all(ddev); 1032 return ret; 1033 } 1034 1035 /* 1036 * DRM_ENCODER 1037 */ 1038 1039 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1040 .destroy = drm_encoder_cleanup, 1041 }; 1042 1043 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1044 { 1045 struct drm_encoder *encoder; 1046 int ret; 1047 1048 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1049 if (!encoder) 1050 return -ENOMEM; 1051 1052 encoder->possible_crtcs = CRTC_MASK; 1053 encoder->possible_clones = 0; /* No cloning support */ 1054 1055 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1056 DRM_MODE_ENCODER_DPI, NULL); 1057 1058 ret = drm_bridge_attach(encoder, bridge, NULL); 1059 if (ret) { 1060 drm_encoder_cleanup(encoder); 1061 return -EINVAL; 1062 } 1063 1064 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1065 1066 return 0; 1067 } 1068 1069 static int ltdc_get_caps(struct drm_device *ddev) 1070 { 1071 struct ltdc_device *ldev = ddev->dev_private; 1072 u32 bus_width_log2, lcr, gc2r; 1073 1074 /* 1075 * at least 1 layer must be managed & the number of layers 1076 * must not exceed LTDC_MAX_LAYER 1077 */ 1078 lcr = reg_read(ldev->regs, LTDC_LCR); 1079 1080 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1081 1082 /* set data bus width */ 1083 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1084 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1085 ldev->caps.bus_width = 8 << bus_width_log2; 1086 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1087 1088 switch (ldev->caps.hw_version) { 1089 case HWVER_10200: 1090 case HWVER_10300: 1091 ldev->caps.reg_ofs = REG_OFS_NONE; 1092 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1093 /* 1094 * Hw older versions support non-alpha color formats derived 1095 * from native alpha color formats only on the primary layer. 1096 * For instance, RG16 native format without alpha works fine 1097 * on 2nd layer but XR24 (derived color format from AR24) 1098 * does not work on 2nd layer. 1099 */ 1100 ldev->caps.non_alpha_only_l1 = true; 1101 ldev->caps.pad_max_freq_hz = 90000000; 1102 if (ldev->caps.hw_version == HWVER_10200) 1103 ldev->caps.pad_max_freq_hz = 65000000; 1104 break; 1105 case HWVER_20101: 1106 ldev->caps.reg_ofs = REG_OFS_4; 1107 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1108 ldev->caps.non_alpha_only_l1 = false; 1109 ldev->caps.pad_max_freq_hz = 150000000; 1110 break; 1111 default: 1112 return -ENODEV; 1113 } 1114 1115 return 0; 1116 } 1117 1118 void ltdc_suspend(struct drm_device *ddev) 1119 { 1120 struct ltdc_device *ldev = ddev->dev_private; 1121 1122 DRM_DEBUG_DRIVER("\n"); 1123 clk_disable_unprepare(ldev->pixel_clk); 1124 } 1125 1126 int ltdc_resume(struct drm_device *ddev) 1127 { 1128 struct ltdc_device *ldev = ddev->dev_private; 1129 int ret; 1130 1131 DRM_DEBUG_DRIVER("\n"); 1132 1133 ret = clk_prepare_enable(ldev->pixel_clk); 1134 if (ret) { 1135 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1136 return ret; 1137 } 1138 1139 return 0; 1140 } 1141 1142 int ltdc_load(struct drm_device *ddev) 1143 { 1144 struct platform_device *pdev = to_platform_device(ddev->dev); 1145 struct ltdc_device *ldev = ddev->dev_private; 1146 struct device *dev = ddev->dev; 1147 struct device_node *np = dev->of_node; 1148 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1149 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1150 struct drm_crtc *crtc; 1151 struct reset_control *rstc; 1152 struct resource *res; 1153 int irq, ret, i, endpoint_not_ready = -ENODEV; 1154 1155 DRM_DEBUG_DRIVER("\n"); 1156 1157 /* Get endpoints if any */ 1158 for (i = 0; i < MAX_ENDPOINTS; i++) { 1159 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1160 &bridge[i]); 1161 1162 /* 1163 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1164 * else if at least one endpoint is ready, continue probing. 1165 */ 1166 if (ret == -EPROBE_DEFER) 1167 return ret; 1168 else if (!ret) 1169 endpoint_not_ready = 0; 1170 } 1171 1172 if (endpoint_not_ready) 1173 return endpoint_not_ready; 1174 1175 rstc = devm_reset_control_get_exclusive(dev, NULL); 1176 1177 mutex_init(&ldev->err_lock); 1178 1179 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1180 if (IS_ERR(ldev->pixel_clk)) { 1181 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1182 DRM_ERROR("Unable to get lcd clock\n"); 1183 return PTR_ERR(ldev->pixel_clk); 1184 } 1185 1186 if (clk_prepare_enable(ldev->pixel_clk)) { 1187 DRM_ERROR("Unable to prepare pixel clock\n"); 1188 return -ENODEV; 1189 } 1190 1191 if (!IS_ERR(rstc)) { 1192 reset_control_assert(rstc); 1193 usleep_range(10, 20); 1194 reset_control_deassert(rstc); 1195 } 1196 1197 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1198 ldev->regs = devm_ioremap_resource(dev, res); 1199 if (IS_ERR(ldev->regs)) { 1200 DRM_ERROR("Unable to get ltdc registers\n"); 1201 ret = PTR_ERR(ldev->regs); 1202 goto err; 1203 } 1204 1205 /* Disable interrupts */ 1206 reg_clear(ldev->regs, LTDC_IER, 1207 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1208 1209 for (i = 0; i < MAX_IRQ; i++) { 1210 irq = platform_get_irq(pdev, i); 1211 if (irq == -EPROBE_DEFER) 1212 goto err; 1213 1214 if (irq < 0) 1215 continue; 1216 1217 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1218 ltdc_irq_thread, IRQF_ONESHOT, 1219 dev_name(dev), ddev); 1220 if (ret) { 1221 DRM_ERROR("Failed to register LTDC interrupt\n"); 1222 goto err; 1223 } 1224 } 1225 1226 1227 ret = ltdc_get_caps(ddev); 1228 if (ret) { 1229 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1230 ldev->caps.hw_version); 1231 goto err; 1232 } 1233 1234 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1235 1236 /* Add endpoints panels or bridges if any */ 1237 for (i = 0; i < MAX_ENDPOINTS; i++) { 1238 if (panel[i]) { 1239 bridge[i] = drm_panel_bridge_add(panel[i], 1240 DRM_MODE_CONNECTOR_DPI); 1241 if (IS_ERR(bridge[i])) { 1242 DRM_ERROR("panel-bridge endpoint %d\n", i); 1243 ret = PTR_ERR(bridge[i]); 1244 goto err; 1245 } 1246 } 1247 1248 if (bridge[i]) { 1249 ret = ltdc_encoder_init(ddev, bridge[i]); 1250 if (ret) { 1251 DRM_ERROR("init encoder endpoint %d\n", i); 1252 goto err; 1253 } 1254 } 1255 } 1256 1257 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1258 if (!crtc) { 1259 DRM_ERROR("Failed to allocate crtc\n"); 1260 ret = -ENOMEM; 1261 goto err; 1262 } 1263 1264 ddev->mode_config.allow_fb_modifiers = true; 1265 1266 ret = ltdc_crtc_init(ddev, crtc); 1267 if (ret) { 1268 DRM_ERROR("Failed to init crtc\n"); 1269 goto err; 1270 } 1271 1272 ret = drm_vblank_init(ddev, NB_CRTC); 1273 if (ret) { 1274 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1275 goto err; 1276 } 1277 1278 /* Allow usage of vblank without having to call drm_irq_install */ 1279 ddev->irq_enabled = 1; 1280 1281 clk_disable_unprepare(ldev->pixel_clk); 1282 1283 pm_runtime_enable(ddev->dev); 1284 1285 return 0; 1286 err: 1287 for (i = 0; i < MAX_ENDPOINTS; i++) 1288 drm_panel_bridge_remove(bridge[i]); 1289 1290 clk_disable_unprepare(ldev->pixel_clk); 1291 1292 return ret; 1293 } 1294 1295 void ltdc_unload(struct drm_device *ddev) 1296 { 1297 int i; 1298 1299 DRM_DEBUG_DRIVER("\n"); 1300 1301 for (i = 0; i < MAX_ENDPOINTS; i++) 1302 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1303 1304 pm_runtime_disable(ddev->dev); 1305 } 1306 1307 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1308 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1309 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1310 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1311 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1312 MODULE_LICENSE("GPL v2"); 1313