1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/platform_device.h> 19 #include <linux/reset.h> 20 21 #include <drm/drm_atomic.h> 22 #include <drm/drm_atomic_helper.h> 23 #include <drm/drm_bridge.h> 24 #include <drm/drm_device.h> 25 #include <drm/drm_fb_cma_helper.h> 26 #include <drm/drm_fourcc.h> 27 #include <drm/drm_gem_cma_helper.h> 28 #include <drm/drm_of.h> 29 #include <drm/drm_plane_helper.h> 30 #include <drm/drm_probe_helper.h> 31 #include <drm/drm_vblank.h> 32 33 #include <video/videomode.h> 34 35 #include "ltdc.h" 36 37 #define NB_CRTC 1 38 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 39 40 #define MAX_IRQ 4 41 42 #define MAX_ENDPOINTS 2 43 44 #define HWVER_10200 0x010200 45 #define HWVER_10300 0x010300 46 #define HWVER_20101 0x020101 47 48 /* 49 * The address of some registers depends on the HW version: such registers have 50 * an extra offset specified with reg_ofs. 51 */ 52 #define REG_OFS_NONE 0 53 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 54 #define REG_OFS (ldev->caps.reg_ofs) 55 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 56 57 /* Global register offsets */ 58 #define LTDC_IDR 0x0000 /* IDentification */ 59 #define LTDC_LCR 0x0004 /* Layer Count */ 60 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 61 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 62 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 63 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 64 #define LTDC_GCR 0x0018 /* Global Control */ 65 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 66 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 67 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 68 #define LTDC_GACR 0x0028 /* GAmma Correction */ 69 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 70 #define LTDC_IER 0x0034 /* Interrupt Enable */ 71 #define LTDC_ISR 0x0038 /* Interrupt Status */ 72 #define LTDC_ICR 0x003C /* Interrupt Clear */ 73 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 74 #define LTDC_CPSR 0x0044 /* Current Position Status */ 75 #define LTDC_CDSR 0x0048 /* Current Display Status */ 76 77 /* Layer register offsets */ 78 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 79 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 80 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 81 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 82 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 83 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 84 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 85 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 86 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 87 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 88 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 89 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 90 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 91 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 92 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 93 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 94 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 95 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 96 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 97 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 98 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 99 100 /* Bit definitions */ 101 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 102 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 103 104 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 105 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 106 107 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 108 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 109 110 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 111 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 112 113 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 114 #define GCR_DEN BIT(16) /* Dither ENable */ 115 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 116 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 117 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 118 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 119 120 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 121 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 122 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 123 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 124 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 125 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 126 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 127 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 128 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 129 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 130 #define GC1R_TP BIT(25) /* Timing Programmable */ 131 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 132 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 133 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 134 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 135 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 136 137 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 138 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 139 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 140 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 141 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 142 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 143 144 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 145 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 146 147 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 148 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 149 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 150 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 151 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 152 153 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 154 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 155 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 156 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 157 158 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 159 160 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 161 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 162 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 163 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 164 165 #define LXCR_LEN BIT(0) /* Layer ENable */ 166 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 167 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 168 169 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 170 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 171 172 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 173 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 174 175 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 176 177 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 178 179 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 180 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 181 182 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 183 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 184 185 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 186 187 #define CLUT_SIZE 256 188 189 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 190 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 191 #define BF1_CA 0x400 /* Constant Alpha */ 192 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 193 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 194 195 #define NB_PF 8 /* Max nb of HW pixel format */ 196 197 enum ltdc_pix_fmt { 198 PF_NONE, 199 /* RGB formats */ 200 PF_ARGB8888, /* ARGB [32 bits] */ 201 PF_RGBA8888, /* RGBA [32 bits] */ 202 PF_RGB888, /* RGB [24 bits] */ 203 PF_RGB565, /* RGB [16 bits] */ 204 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 205 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 206 /* Indexed formats */ 207 PF_L8, /* Indexed 8 bits [8 bits] */ 208 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 209 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 210 }; 211 212 /* The index gives the encoding of the pixel format for an HW version */ 213 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 214 PF_ARGB8888, /* 0x00 */ 215 PF_RGB888, /* 0x01 */ 216 PF_RGB565, /* 0x02 */ 217 PF_ARGB1555, /* 0x03 */ 218 PF_ARGB4444, /* 0x04 */ 219 PF_L8, /* 0x05 */ 220 PF_AL44, /* 0x06 */ 221 PF_AL88 /* 0x07 */ 222 }; 223 224 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 225 PF_ARGB8888, /* 0x00 */ 226 PF_RGB888, /* 0x01 */ 227 PF_RGB565, /* 0x02 */ 228 PF_RGBA8888, /* 0x03 */ 229 PF_AL44, /* 0x04 */ 230 PF_L8, /* 0x05 */ 231 PF_ARGB1555, /* 0x06 */ 232 PF_ARGB4444 /* 0x07 */ 233 }; 234 235 static const u64 ltdc_format_modifiers[] = { 236 DRM_FORMAT_MOD_LINEAR, 237 DRM_FORMAT_MOD_INVALID 238 }; 239 240 static inline u32 reg_read(void __iomem *base, u32 reg) 241 { 242 return readl_relaxed(base + reg); 243 } 244 245 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 246 { 247 writel_relaxed(val, base + reg); 248 } 249 250 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 251 { 252 reg_write(base, reg, reg_read(base, reg) | mask); 253 } 254 255 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 256 { 257 reg_write(base, reg, reg_read(base, reg) & ~mask); 258 } 259 260 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 261 u32 val) 262 { 263 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 264 } 265 266 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 267 { 268 return (struct ltdc_device *)crtc->dev->dev_private; 269 } 270 271 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 272 { 273 return (struct ltdc_device *)plane->dev->dev_private; 274 } 275 276 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 277 { 278 return (struct ltdc_device *)enc->dev->dev_private; 279 } 280 281 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 282 { 283 enum ltdc_pix_fmt pf; 284 285 switch (drm_fmt) { 286 case DRM_FORMAT_ARGB8888: 287 case DRM_FORMAT_XRGB8888: 288 pf = PF_ARGB8888; 289 break; 290 case DRM_FORMAT_RGBA8888: 291 case DRM_FORMAT_RGBX8888: 292 pf = PF_RGBA8888; 293 break; 294 case DRM_FORMAT_RGB888: 295 pf = PF_RGB888; 296 break; 297 case DRM_FORMAT_RGB565: 298 pf = PF_RGB565; 299 break; 300 case DRM_FORMAT_ARGB1555: 301 case DRM_FORMAT_XRGB1555: 302 pf = PF_ARGB1555; 303 break; 304 case DRM_FORMAT_ARGB4444: 305 case DRM_FORMAT_XRGB4444: 306 pf = PF_ARGB4444; 307 break; 308 case DRM_FORMAT_C8: 309 pf = PF_L8; 310 break; 311 default: 312 pf = PF_NONE; 313 break; 314 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 315 } 316 317 return pf; 318 } 319 320 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 321 { 322 switch (pf) { 323 case PF_ARGB8888: 324 return DRM_FORMAT_ARGB8888; 325 case PF_RGBA8888: 326 return DRM_FORMAT_RGBA8888; 327 case PF_RGB888: 328 return DRM_FORMAT_RGB888; 329 case PF_RGB565: 330 return DRM_FORMAT_RGB565; 331 case PF_ARGB1555: 332 return DRM_FORMAT_ARGB1555; 333 case PF_ARGB4444: 334 return DRM_FORMAT_ARGB4444; 335 case PF_L8: 336 return DRM_FORMAT_C8; 337 case PF_AL44: /* No DRM support */ 338 case PF_AL88: /* No DRM support */ 339 case PF_NONE: 340 default: 341 return 0; 342 } 343 } 344 345 static inline u32 get_pixelformat_without_alpha(u32 drm) 346 { 347 switch (drm) { 348 case DRM_FORMAT_ARGB4444: 349 return DRM_FORMAT_XRGB4444; 350 case DRM_FORMAT_RGBA4444: 351 return DRM_FORMAT_RGBX4444; 352 case DRM_FORMAT_ARGB1555: 353 return DRM_FORMAT_XRGB1555; 354 case DRM_FORMAT_RGBA5551: 355 return DRM_FORMAT_RGBX5551; 356 case DRM_FORMAT_ARGB8888: 357 return DRM_FORMAT_XRGB8888; 358 case DRM_FORMAT_RGBA8888: 359 return DRM_FORMAT_RGBX8888; 360 default: 361 return 0; 362 } 363 } 364 365 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 366 { 367 struct drm_device *ddev = arg; 368 struct ltdc_device *ldev = ddev->dev_private; 369 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 370 371 /* Line IRQ : trigger the vblank event */ 372 if (ldev->irq_status & ISR_LIF) 373 drm_crtc_handle_vblank(crtc); 374 375 /* Save FIFO Underrun & Transfer Error status */ 376 mutex_lock(&ldev->err_lock); 377 if (ldev->irq_status & ISR_FUIF) 378 ldev->error_status |= ISR_FUIF; 379 if (ldev->irq_status & ISR_TERRIF) 380 ldev->error_status |= ISR_TERRIF; 381 mutex_unlock(&ldev->err_lock); 382 383 return IRQ_HANDLED; 384 } 385 386 static irqreturn_t ltdc_irq(int irq, void *arg) 387 { 388 struct drm_device *ddev = arg; 389 struct ltdc_device *ldev = ddev->dev_private; 390 391 /* Read & Clear the interrupt status */ 392 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 393 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 394 395 return IRQ_WAKE_THREAD; 396 } 397 398 /* 399 * DRM_CRTC 400 */ 401 402 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 403 { 404 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 405 struct drm_color_lut *lut; 406 u32 val; 407 int i; 408 409 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 410 return; 411 412 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 413 414 for (i = 0; i < CLUT_SIZE; i++, lut++) { 415 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 416 (lut->blue >> 8) | (i << 24); 417 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 418 } 419 } 420 421 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 422 struct drm_crtc_state *old_state) 423 { 424 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 425 426 DRM_DEBUG_DRIVER("\n"); 427 428 /* Sets the background color value */ 429 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 430 431 /* Enable IRQ */ 432 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 433 434 /* Commit shadow registers = update planes at next vblank */ 435 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 436 437 /* Enable LTDC */ 438 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 439 440 drm_crtc_vblank_on(crtc); 441 } 442 443 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 444 struct drm_crtc_state *old_state) 445 { 446 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 447 448 DRM_DEBUG_DRIVER("\n"); 449 450 drm_crtc_vblank_off(crtc); 451 452 /* disable LTDC */ 453 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 454 455 /* disable IRQ */ 456 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 457 458 /* immediately commit disable of layers before switching off LTDC */ 459 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 460 } 461 462 #define CLK_TOLERANCE_HZ 50 463 464 static enum drm_mode_status 465 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 466 const struct drm_display_mode *mode) 467 { 468 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 469 int target = mode->clock * 1000; 470 int target_min = target - CLK_TOLERANCE_HZ; 471 int target_max = target + CLK_TOLERANCE_HZ; 472 int result; 473 474 result = clk_round_rate(ldev->pixel_clk, target); 475 476 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 477 478 /* Filter modes according to the max frequency supported by the pads */ 479 if (result > ldev->caps.pad_max_freq_hz) 480 return MODE_CLOCK_HIGH; 481 482 /* 483 * Accept all "preferred" modes: 484 * - this is important for panels because panel clock tolerances are 485 * bigger than hdmi ones and there is no reason to not accept them 486 * (the fps may vary a little but it is not a problem). 487 * - the hdmi preferred mode will be accepted too, but userland will 488 * be able to use others hdmi "valid" modes if necessary. 489 */ 490 if (mode->type & DRM_MODE_TYPE_PREFERRED) 491 return MODE_OK; 492 493 /* 494 * Filter modes according to the clock value, particularly useful for 495 * hdmi modes that require precise pixel clocks. 496 */ 497 if (result < target_min || result > target_max) 498 return MODE_CLOCK_RANGE; 499 500 return MODE_OK; 501 } 502 503 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 504 const struct drm_display_mode *mode, 505 struct drm_display_mode *adjusted_mode) 506 { 507 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 508 int rate = mode->clock * 1000; 509 510 /* 511 * TODO clk_round_rate() does not work yet. When ready, it can 512 * be used instead of clk_set_rate() then clk_get_rate(). 513 */ 514 515 clk_disable(ldev->pixel_clk); 516 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 517 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 518 return false; 519 } 520 clk_enable(ldev->pixel_clk); 521 522 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 523 524 return true; 525 } 526 527 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 528 { 529 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 530 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 531 struct videomode vm; 532 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 533 u32 total_width, total_height; 534 u32 val; 535 536 drm_display_mode_to_videomode(mode, &vm); 537 538 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 539 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 540 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 541 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 542 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 543 544 /* Convert video timings to ltdc timings */ 545 hsync = vm.hsync_len - 1; 546 vsync = vm.vsync_len - 1; 547 accum_hbp = hsync + vm.hback_porch; 548 accum_vbp = vsync + vm.vback_porch; 549 accum_act_w = accum_hbp + vm.hactive; 550 accum_act_h = accum_vbp + vm.vactive; 551 total_width = accum_act_w + vm.hfront_porch; 552 total_height = accum_act_h + vm.vfront_porch; 553 554 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 555 val = 0; 556 557 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 558 val |= GCR_HSPOL; 559 560 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 561 val |= GCR_VSPOL; 562 563 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 564 val |= GCR_DEPOL; 565 566 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 567 val |= GCR_PCPOL; 568 569 reg_update_bits(ldev->regs, LTDC_GCR, 570 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 571 572 /* Set Synchronization size */ 573 val = (hsync << 16) | vsync; 574 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 575 576 /* Set Accumulated Back porch */ 577 val = (accum_hbp << 16) | accum_vbp; 578 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 579 580 /* Set Accumulated Active Width */ 581 val = (accum_act_w << 16) | accum_act_h; 582 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 583 584 /* Set total width & height */ 585 val = (total_width << 16) | total_height; 586 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 587 588 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 589 } 590 591 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 592 struct drm_crtc_state *old_crtc_state) 593 { 594 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 595 struct drm_pending_vblank_event *event = crtc->state->event; 596 597 DRM_DEBUG_ATOMIC("\n"); 598 599 ltdc_crtc_update_clut(crtc); 600 601 /* Commit shadow registers = update planes at next vblank */ 602 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 603 604 if (event) { 605 crtc->state->event = NULL; 606 607 spin_lock_irq(&crtc->dev->event_lock); 608 if (drm_crtc_vblank_get(crtc) == 0) 609 drm_crtc_arm_vblank_event(crtc, event); 610 else 611 drm_crtc_send_vblank_event(crtc, event); 612 spin_unlock_irq(&crtc->dev->event_lock); 613 } 614 } 615 616 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 617 .mode_valid = ltdc_crtc_mode_valid, 618 .mode_fixup = ltdc_crtc_mode_fixup, 619 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 620 .atomic_flush = ltdc_crtc_atomic_flush, 621 .atomic_enable = ltdc_crtc_atomic_enable, 622 .atomic_disable = ltdc_crtc_atomic_disable, 623 }; 624 625 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 626 { 627 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 628 629 DRM_DEBUG_DRIVER("\n"); 630 reg_set(ldev->regs, LTDC_IER, IER_LIE); 631 632 return 0; 633 } 634 635 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 636 { 637 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 638 639 DRM_DEBUG_DRIVER("\n"); 640 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 641 } 642 643 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 644 bool in_vblank_irq, int *vpos, int *hpos, 645 ktime_t *stime, ktime_t *etime, 646 const struct drm_display_mode *mode) 647 { 648 struct ltdc_device *ldev = ddev->dev_private; 649 int line, vactive_start, vactive_end, vtotal; 650 651 if (stime) 652 *stime = ktime_get(); 653 654 /* The active area starts after vsync + front porch and ends 655 * at vsync + front porc + display size. 656 * The total height also include back porch. 657 * We have 3 possible cases to handle: 658 * - line < vactive_start: vpos = line - vactive_start and will be 659 * negative 660 * - vactive_start < line < vactive_end: vpos = line - vactive_start 661 * and will be positive 662 * - line > vactive_end: vpos = line - vtotal - vactive_start 663 * and will negative 664 * 665 * Computation for the two first cases are identical so we can 666 * simplify the code and only test if line > vactive_end 667 */ 668 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 669 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 670 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 671 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 672 673 if (line > vactive_end) 674 *vpos = line - vtotal - vactive_start; 675 else 676 *vpos = line - vactive_start; 677 678 *hpos = 0; 679 680 if (etime) 681 *etime = ktime_get(); 682 683 return true; 684 } 685 686 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 687 .destroy = drm_crtc_cleanup, 688 .set_config = drm_atomic_helper_set_config, 689 .page_flip = drm_atomic_helper_page_flip, 690 .reset = drm_atomic_helper_crtc_reset, 691 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 692 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 693 .enable_vblank = ltdc_crtc_enable_vblank, 694 .disable_vblank = ltdc_crtc_disable_vblank, 695 .gamma_set = drm_atomic_helper_legacy_gamma_set, 696 }; 697 698 /* 699 * DRM_PLANE 700 */ 701 702 static int ltdc_plane_atomic_check(struct drm_plane *plane, 703 struct drm_plane_state *state) 704 { 705 struct drm_framebuffer *fb = state->fb; 706 u32 src_w, src_h; 707 708 DRM_DEBUG_DRIVER("\n"); 709 710 if (!fb) 711 return 0; 712 713 /* convert src_ from 16:16 format */ 714 src_w = state->src_w >> 16; 715 src_h = state->src_h >> 16; 716 717 /* Reject scaling */ 718 if (src_w != state->crtc_w || src_h != state->crtc_h) { 719 DRM_ERROR("Scaling is not supported"); 720 return -EINVAL; 721 } 722 723 return 0; 724 } 725 726 static void ltdc_plane_atomic_update(struct drm_plane *plane, 727 struct drm_plane_state *oldstate) 728 { 729 struct ltdc_device *ldev = plane_to_ltdc(plane); 730 struct drm_plane_state *state = plane->state; 731 struct drm_framebuffer *fb = state->fb; 732 u32 lofs = plane->index * LAY_OFS; 733 u32 x0 = state->crtc_x; 734 u32 x1 = state->crtc_x + state->crtc_w - 1; 735 u32 y0 = state->crtc_y; 736 u32 y1 = state->crtc_y + state->crtc_h - 1; 737 u32 src_x, src_y, src_w, src_h; 738 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 739 enum ltdc_pix_fmt pf; 740 741 if (!state->crtc || !fb) { 742 DRM_DEBUG_DRIVER("fb or crtc NULL"); 743 return; 744 } 745 746 /* convert src_ from 16:16 format */ 747 src_x = state->src_x >> 16; 748 src_y = state->src_y >> 16; 749 src_w = state->src_w >> 16; 750 src_h = state->src_h >> 16; 751 752 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 753 plane->base.id, fb->base.id, 754 src_w, src_h, src_x, src_y, 755 state->crtc_w, state->crtc_h, 756 state->crtc_x, state->crtc_y); 757 758 bpcr = reg_read(ldev->regs, LTDC_BPCR); 759 ahbp = (bpcr & BPCR_AHBP) >> 16; 760 avbp = bpcr & BPCR_AVBP; 761 762 /* Configures the horizontal start and stop position */ 763 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 764 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 765 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 766 767 /* Configures the vertical start and stop position */ 768 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 769 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 770 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 771 772 /* Specifies the pixel format */ 773 pf = to_ltdc_pixelformat(fb->format->format); 774 for (val = 0; val < NB_PF; val++) 775 if (ldev->caps.pix_fmt_hw[val] == pf) 776 break; 777 778 if (val == NB_PF) { 779 DRM_ERROR("Pixel format %.4s not supported\n", 780 (char *)&fb->format->format); 781 val = 0; /* set by default ARGB 32 bits */ 782 } 783 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 784 785 /* Configures the color frame buffer pitch in bytes & line length */ 786 pitch_in_bytes = fb->pitches[0]; 787 line_length = fb->format->cpp[0] * 788 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 789 val = ((pitch_in_bytes << 16) | line_length); 790 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 791 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 792 793 /* Specifies the constant alpha value */ 794 val = CONSTA_MAX; 795 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 796 797 /* Specifies the blending factors */ 798 val = BF1_PAXCA | BF2_1PAXCA; 799 if (!fb->format->has_alpha) 800 val = BF1_CA | BF2_1CA; 801 802 /* Manage hw-specific capabilities */ 803 if (ldev->caps.non_alpha_only_l1 && 804 plane->type != DRM_PLANE_TYPE_PRIMARY) 805 val = BF1_PAXCA | BF2_1PAXCA; 806 807 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 808 LXBFCR_BF2 | LXBFCR_BF1, val); 809 810 /* Configures the frame buffer line number */ 811 val = y1 - y0 + 1; 812 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 813 814 /* Sets the FB address */ 815 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 816 817 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 818 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 819 820 /* Enable layer and CLUT if needed */ 821 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 822 val |= LXCR_LEN; 823 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 824 LXCR_LEN | LXCR_CLUTEN, val); 825 826 ldev->plane_fpsi[plane->index].counter++; 827 828 mutex_lock(&ldev->err_lock); 829 if (ldev->error_status & ISR_FUIF) { 830 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 831 ldev->error_status &= ~ISR_FUIF; 832 } 833 if (ldev->error_status & ISR_TERRIF) { 834 DRM_WARN("ltdc transfer error\n"); 835 ldev->error_status &= ~ISR_TERRIF; 836 } 837 mutex_unlock(&ldev->err_lock); 838 } 839 840 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 841 struct drm_plane_state *oldstate) 842 { 843 struct ltdc_device *ldev = plane_to_ltdc(plane); 844 u32 lofs = plane->index * LAY_OFS; 845 846 /* disable layer */ 847 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 848 849 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 850 oldstate->crtc->base.id, plane->base.id); 851 } 852 853 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 854 const struct drm_plane_state *state) 855 { 856 struct drm_plane *plane = state->plane; 857 struct ltdc_device *ldev = plane_to_ltdc(plane); 858 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 859 int ms_since_last; 860 ktime_t now; 861 862 now = ktime_get(); 863 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 864 865 drm_printf(p, "\tuser_updates=%dfps\n", 866 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 867 868 fpsi->last_timestamp = now; 869 fpsi->counter = 0; 870 } 871 872 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 873 u32 format, 874 u64 modifier) 875 { 876 if (modifier == DRM_FORMAT_MOD_LINEAR) 877 return true; 878 879 return false; 880 } 881 882 static const struct drm_plane_funcs ltdc_plane_funcs = { 883 .update_plane = drm_atomic_helper_update_plane, 884 .disable_plane = drm_atomic_helper_disable_plane, 885 .destroy = drm_plane_cleanup, 886 .reset = drm_atomic_helper_plane_reset, 887 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 888 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 889 .atomic_print_state = ltdc_plane_atomic_print_state, 890 .format_mod_supported = ltdc_plane_format_mod_supported, 891 }; 892 893 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 894 .atomic_check = ltdc_plane_atomic_check, 895 .atomic_update = ltdc_plane_atomic_update, 896 .atomic_disable = ltdc_plane_atomic_disable, 897 }; 898 899 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 900 enum drm_plane_type type) 901 { 902 unsigned long possible_crtcs = CRTC_MASK; 903 struct ltdc_device *ldev = ddev->dev_private; 904 struct device *dev = ddev->dev; 905 struct drm_plane *plane; 906 unsigned int i, nb_fmt = 0; 907 u32 formats[NB_PF * 2]; 908 u32 drm_fmt, drm_fmt_no_alpha; 909 const u64 *modifiers = ltdc_format_modifiers; 910 int ret; 911 912 /* Get supported pixel formats */ 913 for (i = 0; i < NB_PF; i++) { 914 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 915 if (!drm_fmt) 916 continue; 917 formats[nb_fmt++] = drm_fmt; 918 919 /* Add the no-alpha related format if any & supported */ 920 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 921 if (!drm_fmt_no_alpha) 922 continue; 923 924 /* Manage hw-specific capabilities */ 925 if (ldev->caps.non_alpha_only_l1 && 926 type != DRM_PLANE_TYPE_PRIMARY) 927 continue; 928 929 formats[nb_fmt++] = drm_fmt_no_alpha; 930 } 931 932 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 933 if (!plane) 934 return NULL; 935 936 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 937 <dc_plane_funcs, formats, nb_fmt, 938 modifiers, type, NULL); 939 if (ret < 0) 940 return NULL; 941 942 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 943 944 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 945 946 return plane; 947 } 948 949 static void ltdc_plane_destroy_all(struct drm_device *ddev) 950 { 951 struct drm_plane *plane, *plane_temp; 952 953 list_for_each_entry_safe(plane, plane_temp, 954 &ddev->mode_config.plane_list, head) 955 drm_plane_cleanup(plane); 956 } 957 958 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 959 { 960 struct ltdc_device *ldev = ddev->dev_private; 961 struct drm_plane *primary, *overlay; 962 unsigned int i; 963 int ret; 964 965 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 966 if (!primary) { 967 DRM_ERROR("Can not create primary plane\n"); 968 return -EINVAL; 969 } 970 971 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 972 <dc_crtc_funcs, NULL); 973 if (ret) { 974 DRM_ERROR("Can not initialize CRTC\n"); 975 goto cleanup; 976 } 977 978 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 979 980 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 981 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 982 983 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 984 985 /* Add planes. Note : the first layer is used by primary plane */ 986 for (i = 1; i < ldev->caps.nb_layers; i++) { 987 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 988 if (!overlay) { 989 ret = -ENOMEM; 990 DRM_ERROR("Can not create overlay plane %d\n", i); 991 goto cleanup; 992 } 993 } 994 995 return 0; 996 997 cleanup: 998 ltdc_plane_destroy_all(ddev); 999 return ret; 1000 } 1001 1002 /* 1003 * DRM_ENCODER 1004 */ 1005 1006 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1007 .destroy = drm_encoder_cleanup, 1008 }; 1009 1010 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1011 { 1012 struct drm_encoder *encoder; 1013 int ret; 1014 1015 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1016 if (!encoder) 1017 return -ENOMEM; 1018 1019 encoder->possible_crtcs = CRTC_MASK; 1020 encoder->possible_clones = 0; /* No cloning support */ 1021 1022 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1023 DRM_MODE_ENCODER_DPI, NULL); 1024 1025 ret = drm_bridge_attach(encoder, bridge, NULL); 1026 if (ret) { 1027 drm_encoder_cleanup(encoder); 1028 return -EINVAL; 1029 } 1030 1031 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1032 1033 return 0; 1034 } 1035 1036 static int ltdc_get_caps(struct drm_device *ddev) 1037 { 1038 struct ltdc_device *ldev = ddev->dev_private; 1039 u32 bus_width_log2, lcr, gc2r; 1040 1041 /* 1042 * at least 1 layer must be managed & the number of layers 1043 * must not exceed LTDC_MAX_LAYER 1044 */ 1045 lcr = reg_read(ldev->regs, LTDC_LCR); 1046 1047 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1048 1049 /* set data bus width */ 1050 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1051 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1052 ldev->caps.bus_width = 8 << bus_width_log2; 1053 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1054 1055 switch (ldev->caps.hw_version) { 1056 case HWVER_10200: 1057 case HWVER_10300: 1058 ldev->caps.reg_ofs = REG_OFS_NONE; 1059 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1060 /* 1061 * Hw older versions support non-alpha color formats derived 1062 * from native alpha color formats only on the primary layer. 1063 * For instance, RG16 native format without alpha works fine 1064 * on 2nd layer but XR24 (derived color format from AR24) 1065 * does not work on 2nd layer. 1066 */ 1067 ldev->caps.non_alpha_only_l1 = true; 1068 ldev->caps.pad_max_freq_hz = 90000000; 1069 if (ldev->caps.hw_version == HWVER_10200) 1070 ldev->caps.pad_max_freq_hz = 65000000; 1071 break; 1072 case HWVER_20101: 1073 ldev->caps.reg_ofs = REG_OFS_4; 1074 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1075 ldev->caps.non_alpha_only_l1 = false; 1076 ldev->caps.pad_max_freq_hz = 150000000; 1077 break; 1078 default: 1079 return -ENODEV; 1080 } 1081 1082 return 0; 1083 } 1084 1085 void ltdc_suspend(struct drm_device *ddev) 1086 { 1087 struct ltdc_device *ldev = ddev->dev_private; 1088 1089 DRM_DEBUG_DRIVER("\n"); 1090 clk_disable_unprepare(ldev->pixel_clk); 1091 } 1092 1093 int ltdc_resume(struct drm_device *ddev) 1094 { 1095 struct ltdc_device *ldev = ddev->dev_private; 1096 int ret; 1097 1098 DRM_DEBUG_DRIVER("\n"); 1099 1100 ret = clk_prepare_enable(ldev->pixel_clk); 1101 if (ret) { 1102 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1103 return ret; 1104 } 1105 1106 return 0; 1107 } 1108 1109 int ltdc_load(struct drm_device *ddev) 1110 { 1111 struct platform_device *pdev = to_platform_device(ddev->dev); 1112 struct ltdc_device *ldev = ddev->dev_private; 1113 struct device *dev = ddev->dev; 1114 struct device_node *np = dev->of_node; 1115 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1116 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1117 struct drm_crtc *crtc; 1118 struct reset_control *rstc; 1119 struct resource *res; 1120 int irq, ret, i, endpoint_not_ready = -ENODEV; 1121 1122 DRM_DEBUG_DRIVER("\n"); 1123 1124 /* Get endpoints if any */ 1125 for (i = 0; i < MAX_ENDPOINTS; i++) { 1126 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1127 &bridge[i]); 1128 1129 /* 1130 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1131 * else if at least one endpoint is ready, continue probing. 1132 */ 1133 if (ret == -EPROBE_DEFER) 1134 return ret; 1135 else if (!ret) 1136 endpoint_not_ready = 0; 1137 } 1138 1139 if (endpoint_not_ready) 1140 return endpoint_not_ready; 1141 1142 rstc = devm_reset_control_get_exclusive(dev, NULL); 1143 1144 mutex_init(&ldev->err_lock); 1145 1146 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1147 if (IS_ERR(ldev->pixel_clk)) { 1148 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1149 DRM_ERROR("Unable to get lcd clock\n"); 1150 return PTR_ERR(ldev->pixel_clk); 1151 } 1152 1153 if (clk_prepare_enable(ldev->pixel_clk)) { 1154 DRM_ERROR("Unable to prepare pixel clock\n"); 1155 return -ENODEV; 1156 } 1157 1158 if (!IS_ERR(rstc)) { 1159 reset_control_assert(rstc); 1160 usleep_range(10, 20); 1161 reset_control_deassert(rstc); 1162 } 1163 1164 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1165 ldev->regs = devm_ioremap_resource(dev, res); 1166 if (IS_ERR(ldev->regs)) { 1167 DRM_ERROR("Unable to get ltdc registers\n"); 1168 ret = PTR_ERR(ldev->regs); 1169 goto err; 1170 } 1171 1172 /* Disable interrupts */ 1173 reg_clear(ldev->regs, LTDC_IER, 1174 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1175 1176 for (i = 0; i < MAX_IRQ; i++) { 1177 irq = platform_get_irq(pdev, i); 1178 if (irq == -EPROBE_DEFER) 1179 goto err; 1180 1181 if (irq < 0) 1182 continue; 1183 1184 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1185 ltdc_irq_thread, IRQF_ONESHOT, 1186 dev_name(dev), ddev); 1187 if (ret) { 1188 DRM_ERROR("Failed to register LTDC interrupt\n"); 1189 goto err; 1190 } 1191 } 1192 1193 1194 ret = ltdc_get_caps(ddev); 1195 if (ret) { 1196 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1197 ldev->caps.hw_version); 1198 goto err; 1199 } 1200 1201 DRM_INFO("ltdc hw version 0x%08x - ready\n", ldev->caps.hw_version); 1202 1203 /* Add endpoints panels or bridges if any */ 1204 for (i = 0; i < MAX_ENDPOINTS; i++) { 1205 if (panel[i]) { 1206 bridge[i] = drm_panel_bridge_add(panel[i], 1207 DRM_MODE_CONNECTOR_DPI); 1208 if (IS_ERR(bridge[i])) { 1209 DRM_ERROR("panel-bridge endpoint %d\n", i); 1210 ret = PTR_ERR(bridge[i]); 1211 goto err; 1212 } 1213 } 1214 1215 if (bridge[i]) { 1216 ret = ltdc_encoder_init(ddev, bridge[i]); 1217 if (ret) { 1218 DRM_ERROR("init encoder endpoint %d\n", i); 1219 goto err; 1220 } 1221 } 1222 } 1223 1224 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1225 if (!crtc) { 1226 DRM_ERROR("Failed to allocate crtc\n"); 1227 ret = -ENOMEM; 1228 goto err; 1229 } 1230 1231 ddev->mode_config.allow_fb_modifiers = true; 1232 1233 ret = ltdc_crtc_init(ddev, crtc); 1234 if (ret) { 1235 DRM_ERROR("Failed to init crtc\n"); 1236 goto err; 1237 } 1238 1239 ret = drm_vblank_init(ddev, NB_CRTC); 1240 if (ret) { 1241 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1242 goto err; 1243 } 1244 1245 /* Allow usage of vblank without having to call drm_irq_install */ 1246 ddev->irq_enabled = 1; 1247 1248 return 0; 1249 1250 err: 1251 for (i = 0; i < MAX_ENDPOINTS; i++) 1252 drm_panel_bridge_remove(bridge[i]); 1253 1254 clk_disable_unprepare(ldev->pixel_clk); 1255 1256 return ret; 1257 } 1258 1259 void ltdc_unload(struct drm_device *ddev) 1260 { 1261 struct ltdc_device *ldev = ddev->dev_private; 1262 int i; 1263 1264 DRM_DEBUG_DRIVER("\n"); 1265 1266 for (i = 0; i < MAX_ENDPOINTS; i++) 1267 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1268 1269 clk_disable_unprepare(ldev->pixel_clk); 1270 } 1271 1272 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1273 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1274 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1275 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1276 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1277 MODULE_LICENSE("GPL v2"); 1278