1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/pinctrl/consumer.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/reset.h> 22 23 #include <drm/drm_atomic.h> 24 #include <drm/drm_atomic_helper.h> 25 #include <drm/drm_bridge.h> 26 #include <drm/drm_device.h> 27 #include <drm/drm_fb_cma_helper.h> 28 #include <drm/drm_fourcc.h> 29 #include <drm/drm_gem_cma_helper.h> 30 #include <drm/drm_gem_framebuffer_helper.h> 31 #include <drm/drm_of.h> 32 #include <drm/drm_plane_helper.h> 33 #include <drm/drm_probe_helper.h> 34 #include <drm/drm_vblank.h> 35 36 #include <video/videomode.h> 37 38 #include "ltdc.h" 39 40 #define NB_CRTC 1 41 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 42 43 #define MAX_IRQ 4 44 45 #define MAX_ENDPOINTS 2 46 47 #define HWVER_10200 0x010200 48 #define HWVER_10300 0x010300 49 #define HWVER_20101 0x020101 50 51 /* 52 * The address of some registers depends on the HW version: such registers have 53 * an extra offset specified with reg_ofs. 54 */ 55 #define REG_OFS_NONE 0 56 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 57 #define REG_OFS (ldev->caps.reg_ofs) 58 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 59 60 /* Global register offsets */ 61 #define LTDC_IDR 0x0000 /* IDentification */ 62 #define LTDC_LCR 0x0004 /* Layer Count */ 63 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 64 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 65 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 66 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 67 #define LTDC_GCR 0x0018 /* Global Control */ 68 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 69 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 70 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 71 #define LTDC_GACR 0x0028 /* GAmma Correction */ 72 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 73 #define LTDC_IER 0x0034 /* Interrupt Enable */ 74 #define LTDC_ISR 0x0038 /* Interrupt Status */ 75 #define LTDC_ICR 0x003C /* Interrupt Clear */ 76 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 77 #define LTDC_CPSR 0x0044 /* Current Position Status */ 78 #define LTDC_CDSR 0x0048 /* Current Display Status */ 79 80 /* Layer register offsets */ 81 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 82 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 83 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 84 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 85 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 86 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 87 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 88 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 89 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 90 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 91 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 92 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 93 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 94 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 95 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 96 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 97 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 98 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 99 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 100 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 101 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 102 103 /* Bit definitions */ 104 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 105 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 106 107 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 108 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 109 110 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 111 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 112 113 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 114 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 115 116 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 117 #define GCR_DEN BIT(16) /* Dither ENable */ 118 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 119 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 120 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 121 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 122 123 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 124 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 125 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 126 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 127 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 128 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 129 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 130 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 131 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 132 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 133 #define GC1R_TP BIT(25) /* Timing Programmable */ 134 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 135 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 136 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 137 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 138 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 139 140 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 141 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 142 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 143 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 144 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 145 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 146 147 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 148 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 149 150 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 151 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 152 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 153 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 154 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 155 156 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 157 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 158 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 159 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 160 161 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 162 163 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 164 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 165 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 166 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 167 168 #define LXCR_LEN BIT(0) /* Layer ENable */ 169 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 170 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 171 172 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 173 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 174 175 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 176 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 177 178 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 179 180 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 181 182 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 183 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 184 185 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 186 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 187 188 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 189 190 #define CLUT_SIZE 256 191 192 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 193 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 194 #define BF1_CA 0x400 /* Constant Alpha */ 195 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 196 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 197 198 #define NB_PF 8 /* Max nb of HW pixel format */ 199 200 enum ltdc_pix_fmt { 201 PF_NONE, 202 /* RGB formats */ 203 PF_ARGB8888, /* ARGB [32 bits] */ 204 PF_RGBA8888, /* RGBA [32 bits] */ 205 PF_RGB888, /* RGB [24 bits] */ 206 PF_RGB565, /* RGB [16 bits] */ 207 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 208 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 209 /* Indexed formats */ 210 PF_L8, /* Indexed 8 bits [8 bits] */ 211 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 212 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 213 }; 214 215 /* The index gives the encoding of the pixel format for an HW version */ 216 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 217 PF_ARGB8888, /* 0x00 */ 218 PF_RGB888, /* 0x01 */ 219 PF_RGB565, /* 0x02 */ 220 PF_ARGB1555, /* 0x03 */ 221 PF_ARGB4444, /* 0x04 */ 222 PF_L8, /* 0x05 */ 223 PF_AL44, /* 0x06 */ 224 PF_AL88 /* 0x07 */ 225 }; 226 227 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 228 PF_ARGB8888, /* 0x00 */ 229 PF_RGB888, /* 0x01 */ 230 PF_RGB565, /* 0x02 */ 231 PF_RGBA8888, /* 0x03 */ 232 PF_AL44, /* 0x04 */ 233 PF_L8, /* 0x05 */ 234 PF_ARGB1555, /* 0x06 */ 235 PF_ARGB4444 /* 0x07 */ 236 }; 237 238 static const u64 ltdc_format_modifiers[] = { 239 DRM_FORMAT_MOD_LINEAR, 240 DRM_FORMAT_MOD_INVALID 241 }; 242 243 static inline u32 reg_read(void __iomem *base, u32 reg) 244 { 245 return readl_relaxed(base + reg); 246 } 247 248 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 249 { 250 writel_relaxed(val, base + reg); 251 } 252 253 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 254 { 255 reg_write(base, reg, reg_read(base, reg) | mask); 256 } 257 258 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 259 { 260 reg_write(base, reg, reg_read(base, reg) & ~mask); 261 } 262 263 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 264 u32 val) 265 { 266 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 267 } 268 269 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 270 { 271 return (struct ltdc_device *)crtc->dev->dev_private; 272 } 273 274 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 275 { 276 return (struct ltdc_device *)plane->dev->dev_private; 277 } 278 279 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 280 { 281 return (struct ltdc_device *)enc->dev->dev_private; 282 } 283 284 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 285 { 286 enum ltdc_pix_fmt pf; 287 288 switch (drm_fmt) { 289 case DRM_FORMAT_ARGB8888: 290 case DRM_FORMAT_XRGB8888: 291 pf = PF_ARGB8888; 292 break; 293 case DRM_FORMAT_RGBA8888: 294 case DRM_FORMAT_RGBX8888: 295 pf = PF_RGBA8888; 296 break; 297 case DRM_FORMAT_RGB888: 298 pf = PF_RGB888; 299 break; 300 case DRM_FORMAT_RGB565: 301 pf = PF_RGB565; 302 break; 303 case DRM_FORMAT_ARGB1555: 304 case DRM_FORMAT_XRGB1555: 305 pf = PF_ARGB1555; 306 break; 307 case DRM_FORMAT_ARGB4444: 308 case DRM_FORMAT_XRGB4444: 309 pf = PF_ARGB4444; 310 break; 311 case DRM_FORMAT_C8: 312 pf = PF_L8; 313 break; 314 default: 315 pf = PF_NONE; 316 break; 317 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 318 } 319 320 return pf; 321 } 322 323 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 324 { 325 switch (pf) { 326 case PF_ARGB8888: 327 return DRM_FORMAT_ARGB8888; 328 case PF_RGBA8888: 329 return DRM_FORMAT_RGBA8888; 330 case PF_RGB888: 331 return DRM_FORMAT_RGB888; 332 case PF_RGB565: 333 return DRM_FORMAT_RGB565; 334 case PF_ARGB1555: 335 return DRM_FORMAT_ARGB1555; 336 case PF_ARGB4444: 337 return DRM_FORMAT_ARGB4444; 338 case PF_L8: 339 return DRM_FORMAT_C8; 340 case PF_AL44: /* No DRM support */ 341 case PF_AL88: /* No DRM support */ 342 case PF_NONE: 343 default: 344 return 0; 345 } 346 } 347 348 static inline u32 get_pixelformat_without_alpha(u32 drm) 349 { 350 switch (drm) { 351 case DRM_FORMAT_ARGB4444: 352 return DRM_FORMAT_XRGB4444; 353 case DRM_FORMAT_RGBA4444: 354 return DRM_FORMAT_RGBX4444; 355 case DRM_FORMAT_ARGB1555: 356 return DRM_FORMAT_XRGB1555; 357 case DRM_FORMAT_RGBA5551: 358 return DRM_FORMAT_RGBX5551; 359 case DRM_FORMAT_ARGB8888: 360 return DRM_FORMAT_XRGB8888; 361 case DRM_FORMAT_RGBA8888: 362 return DRM_FORMAT_RGBX8888; 363 default: 364 return 0; 365 } 366 } 367 368 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 369 { 370 struct drm_device *ddev = arg; 371 struct ltdc_device *ldev = ddev->dev_private; 372 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 373 374 /* Line IRQ : trigger the vblank event */ 375 if (ldev->irq_status & ISR_LIF) 376 drm_crtc_handle_vblank(crtc); 377 378 /* Save FIFO Underrun & Transfer Error status */ 379 mutex_lock(&ldev->err_lock); 380 if (ldev->irq_status & ISR_FUIF) 381 ldev->error_status |= ISR_FUIF; 382 if (ldev->irq_status & ISR_TERRIF) 383 ldev->error_status |= ISR_TERRIF; 384 mutex_unlock(&ldev->err_lock); 385 386 return IRQ_HANDLED; 387 } 388 389 static irqreturn_t ltdc_irq(int irq, void *arg) 390 { 391 struct drm_device *ddev = arg; 392 struct ltdc_device *ldev = ddev->dev_private; 393 394 /* Read & Clear the interrupt status */ 395 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 396 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 397 398 return IRQ_WAKE_THREAD; 399 } 400 401 /* 402 * DRM_CRTC 403 */ 404 405 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 406 { 407 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 408 struct drm_color_lut *lut; 409 u32 val; 410 int i; 411 412 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 413 return; 414 415 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 416 417 for (i = 0; i < CLUT_SIZE; i++, lut++) { 418 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 419 (lut->blue >> 8) | (i << 24); 420 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 421 } 422 } 423 424 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 425 struct drm_crtc_state *old_state) 426 { 427 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 428 429 DRM_DEBUG_DRIVER("\n"); 430 431 /* Sets the background color value */ 432 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 433 434 /* Enable IRQ */ 435 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 436 437 /* Commit shadow registers = update planes at next vblank */ 438 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 439 440 /* Enable LTDC */ 441 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 442 443 drm_crtc_vblank_on(crtc); 444 } 445 446 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 447 struct drm_crtc_state *old_state) 448 { 449 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 450 struct drm_device *ddev = crtc->dev; 451 452 DRM_DEBUG_DRIVER("\n"); 453 454 drm_crtc_vblank_off(crtc); 455 456 /* disable LTDC */ 457 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 458 459 /* disable IRQ */ 460 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 461 462 /* immediately commit disable of layers before switching off LTDC */ 463 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 464 465 pm_runtime_put_sync(ddev->dev); 466 } 467 468 #define CLK_TOLERANCE_HZ 50 469 470 static enum drm_mode_status 471 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 472 const struct drm_display_mode *mode) 473 { 474 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 475 int target = mode->clock * 1000; 476 int target_min = target - CLK_TOLERANCE_HZ; 477 int target_max = target + CLK_TOLERANCE_HZ; 478 int result; 479 480 result = clk_round_rate(ldev->pixel_clk, target); 481 482 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 483 484 /* Filter modes according to the max frequency supported by the pads */ 485 if (result > ldev->caps.pad_max_freq_hz) 486 return MODE_CLOCK_HIGH; 487 488 /* 489 * Accept all "preferred" modes: 490 * - this is important for panels because panel clock tolerances are 491 * bigger than hdmi ones and there is no reason to not accept them 492 * (the fps may vary a little but it is not a problem). 493 * - the hdmi preferred mode will be accepted too, but userland will 494 * be able to use others hdmi "valid" modes if necessary. 495 */ 496 if (mode->type & DRM_MODE_TYPE_PREFERRED) 497 return MODE_OK; 498 499 /* 500 * Filter modes according to the clock value, particularly useful for 501 * hdmi modes that require precise pixel clocks. 502 */ 503 if (result < target_min || result > target_max) 504 return MODE_CLOCK_RANGE; 505 506 return MODE_OK; 507 } 508 509 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 510 const struct drm_display_mode *mode, 511 struct drm_display_mode *adjusted_mode) 512 { 513 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 514 struct drm_device *ddev = crtc->dev; 515 int rate = mode->clock * 1000; 516 bool runtime_active; 517 int ret; 518 519 runtime_active = pm_runtime_active(ddev->dev); 520 521 if (runtime_active) 522 pm_runtime_put_sync(ddev->dev); 523 524 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 525 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 526 return false; 527 } 528 529 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 530 531 if (runtime_active) { 532 ret = pm_runtime_get_sync(ddev->dev); 533 if (ret) { 534 DRM_ERROR("Failed to fixup mode, cannot get sync\n"); 535 return false; 536 } 537 } 538 539 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 540 mode->clock, adjusted_mode->clock); 541 542 return true; 543 } 544 545 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 546 { 547 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 548 struct drm_device *ddev = crtc->dev; 549 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 550 struct videomode vm; 551 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 552 u32 total_width, total_height; 553 u32 val; 554 int ret; 555 556 if (!pm_runtime_active(ddev->dev)) { 557 ret = pm_runtime_get_sync(ddev->dev); 558 if (ret) { 559 DRM_ERROR("Failed to set mode, cannot get sync\n"); 560 return; 561 } 562 } 563 564 drm_display_mode_to_videomode(mode, &vm); 565 566 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 567 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 568 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 569 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 570 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 571 572 /* Convert video timings to ltdc timings */ 573 hsync = vm.hsync_len - 1; 574 vsync = vm.vsync_len - 1; 575 accum_hbp = hsync + vm.hback_porch; 576 accum_vbp = vsync + vm.vback_porch; 577 accum_act_w = accum_hbp + vm.hactive; 578 accum_act_h = accum_vbp + vm.vactive; 579 total_width = accum_act_w + vm.hfront_porch; 580 total_height = accum_act_h + vm.vfront_porch; 581 582 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 583 val = 0; 584 585 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 586 val |= GCR_HSPOL; 587 588 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 589 val |= GCR_VSPOL; 590 591 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 592 val |= GCR_DEPOL; 593 594 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 595 val |= GCR_PCPOL; 596 597 reg_update_bits(ldev->regs, LTDC_GCR, 598 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 599 600 /* Set Synchronization size */ 601 val = (hsync << 16) | vsync; 602 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 603 604 /* Set Accumulated Back porch */ 605 val = (accum_hbp << 16) | accum_vbp; 606 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 607 608 /* Set Accumulated Active Width */ 609 val = (accum_act_w << 16) | accum_act_h; 610 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 611 612 /* Set total width & height */ 613 val = (total_width << 16) | total_height; 614 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 615 616 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 617 } 618 619 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 620 struct drm_crtc_state *old_crtc_state) 621 { 622 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 623 struct drm_device *ddev = crtc->dev; 624 struct drm_pending_vblank_event *event = crtc->state->event; 625 626 DRM_DEBUG_ATOMIC("\n"); 627 628 ltdc_crtc_update_clut(crtc); 629 630 /* Commit shadow registers = update planes at next vblank */ 631 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 632 633 if (event) { 634 crtc->state->event = NULL; 635 636 spin_lock_irq(&ddev->event_lock); 637 if (drm_crtc_vblank_get(crtc) == 0) 638 drm_crtc_arm_vblank_event(crtc, event); 639 else 640 drm_crtc_send_vblank_event(crtc, event); 641 spin_unlock_irq(&ddev->event_lock); 642 } 643 } 644 645 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 646 .mode_valid = ltdc_crtc_mode_valid, 647 .mode_fixup = ltdc_crtc_mode_fixup, 648 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 649 .atomic_flush = ltdc_crtc_atomic_flush, 650 .atomic_enable = ltdc_crtc_atomic_enable, 651 .atomic_disable = ltdc_crtc_atomic_disable, 652 }; 653 654 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 655 { 656 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 657 658 DRM_DEBUG_DRIVER("\n"); 659 reg_set(ldev->regs, LTDC_IER, IER_LIE); 660 661 return 0; 662 } 663 664 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 665 { 666 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 667 668 DRM_DEBUG_DRIVER("\n"); 669 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 670 } 671 672 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 673 bool in_vblank_irq, int *vpos, int *hpos, 674 ktime_t *stime, ktime_t *etime, 675 const struct drm_display_mode *mode) 676 { 677 struct ltdc_device *ldev = ddev->dev_private; 678 int line, vactive_start, vactive_end, vtotal; 679 680 if (stime) 681 *stime = ktime_get(); 682 683 /* The active area starts after vsync + front porch and ends 684 * at vsync + front porc + display size. 685 * The total height also include back porch. 686 * We have 3 possible cases to handle: 687 * - line < vactive_start: vpos = line - vactive_start and will be 688 * negative 689 * - vactive_start < line < vactive_end: vpos = line - vactive_start 690 * and will be positive 691 * - line > vactive_end: vpos = line - vtotal - vactive_start 692 * and will negative 693 * 694 * Computation for the two first cases are identical so we can 695 * simplify the code and only test if line > vactive_end 696 */ 697 if (pm_runtime_active(ddev->dev)) { 698 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 699 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 700 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 701 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 702 703 if (line > vactive_end) 704 *vpos = line - vtotal - vactive_start; 705 else 706 *vpos = line - vactive_start; 707 } else { 708 *vpos = 0; 709 } 710 711 *hpos = 0; 712 713 if (etime) 714 *etime = ktime_get(); 715 716 return true; 717 } 718 719 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 720 .destroy = drm_crtc_cleanup, 721 .set_config = drm_atomic_helper_set_config, 722 .page_flip = drm_atomic_helper_page_flip, 723 .reset = drm_atomic_helper_crtc_reset, 724 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 725 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 726 .enable_vblank = ltdc_crtc_enable_vblank, 727 .disable_vblank = ltdc_crtc_disable_vblank, 728 .gamma_set = drm_atomic_helper_legacy_gamma_set, 729 }; 730 731 /* 732 * DRM_PLANE 733 */ 734 735 static int ltdc_plane_atomic_check(struct drm_plane *plane, 736 struct drm_plane_state *state) 737 { 738 struct drm_framebuffer *fb = state->fb; 739 u32 src_w, src_h; 740 741 DRM_DEBUG_DRIVER("\n"); 742 743 if (!fb) 744 return 0; 745 746 /* convert src_ from 16:16 format */ 747 src_w = state->src_w >> 16; 748 src_h = state->src_h >> 16; 749 750 /* Reject scaling */ 751 if (src_w != state->crtc_w || src_h != state->crtc_h) { 752 DRM_ERROR("Scaling is not supported"); 753 return -EINVAL; 754 } 755 756 return 0; 757 } 758 759 static void ltdc_plane_atomic_update(struct drm_plane *plane, 760 struct drm_plane_state *oldstate) 761 { 762 struct ltdc_device *ldev = plane_to_ltdc(plane); 763 struct drm_plane_state *state = plane->state; 764 struct drm_framebuffer *fb = state->fb; 765 u32 lofs = plane->index * LAY_OFS; 766 u32 x0 = state->crtc_x; 767 u32 x1 = state->crtc_x + state->crtc_w - 1; 768 u32 y0 = state->crtc_y; 769 u32 y1 = state->crtc_y + state->crtc_h - 1; 770 u32 src_x, src_y, src_w, src_h; 771 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 772 enum ltdc_pix_fmt pf; 773 774 if (!state->crtc || !fb) { 775 DRM_DEBUG_DRIVER("fb or crtc NULL"); 776 return; 777 } 778 779 /* convert src_ from 16:16 format */ 780 src_x = state->src_x >> 16; 781 src_y = state->src_y >> 16; 782 src_w = state->src_w >> 16; 783 src_h = state->src_h >> 16; 784 785 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 786 plane->base.id, fb->base.id, 787 src_w, src_h, src_x, src_y, 788 state->crtc_w, state->crtc_h, 789 state->crtc_x, state->crtc_y); 790 791 bpcr = reg_read(ldev->regs, LTDC_BPCR); 792 ahbp = (bpcr & BPCR_AHBP) >> 16; 793 avbp = bpcr & BPCR_AVBP; 794 795 /* Configures the horizontal start and stop position */ 796 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 797 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 798 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 799 800 /* Configures the vertical start and stop position */ 801 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 802 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 803 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 804 805 /* Specifies the pixel format */ 806 pf = to_ltdc_pixelformat(fb->format->format); 807 for (val = 0; val < NB_PF; val++) 808 if (ldev->caps.pix_fmt_hw[val] == pf) 809 break; 810 811 if (val == NB_PF) { 812 DRM_ERROR("Pixel format %.4s not supported\n", 813 (char *)&fb->format->format); 814 val = 0; /* set by default ARGB 32 bits */ 815 } 816 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 817 818 /* Configures the color frame buffer pitch in bytes & line length */ 819 pitch_in_bytes = fb->pitches[0]; 820 line_length = fb->format->cpp[0] * 821 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 822 val = ((pitch_in_bytes << 16) | line_length); 823 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 824 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 825 826 /* Specifies the constant alpha value */ 827 val = CONSTA_MAX; 828 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 829 830 /* Specifies the blending factors */ 831 val = BF1_PAXCA | BF2_1PAXCA; 832 if (!fb->format->has_alpha) 833 val = BF1_CA | BF2_1CA; 834 835 /* Manage hw-specific capabilities */ 836 if (ldev->caps.non_alpha_only_l1 && 837 plane->type != DRM_PLANE_TYPE_PRIMARY) 838 val = BF1_PAXCA | BF2_1PAXCA; 839 840 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 841 LXBFCR_BF2 | LXBFCR_BF1, val); 842 843 /* Configures the frame buffer line number */ 844 val = y1 - y0 + 1; 845 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 846 847 /* Sets the FB address */ 848 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 849 850 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 851 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 852 853 /* Enable layer and CLUT if needed */ 854 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 855 val |= LXCR_LEN; 856 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 857 LXCR_LEN | LXCR_CLUTEN, val); 858 859 ldev->plane_fpsi[plane->index].counter++; 860 861 mutex_lock(&ldev->err_lock); 862 if (ldev->error_status & ISR_FUIF) { 863 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 864 ldev->error_status &= ~ISR_FUIF; 865 } 866 if (ldev->error_status & ISR_TERRIF) { 867 DRM_WARN("ltdc transfer error\n"); 868 ldev->error_status &= ~ISR_TERRIF; 869 } 870 mutex_unlock(&ldev->err_lock); 871 } 872 873 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 874 struct drm_plane_state *oldstate) 875 { 876 struct ltdc_device *ldev = plane_to_ltdc(plane); 877 u32 lofs = plane->index * LAY_OFS; 878 879 /* disable layer */ 880 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 881 882 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 883 oldstate->crtc->base.id, plane->base.id); 884 } 885 886 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 887 const struct drm_plane_state *state) 888 { 889 struct drm_plane *plane = state->plane; 890 struct ltdc_device *ldev = plane_to_ltdc(plane); 891 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 892 int ms_since_last; 893 ktime_t now; 894 895 now = ktime_get(); 896 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 897 898 drm_printf(p, "\tuser_updates=%dfps\n", 899 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 900 901 fpsi->last_timestamp = now; 902 fpsi->counter = 0; 903 } 904 905 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 906 u32 format, 907 u64 modifier) 908 { 909 if (modifier == DRM_FORMAT_MOD_LINEAR) 910 return true; 911 912 return false; 913 } 914 915 static const struct drm_plane_funcs ltdc_plane_funcs = { 916 .update_plane = drm_atomic_helper_update_plane, 917 .disable_plane = drm_atomic_helper_disable_plane, 918 .destroy = drm_plane_cleanup, 919 .reset = drm_atomic_helper_plane_reset, 920 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 921 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 922 .atomic_print_state = ltdc_plane_atomic_print_state, 923 .format_mod_supported = ltdc_plane_format_mod_supported, 924 }; 925 926 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 927 .prepare_fb = drm_gem_fb_prepare_fb, 928 .atomic_check = ltdc_plane_atomic_check, 929 .atomic_update = ltdc_plane_atomic_update, 930 .atomic_disable = ltdc_plane_atomic_disable, 931 }; 932 933 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 934 enum drm_plane_type type) 935 { 936 unsigned long possible_crtcs = CRTC_MASK; 937 struct ltdc_device *ldev = ddev->dev_private; 938 struct device *dev = ddev->dev; 939 struct drm_plane *plane; 940 unsigned int i, nb_fmt = 0; 941 u32 formats[NB_PF * 2]; 942 u32 drm_fmt, drm_fmt_no_alpha; 943 const u64 *modifiers = ltdc_format_modifiers; 944 int ret; 945 946 /* Get supported pixel formats */ 947 for (i = 0; i < NB_PF; i++) { 948 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 949 if (!drm_fmt) 950 continue; 951 formats[nb_fmt++] = drm_fmt; 952 953 /* Add the no-alpha related format if any & supported */ 954 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 955 if (!drm_fmt_no_alpha) 956 continue; 957 958 /* Manage hw-specific capabilities */ 959 if (ldev->caps.non_alpha_only_l1 && 960 type != DRM_PLANE_TYPE_PRIMARY) 961 continue; 962 963 formats[nb_fmt++] = drm_fmt_no_alpha; 964 } 965 966 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 967 if (!plane) 968 return NULL; 969 970 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 971 <dc_plane_funcs, formats, nb_fmt, 972 modifiers, type, NULL); 973 if (ret < 0) 974 return NULL; 975 976 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 977 978 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 979 980 return plane; 981 } 982 983 static void ltdc_plane_destroy_all(struct drm_device *ddev) 984 { 985 struct drm_plane *plane, *plane_temp; 986 987 list_for_each_entry_safe(plane, plane_temp, 988 &ddev->mode_config.plane_list, head) 989 drm_plane_cleanup(plane); 990 } 991 992 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 993 { 994 struct ltdc_device *ldev = ddev->dev_private; 995 struct drm_plane *primary, *overlay; 996 unsigned int i; 997 int ret; 998 999 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 1000 if (!primary) { 1001 DRM_ERROR("Can not create primary plane\n"); 1002 return -EINVAL; 1003 } 1004 1005 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1006 <dc_crtc_funcs, NULL); 1007 if (ret) { 1008 DRM_ERROR("Can not initialize CRTC\n"); 1009 goto cleanup; 1010 } 1011 1012 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1013 1014 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1015 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1016 1017 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1018 1019 /* Add planes. Note : the first layer is used by primary plane */ 1020 for (i = 1; i < ldev->caps.nb_layers; i++) { 1021 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 1022 if (!overlay) { 1023 ret = -ENOMEM; 1024 DRM_ERROR("Can not create overlay plane %d\n", i); 1025 goto cleanup; 1026 } 1027 } 1028 1029 return 0; 1030 1031 cleanup: 1032 ltdc_plane_destroy_all(ddev); 1033 return ret; 1034 } 1035 1036 /* 1037 * DRM_ENCODER 1038 */ 1039 1040 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1041 .destroy = drm_encoder_cleanup, 1042 }; 1043 1044 static void ltdc_encoder_disable(struct drm_encoder *encoder) 1045 { 1046 struct drm_device *ddev = encoder->dev; 1047 1048 DRM_DEBUG_DRIVER("\n"); 1049 1050 /* Set to sleep state the pinctrl whatever type of encoder */ 1051 pinctrl_pm_select_sleep_state(ddev->dev); 1052 } 1053 1054 static void ltdc_encoder_enable(struct drm_encoder *encoder) 1055 { 1056 struct drm_device *ddev = encoder->dev; 1057 1058 DRM_DEBUG_DRIVER("\n"); 1059 1060 /* 1061 * Set to default state the pinctrl only with DPI type. 1062 * Others types like DSI, don't need pinctrl due to 1063 * internal bridge (the signals do not come out of the chipset). 1064 */ 1065 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) 1066 pinctrl_pm_select_default_state(ddev->dev); 1067 } 1068 1069 static const struct drm_encoder_helper_funcs ltdc_encoder_helper_funcs = { 1070 .disable = ltdc_encoder_disable, 1071 .enable = ltdc_encoder_enable, 1072 }; 1073 1074 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1075 { 1076 struct drm_encoder *encoder; 1077 int ret; 1078 1079 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1080 if (!encoder) 1081 return -ENOMEM; 1082 1083 encoder->possible_crtcs = CRTC_MASK; 1084 encoder->possible_clones = 0; /* No cloning support */ 1085 1086 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1087 DRM_MODE_ENCODER_DPI, NULL); 1088 1089 drm_encoder_helper_add(encoder, <dc_encoder_helper_funcs); 1090 1091 ret = drm_bridge_attach(encoder, bridge, NULL); 1092 if (ret) { 1093 drm_encoder_cleanup(encoder); 1094 return -EINVAL; 1095 } 1096 1097 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1098 1099 return 0; 1100 } 1101 1102 static int ltdc_get_caps(struct drm_device *ddev) 1103 { 1104 struct ltdc_device *ldev = ddev->dev_private; 1105 u32 bus_width_log2, lcr, gc2r; 1106 1107 /* 1108 * at least 1 layer must be managed & the number of layers 1109 * must not exceed LTDC_MAX_LAYER 1110 */ 1111 lcr = reg_read(ldev->regs, LTDC_LCR); 1112 1113 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1114 1115 /* set data bus width */ 1116 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1117 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1118 ldev->caps.bus_width = 8 << bus_width_log2; 1119 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1120 1121 switch (ldev->caps.hw_version) { 1122 case HWVER_10200: 1123 case HWVER_10300: 1124 ldev->caps.reg_ofs = REG_OFS_NONE; 1125 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1126 /* 1127 * Hw older versions support non-alpha color formats derived 1128 * from native alpha color formats only on the primary layer. 1129 * For instance, RG16 native format without alpha works fine 1130 * on 2nd layer but XR24 (derived color format from AR24) 1131 * does not work on 2nd layer. 1132 */ 1133 ldev->caps.non_alpha_only_l1 = true; 1134 ldev->caps.pad_max_freq_hz = 90000000; 1135 if (ldev->caps.hw_version == HWVER_10200) 1136 ldev->caps.pad_max_freq_hz = 65000000; 1137 break; 1138 case HWVER_20101: 1139 ldev->caps.reg_ofs = REG_OFS_4; 1140 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1141 ldev->caps.non_alpha_only_l1 = false; 1142 ldev->caps.pad_max_freq_hz = 150000000; 1143 break; 1144 default: 1145 return -ENODEV; 1146 } 1147 1148 return 0; 1149 } 1150 1151 void ltdc_suspend(struct drm_device *ddev) 1152 { 1153 struct ltdc_device *ldev = ddev->dev_private; 1154 1155 DRM_DEBUG_DRIVER("\n"); 1156 clk_disable_unprepare(ldev->pixel_clk); 1157 } 1158 1159 int ltdc_resume(struct drm_device *ddev) 1160 { 1161 struct ltdc_device *ldev = ddev->dev_private; 1162 int ret; 1163 1164 DRM_DEBUG_DRIVER("\n"); 1165 1166 ret = clk_prepare_enable(ldev->pixel_clk); 1167 if (ret) { 1168 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1169 return ret; 1170 } 1171 1172 return 0; 1173 } 1174 1175 int ltdc_load(struct drm_device *ddev) 1176 { 1177 struct platform_device *pdev = to_platform_device(ddev->dev); 1178 struct ltdc_device *ldev = ddev->dev_private; 1179 struct device *dev = ddev->dev; 1180 struct device_node *np = dev->of_node; 1181 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1182 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1183 struct drm_crtc *crtc; 1184 struct reset_control *rstc; 1185 struct resource *res; 1186 int irq, ret, i, endpoint_not_ready = -ENODEV; 1187 1188 DRM_DEBUG_DRIVER("\n"); 1189 1190 /* Get endpoints if any */ 1191 for (i = 0; i < MAX_ENDPOINTS; i++) { 1192 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1193 &bridge[i]); 1194 1195 /* 1196 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1197 * else if at least one endpoint is ready, continue probing. 1198 */ 1199 if (ret == -EPROBE_DEFER) 1200 return ret; 1201 else if (!ret) 1202 endpoint_not_ready = 0; 1203 } 1204 1205 if (endpoint_not_ready) 1206 return endpoint_not_ready; 1207 1208 rstc = devm_reset_control_get_exclusive(dev, NULL); 1209 1210 mutex_init(&ldev->err_lock); 1211 1212 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1213 if (IS_ERR(ldev->pixel_clk)) { 1214 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1215 DRM_ERROR("Unable to get lcd clock\n"); 1216 return PTR_ERR(ldev->pixel_clk); 1217 } 1218 1219 if (clk_prepare_enable(ldev->pixel_clk)) { 1220 DRM_ERROR("Unable to prepare pixel clock\n"); 1221 return -ENODEV; 1222 } 1223 1224 if (!IS_ERR(rstc)) { 1225 reset_control_assert(rstc); 1226 usleep_range(10, 20); 1227 reset_control_deassert(rstc); 1228 } 1229 1230 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1231 ldev->regs = devm_ioremap_resource(dev, res); 1232 if (IS_ERR(ldev->regs)) { 1233 DRM_ERROR("Unable to get ltdc registers\n"); 1234 ret = PTR_ERR(ldev->regs); 1235 goto err; 1236 } 1237 1238 /* Disable interrupts */ 1239 reg_clear(ldev->regs, LTDC_IER, 1240 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1241 1242 for (i = 0; i < MAX_IRQ; i++) { 1243 irq = platform_get_irq(pdev, i); 1244 if (irq == -EPROBE_DEFER) 1245 goto err; 1246 1247 if (irq < 0) 1248 continue; 1249 1250 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1251 ltdc_irq_thread, IRQF_ONESHOT, 1252 dev_name(dev), ddev); 1253 if (ret) { 1254 DRM_ERROR("Failed to register LTDC interrupt\n"); 1255 goto err; 1256 } 1257 } 1258 1259 1260 ret = ltdc_get_caps(ddev); 1261 if (ret) { 1262 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1263 ldev->caps.hw_version); 1264 goto err; 1265 } 1266 1267 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1268 1269 /* Add endpoints panels or bridges if any */ 1270 for (i = 0; i < MAX_ENDPOINTS; i++) { 1271 if (panel[i]) { 1272 bridge[i] = drm_panel_bridge_add_typed(panel[i], 1273 DRM_MODE_CONNECTOR_DPI); 1274 if (IS_ERR(bridge[i])) { 1275 DRM_ERROR("panel-bridge endpoint %d\n", i); 1276 ret = PTR_ERR(bridge[i]); 1277 goto err; 1278 } 1279 } 1280 1281 if (bridge[i]) { 1282 ret = ltdc_encoder_init(ddev, bridge[i]); 1283 if (ret) { 1284 DRM_ERROR("init encoder endpoint %d\n", i); 1285 goto err; 1286 } 1287 } 1288 } 1289 1290 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1291 if (!crtc) { 1292 DRM_ERROR("Failed to allocate crtc\n"); 1293 ret = -ENOMEM; 1294 goto err; 1295 } 1296 1297 ddev->mode_config.allow_fb_modifiers = true; 1298 1299 ret = ltdc_crtc_init(ddev, crtc); 1300 if (ret) { 1301 DRM_ERROR("Failed to init crtc\n"); 1302 goto err; 1303 } 1304 1305 ret = drm_vblank_init(ddev, NB_CRTC); 1306 if (ret) { 1307 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1308 goto err; 1309 } 1310 1311 /* Allow usage of vblank without having to call drm_irq_install */ 1312 ddev->irq_enabled = 1; 1313 1314 clk_disable_unprepare(ldev->pixel_clk); 1315 1316 pinctrl_pm_select_sleep_state(ddev->dev); 1317 1318 pm_runtime_enable(ddev->dev); 1319 1320 return 0; 1321 err: 1322 for (i = 0; i < MAX_ENDPOINTS; i++) 1323 drm_panel_bridge_remove(bridge[i]); 1324 1325 clk_disable_unprepare(ldev->pixel_clk); 1326 1327 return ret; 1328 } 1329 1330 void ltdc_unload(struct drm_device *ddev) 1331 { 1332 int i; 1333 1334 DRM_DEBUG_DRIVER("\n"); 1335 1336 for (i = 0; i < MAX_ENDPOINTS; i++) 1337 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1338 1339 pm_runtime_disable(ddev->dev); 1340 } 1341 1342 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1343 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1344 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1345 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1346 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1347 MODULE_LICENSE("GPL v2"); 1348