1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (C) STMicroelectronics SA 2017 4 * 5 * Authors: Philippe Cornu <philippe.cornu@st.com> 6 * Yannick Fertre <yannick.fertre@st.com> 7 * Fabien Dessenne <fabien.dessenne@st.com> 8 * Mickael Reulier <mickael.reulier@st.com> 9 */ 10 11 #include <linux/clk.h> 12 #include <linux/component.h> 13 #include <linux/delay.h> 14 #include <linux/interrupt.h> 15 #include <linux/module.h> 16 #include <linux/of_address.h> 17 #include <linux/of_graph.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 22 #include <drm/drm_atomic.h> 23 #include <drm/drm_atomic_helper.h> 24 #include <drm/drm_bridge.h> 25 #include <drm/drm_device.h> 26 #include <drm/drm_fb_cma_helper.h> 27 #include <drm/drm_fourcc.h> 28 #include <drm/drm_gem_cma_helper.h> 29 #include <drm/drm_of.h> 30 #include <drm/drm_plane_helper.h> 31 #include <drm/drm_probe_helper.h> 32 #include <drm/drm_vblank.h> 33 34 #include <video/videomode.h> 35 36 #include "ltdc.h" 37 38 #define NB_CRTC 1 39 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0) 40 41 #define MAX_IRQ 4 42 43 #define MAX_ENDPOINTS 2 44 45 #define HWVER_10200 0x010200 46 #define HWVER_10300 0x010300 47 #define HWVER_20101 0x020101 48 49 /* 50 * The address of some registers depends on the HW version: such registers have 51 * an extra offset specified with reg_ofs. 52 */ 53 #define REG_OFS_NONE 0 54 #define REG_OFS_4 4 /* Insertion of "Layer Conf. 2" reg */ 55 #define REG_OFS (ldev->caps.reg_ofs) 56 #define LAY_OFS 0x80 /* Register Offset between 2 layers */ 57 58 /* Global register offsets */ 59 #define LTDC_IDR 0x0000 /* IDentification */ 60 #define LTDC_LCR 0x0004 /* Layer Count */ 61 #define LTDC_SSCR 0x0008 /* Synchronization Size Configuration */ 62 #define LTDC_BPCR 0x000C /* Back Porch Configuration */ 63 #define LTDC_AWCR 0x0010 /* Active Width Configuration */ 64 #define LTDC_TWCR 0x0014 /* Total Width Configuration */ 65 #define LTDC_GCR 0x0018 /* Global Control */ 66 #define LTDC_GC1R 0x001C /* Global Configuration 1 */ 67 #define LTDC_GC2R 0x0020 /* Global Configuration 2 */ 68 #define LTDC_SRCR 0x0024 /* Shadow Reload Configuration */ 69 #define LTDC_GACR 0x0028 /* GAmma Correction */ 70 #define LTDC_BCCR 0x002C /* Background Color Configuration */ 71 #define LTDC_IER 0x0034 /* Interrupt Enable */ 72 #define LTDC_ISR 0x0038 /* Interrupt Status */ 73 #define LTDC_ICR 0x003C /* Interrupt Clear */ 74 #define LTDC_LIPCR 0x0040 /* Line Interrupt Position Conf. */ 75 #define LTDC_CPSR 0x0044 /* Current Position Status */ 76 #define LTDC_CDSR 0x0048 /* Current Display Status */ 77 78 /* Layer register offsets */ 79 #define LTDC_L1LC1R (0x80) /* L1 Layer Configuration 1 */ 80 #define LTDC_L1LC2R (0x84) /* L1 Layer Configuration 2 */ 81 #define LTDC_L1CR (0x84 + REG_OFS)/* L1 Control */ 82 #define LTDC_L1WHPCR (0x88 + REG_OFS)/* L1 Window Hor Position Config */ 83 #define LTDC_L1WVPCR (0x8C + REG_OFS)/* L1 Window Vert Position Config */ 84 #define LTDC_L1CKCR (0x90 + REG_OFS)/* L1 Color Keying Configuration */ 85 #define LTDC_L1PFCR (0x94 + REG_OFS)/* L1 Pixel Format Configuration */ 86 #define LTDC_L1CACR (0x98 + REG_OFS)/* L1 Constant Alpha Config */ 87 #define LTDC_L1DCCR (0x9C + REG_OFS)/* L1 Default Color Configuration */ 88 #define LTDC_L1BFCR (0xA0 + REG_OFS)/* L1 Blend Factors Configuration */ 89 #define LTDC_L1FBBCR (0xA4 + REG_OFS)/* L1 FrameBuffer Bus Control */ 90 #define LTDC_L1AFBCR (0xA8 + REG_OFS)/* L1 AuxFB Control */ 91 #define LTDC_L1CFBAR (0xAC + REG_OFS)/* L1 Color FrameBuffer Address */ 92 #define LTDC_L1CFBLR (0xB0 + REG_OFS)/* L1 Color FrameBuffer Length */ 93 #define LTDC_L1CFBLNR (0xB4 + REG_OFS)/* L1 Color FrameBuffer Line Nb */ 94 #define LTDC_L1AFBAR (0xB8 + REG_OFS)/* L1 AuxFB Address */ 95 #define LTDC_L1AFBLR (0xBC + REG_OFS)/* L1 AuxFB Length */ 96 #define LTDC_L1AFBLNR (0xC0 + REG_OFS)/* L1 AuxFB Line Number */ 97 #define LTDC_L1CLUTWR (0xC4 + REG_OFS)/* L1 CLUT Write */ 98 #define LTDC_L1YS1R (0xE0 + REG_OFS)/* L1 YCbCr Scale 1 */ 99 #define LTDC_L1YS2R (0xE4 + REG_OFS)/* L1 YCbCr Scale 2 */ 100 101 /* Bit definitions */ 102 #define SSCR_VSH GENMASK(10, 0) /* Vertical Synchronization Height */ 103 #define SSCR_HSW GENMASK(27, 16) /* Horizontal Synchronization Width */ 104 105 #define BPCR_AVBP GENMASK(10, 0) /* Accumulated Vertical Back Porch */ 106 #define BPCR_AHBP GENMASK(27, 16) /* Accumulated Horizontal Back Porch */ 107 108 #define AWCR_AAH GENMASK(10, 0) /* Accumulated Active Height */ 109 #define AWCR_AAW GENMASK(27, 16) /* Accumulated Active Width */ 110 111 #define TWCR_TOTALH GENMASK(10, 0) /* TOTAL Height */ 112 #define TWCR_TOTALW GENMASK(27, 16) /* TOTAL Width */ 113 114 #define GCR_LTDCEN BIT(0) /* LTDC ENable */ 115 #define GCR_DEN BIT(16) /* Dither ENable */ 116 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */ 117 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */ 118 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */ 119 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */ 120 121 #define GC1R_WBCH GENMASK(3, 0) /* Width of Blue CHannel output */ 122 #define GC1R_WGCH GENMASK(7, 4) /* Width of Green Channel output */ 123 #define GC1R_WRCH GENMASK(11, 8) /* Width of Red Channel output */ 124 #define GC1R_PBEN BIT(12) /* Precise Blending ENable */ 125 #define GC1R_DT GENMASK(15, 14) /* Dithering Technique */ 126 #define GC1R_GCT GENMASK(19, 17) /* Gamma Correction Technique */ 127 #define GC1R_SHREN BIT(21) /* SHadow Registers ENabled */ 128 #define GC1R_BCP BIT(22) /* Background Colour Programmable */ 129 #define GC1R_BBEN BIT(23) /* Background Blending ENabled */ 130 #define GC1R_LNIP BIT(24) /* Line Number IRQ Position */ 131 #define GC1R_TP BIT(25) /* Timing Programmable */ 132 #define GC1R_IPP BIT(26) /* IRQ Polarity Programmable */ 133 #define GC1R_SPP BIT(27) /* Sync Polarity Programmable */ 134 #define GC1R_DWP BIT(28) /* Dither Width Programmable */ 135 #define GC1R_STREN BIT(29) /* STatus Registers ENabled */ 136 #define GC1R_BMEN BIT(31) /* Blind Mode ENabled */ 137 138 #define GC2R_EDCA BIT(0) /* External Display Control Ability */ 139 #define GC2R_STSAEN BIT(1) /* Slave Timing Sync Ability ENabled */ 140 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */ 141 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */ 142 #define GC2R_BW GENMASK(6, 4) /* Bus Width (log2 of nb of bytes) */ 143 #define GC2R_EDCEN BIT(7) /* External Display Control ENabled */ 144 145 #define SRCR_IMR BIT(0) /* IMmediate Reload */ 146 #define SRCR_VBR BIT(1) /* Vertical Blanking Reload */ 147 148 #define BCCR_BCBLACK 0x00 /* Background Color BLACK */ 149 #define BCCR_BCBLUE GENMASK(7, 0) /* Background Color BLUE */ 150 #define BCCR_BCGREEN GENMASK(15, 8) /* Background Color GREEN */ 151 #define BCCR_BCRED GENMASK(23, 16) /* Background Color RED */ 152 #define BCCR_BCWHITE GENMASK(23, 0) /* Background Color WHITE */ 153 154 #define IER_LIE BIT(0) /* Line Interrupt Enable */ 155 #define IER_FUIE BIT(1) /* Fifo Underrun Interrupt Enable */ 156 #define IER_TERRIE BIT(2) /* Transfer ERRor Interrupt Enable */ 157 #define IER_RRIE BIT(3) /* Register Reload Interrupt enable */ 158 159 #define CPSR_CYPOS GENMASK(15, 0) /* Current Y position */ 160 161 #define ISR_LIF BIT(0) /* Line Interrupt Flag */ 162 #define ISR_FUIF BIT(1) /* Fifo Underrun Interrupt Flag */ 163 #define ISR_TERRIF BIT(2) /* Transfer ERRor Interrupt Flag */ 164 #define ISR_RRIF BIT(3) /* Register Reload Interrupt Flag */ 165 166 #define LXCR_LEN BIT(0) /* Layer ENable */ 167 #define LXCR_COLKEN BIT(1) /* Color Keying Enable */ 168 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */ 169 170 #define LXWHPCR_WHSTPOS GENMASK(11, 0) /* Window Horizontal StarT POSition */ 171 #define LXWHPCR_WHSPPOS GENMASK(27, 16) /* Window Horizontal StoP POSition */ 172 173 #define LXWVPCR_WVSTPOS GENMASK(10, 0) /* Window Vertical StarT POSition */ 174 #define LXWVPCR_WVSPPOS GENMASK(26, 16) /* Window Vertical StoP POSition */ 175 176 #define LXPFCR_PF GENMASK(2, 0) /* Pixel Format */ 177 178 #define LXCACR_CONSTA GENMASK(7, 0) /* CONSTant Alpha */ 179 180 #define LXBFCR_BF2 GENMASK(2, 0) /* Blending Factor 2 */ 181 #define LXBFCR_BF1 GENMASK(10, 8) /* Blending Factor 1 */ 182 183 #define LXCFBLR_CFBLL GENMASK(12, 0) /* Color Frame Buffer Line Length */ 184 #define LXCFBLR_CFBP GENMASK(28, 16) /* Color Frame Buffer Pitch in bytes */ 185 186 #define LXCFBLNR_CFBLN GENMASK(10, 0) /* Color Frame Buffer Line Number */ 187 188 #define CLUT_SIZE 256 189 190 #define CONSTA_MAX 0xFF /* CONSTant Alpha MAX= 1.0 */ 191 #define BF1_PAXCA 0x600 /* Pixel Alpha x Constant Alpha */ 192 #define BF1_CA 0x400 /* Constant Alpha */ 193 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */ 194 #define BF2_1CA 0x005 /* 1 - Constant Alpha */ 195 196 #define NB_PF 8 /* Max nb of HW pixel format */ 197 198 enum ltdc_pix_fmt { 199 PF_NONE, 200 /* RGB formats */ 201 PF_ARGB8888, /* ARGB [32 bits] */ 202 PF_RGBA8888, /* RGBA [32 bits] */ 203 PF_RGB888, /* RGB [24 bits] */ 204 PF_RGB565, /* RGB [16 bits] */ 205 PF_ARGB1555, /* ARGB A:1 bit RGB:15 bits [16 bits] */ 206 PF_ARGB4444, /* ARGB A:4 bits R/G/B: 4 bits each [16 bits] */ 207 /* Indexed formats */ 208 PF_L8, /* Indexed 8 bits [8 bits] */ 209 PF_AL44, /* Alpha:4 bits + indexed 4 bits [8 bits] */ 210 PF_AL88 /* Alpha:8 bits + indexed 8 bits [16 bits] */ 211 }; 212 213 /* The index gives the encoding of the pixel format for an HW version */ 214 static const enum ltdc_pix_fmt ltdc_pix_fmt_a0[NB_PF] = { 215 PF_ARGB8888, /* 0x00 */ 216 PF_RGB888, /* 0x01 */ 217 PF_RGB565, /* 0x02 */ 218 PF_ARGB1555, /* 0x03 */ 219 PF_ARGB4444, /* 0x04 */ 220 PF_L8, /* 0x05 */ 221 PF_AL44, /* 0x06 */ 222 PF_AL88 /* 0x07 */ 223 }; 224 225 static const enum ltdc_pix_fmt ltdc_pix_fmt_a1[NB_PF] = { 226 PF_ARGB8888, /* 0x00 */ 227 PF_RGB888, /* 0x01 */ 228 PF_RGB565, /* 0x02 */ 229 PF_RGBA8888, /* 0x03 */ 230 PF_AL44, /* 0x04 */ 231 PF_L8, /* 0x05 */ 232 PF_ARGB1555, /* 0x06 */ 233 PF_ARGB4444 /* 0x07 */ 234 }; 235 236 static const u64 ltdc_format_modifiers[] = { 237 DRM_FORMAT_MOD_LINEAR, 238 DRM_FORMAT_MOD_INVALID 239 }; 240 241 static inline u32 reg_read(void __iomem *base, u32 reg) 242 { 243 return readl_relaxed(base + reg); 244 } 245 246 static inline void reg_write(void __iomem *base, u32 reg, u32 val) 247 { 248 writel_relaxed(val, base + reg); 249 } 250 251 static inline void reg_set(void __iomem *base, u32 reg, u32 mask) 252 { 253 reg_write(base, reg, reg_read(base, reg) | mask); 254 } 255 256 static inline void reg_clear(void __iomem *base, u32 reg, u32 mask) 257 { 258 reg_write(base, reg, reg_read(base, reg) & ~mask); 259 } 260 261 static inline void reg_update_bits(void __iomem *base, u32 reg, u32 mask, 262 u32 val) 263 { 264 reg_write(base, reg, (reg_read(base, reg) & ~mask) | val); 265 } 266 267 static inline struct ltdc_device *crtc_to_ltdc(struct drm_crtc *crtc) 268 { 269 return (struct ltdc_device *)crtc->dev->dev_private; 270 } 271 272 static inline struct ltdc_device *plane_to_ltdc(struct drm_plane *plane) 273 { 274 return (struct ltdc_device *)plane->dev->dev_private; 275 } 276 277 static inline struct ltdc_device *encoder_to_ltdc(struct drm_encoder *enc) 278 { 279 return (struct ltdc_device *)enc->dev->dev_private; 280 } 281 282 static inline enum ltdc_pix_fmt to_ltdc_pixelformat(u32 drm_fmt) 283 { 284 enum ltdc_pix_fmt pf; 285 286 switch (drm_fmt) { 287 case DRM_FORMAT_ARGB8888: 288 case DRM_FORMAT_XRGB8888: 289 pf = PF_ARGB8888; 290 break; 291 case DRM_FORMAT_RGBA8888: 292 case DRM_FORMAT_RGBX8888: 293 pf = PF_RGBA8888; 294 break; 295 case DRM_FORMAT_RGB888: 296 pf = PF_RGB888; 297 break; 298 case DRM_FORMAT_RGB565: 299 pf = PF_RGB565; 300 break; 301 case DRM_FORMAT_ARGB1555: 302 case DRM_FORMAT_XRGB1555: 303 pf = PF_ARGB1555; 304 break; 305 case DRM_FORMAT_ARGB4444: 306 case DRM_FORMAT_XRGB4444: 307 pf = PF_ARGB4444; 308 break; 309 case DRM_FORMAT_C8: 310 pf = PF_L8; 311 break; 312 default: 313 pf = PF_NONE; 314 break; 315 /* Note: There are no DRM_FORMAT for AL44 and AL88 */ 316 } 317 318 return pf; 319 } 320 321 static inline u32 to_drm_pixelformat(enum ltdc_pix_fmt pf) 322 { 323 switch (pf) { 324 case PF_ARGB8888: 325 return DRM_FORMAT_ARGB8888; 326 case PF_RGBA8888: 327 return DRM_FORMAT_RGBA8888; 328 case PF_RGB888: 329 return DRM_FORMAT_RGB888; 330 case PF_RGB565: 331 return DRM_FORMAT_RGB565; 332 case PF_ARGB1555: 333 return DRM_FORMAT_ARGB1555; 334 case PF_ARGB4444: 335 return DRM_FORMAT_ARGB4444; 336 case PF_L8: 337 return DRM_FORMAT_C8; 338 case PF_AL44: /* No DRM support */ 339 case PF_AL88: /* No DRM support */ 340 case PF_NONE: 341 default: 342 return 0; 343 } 344 } 345 346 static inline u32 get_pixelformat_without_alpha(u32 drm) 347 { 348 switch (drm) { 349 case DRM_FORMAT_ARGB4444: 350 return DRM_FORMAT_XRGB4444; 351 case DRM_FORMAT_RGBA4444: 352 return DRM_FORMAT_RGBX4444; 353 case DRM_FORMAT_ARGB1555: 354 return DRM_FORMAT_XRGB1555; 355 case DRM_FORMAT_RGBA5551: 356 return DRM_FORMAT_RGBX5551; 357 case DRM_FORMAT_ARGB8888: 358 return DRM_FORMAT_XRGB8888; 359 case DRM_FORMAT_RGBA8888: 360 return DRM_FORMAT_RGBX8888; 361 default: 362 return 0; 363 } 364 } 365 366 static irqreturn_t ltdc_irq_thread(int irq, void *arg) 367 { 368 struct drm_device *ddev = arg; 369 struct ltdc_device *ldev = ddev->dev_private; 370 struct drm_crtc *crtc = drm_crtc_from_index(ddev, 0); 371 372 /* Line IRQ : trigger the vblank event */ 373 if (ldev->irq_status & ISR_LIF) 374 drm_crtc_handle_vblank(crtc); 375 376 /* Save FIFO Underrun & Transfer Error status */ 377 mutex_lock(&ldev->err_lock); 378 if (ldev->irq_status & ISR_FUIF) 379 ldev->error_status |= ISR_FUIF; 380 if (ldev->irq_status & ISR_TERRIF) 381 ldev->error_status |= ISR_TERRIF; 382 mutex_unlock(&ldev->err_lock); 383 384 return IRQ_HANDLED; 385 } 386 387 static irqreturn_t ltdc_irq(int irq, void *arg) 388 { 389 struct drm_device *ddev = arg; 390 struct ltdc_device *ldev = ddev->dev_private; 391 392 /* Read & Clear the interrupt status */ 393 ldev->irq_status = reg_read(ldev->regs, LTDC_ISR); 394 reg_write(ldev->regs, LTDC_ICR, ldev->irq_status); 395 396 return IRQ_WAKE_THREAD; 397 } 398 399 /* 400 * DRM_CRTC 401 */ 402 403 static void ltdc_crtc_update_clut(struct drm_crtc *crtc) 404 { 405 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 406 struct drm_color_lut *lut; 407 u32 val; 408 int i; 409 410 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) 411 return; 412 413 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; 414 415 for (i = 0; i < CLUT_SIZE; i++, lut++) { 416 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | 417 (lut->blue >> 8) | (i << 24); 418 reg_write(ldev->regs, LTDC_L1CLUTWR, val); 419 } 420 } 421 422 static void ltdc_crtc_atomic_enable(struct drm_crtc *crtc, 423 struct drm_crtc_state *old_state) 424 { 425 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 426 427 DRM_DEBUG_DRIVER("\n"); 428 429 /* Sets the background color value */ 430 reg_write(ldev->regs, LTDC_BCCR, BCCR_BCBLACK); 431 432 /* Enable IRQ */ 433 reg_set(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 434 435 /* Commit shadow registers = update planes at next vblank */ 436 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 437 438 /* Enable LTDC */ 439 reg_set(ldev->regs, LTDC_GCR, GCR_LTDCEN); 440 441 drm_crtc_vblank_on(crtc); 442 } 443 444 static void ltdc_crtc_atomic_disable(struct drm_crtc *crtc, 445 struct drm_crtc_state *old_state) 446 { 447 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 448 struct drm_device *ddev = crtc->dev; 449 450 DRM_DEBUG_DRIVER("\n"); 451 452 drm_crtc_vblank_off(crtc); 453 454 /* disable LTDC */ 455 reg_clear(ldev->regs, LTDC_GCR, GCR_LTDCEN); 456 457 /* disable IRQ */ 458 reg_clear(ldev->regs, LTDC_IER, IER_RRIE | IER_FUIE | IER_TERRIE); 459 460 /* immediately commit disable of layers before switching off LTDC */ 461 reg_set(ldev->regs, LTDC_SRCR, SRCR_IMR); 462 463 pm_runtime_put_sync(ddev->dev); 464 } 465 466 #define CLK_TOLERANCE_HZ 50 467 468 static enum drm_mode_status 469 ltdc_crtc_mode_valid(struct drm_crtc *crtc, 470 const struct drm_display_mode *mode) 471 { 472 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 473 int target = mode->clock * 1000; 474 int target_min = target - CLK_TOLERANCE_HZ; 475 int target_max = target + CLK_TOLERANCE_HZ; 476 int result; 477 478 result = clk_round_rate(ldev->pixel_clk, target); 479 480 DRM_DEBUG_DRIVER("clk rate target %d, available %d\n", target, result); 481 482 /* Filter modes according to the max frequency supported by the pads */ 483 if (result > ldev->caps.pad_max_freq_hz) 484 return MODE_CLOCK_HIGH; 485 486 /* 487 * Accept all "preferred" modes: 488 * - this is important for panels because panel clock tolerances are 489 * bigger than hdmi ones and there is no reason to not accept them 490 * (the fps may vary a little but it is not a problem). 491 * - the hdmi preferred mode will be accepted too, but userland will 492 * be able to use others hdmi "valid" modes if necessary. 493 */ 494 if (mode->type & DRM_MODE_TYPE_PREFERRED) 495 return MODE_OK; 496 497 /* 498 * Filter modes according to the clock value, particularly useful for 499 * hdmi modes that require precise pixel clocks. 500 */ 501 if (result < target_min || result > target_max) 502 return MODE_CLOCK_RANGE; 503 504 return MODE_OK; 505 } 506 507 static bool ltdc_crtc_mode_fixup(struct drm_crtc *crtc, 508 const struct drm_display_mode *mode, 509 struct drm_display_mode *adjusted_mode) 510 { 511 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 512 struct drm_device *ddev = crtc->dev; 513 int rate = mode->clock * 1000; 514 bool runtime_active; 515 int ret; 516 517 runtime_active = pm_runtime_active(ddev->dev); 518 519 if (runtime_active) 520 pm_runtime_put_sync(ddev->dev); 521 522 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { 523 DRM_ERROR("Cannot set rate (%dHz) for pixel clk\n", rate); 524 return false; 525 } 526 527 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; 528 529 if (runtime_active) { 530 ret = pm_runtime_get_sync(ddev->dev); 531 if (ret) { 532 DRM_ERROR("Failed to fixup mode, cannot get sync\n"); 533 return false; 534 } 535 } 536 537 DRM_DEBUG_DRIVER("requested clock %dkHz, adjusted clock %dkHz\n", 538 mode->clock, adjusted_mode->clock); 539 540 return true; 541 } 542 543 static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) 544 { 545 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 546 struct drm_device *ddev = crtc->dev; 547 struct drm_display_mode *mode = &crtc->state->adjusted_mode; 548 struct videomode vm; 549 u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; 550 u32 total_width, total_height; 551 u32 val; 552 int ret; 553 554 if (!pm_runtime_active(ddev->dev)) { 555 ret = pm_runtime_get_sync(ddev->dev); 556 if (ret) { 557 DRM_ERROR("Failed to set mode, cannot get sync\n"); 558 return; 559 } 560 } 561 562 drm_display_mode_to_videomode(mode, &vm); 563 564 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); 565 DRM_DEBUG_DRIVER("Video mode: %dx%d", vm.hactive, vm.vactive); 566 DRM_DEBUG_DRIVER(" hfp %d hbp %d hsl %d vfp %d vbp %d vsl %d\n", 567 vm.hfront_porch, vm.hback_porch, vm.hsync_len, 568 vm.vfront_porch, vm.vback_porch, vm.vsync_len); 569 570 /* Convert video timings to ltdc timings */ 571 hsync = vm.hsync_len - 1; 572 vsync = vm.vsync_len - 1; 573 accum_hbp = hsync + vm.hback_porch; 574 accum_vbp = vsync + vm.vback_porch; 575 accum_act_w = accum_hbp + vm.hactive; 576 accum_act_h = accum_vbp + vm.vactive; 577 total_width = accum_act_w + vm.hfront_porch; 578 total_height = accum_act_h + vm.vfront_porch; 579 580 /* Configures the HS, VS, DE and PC polarities. Default Active Low */ 581 val = 0; 582 583 if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) 584 val |= GCR_HSPOL; 585 586 if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) 587 val |= GCR_VSPOL; 588 589 if (vm.flags & DISPLAY_FLAGS_DE_LOW) 590 val |= GCR_DEPOL; 591 592 if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) 593 val |= GCR_PCPOL; 594 595 reg_update_bits(ldev->regs, LTDC_GCR, 596 GCR_HSPOL | GCR_VSPOL | GCR_DEPOL | GCR_PCPOL, val); 597 598 /* Set Synchronization size */ 599 val = (hsync << 16) | vsync; 600 reg_update_bits(ldev->regs, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); 601 602 /* Set Accumulated Back porch */ 603 val = (accum_hbp << 16) | accum_vbp; 604 reg_update_bits(ldev->regs, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); 605 606 /* Set Accumulated Active Width */ 607 val = (accum_act_w << 16) | accum_act_h; 608 reg_update_bits(ldev->regs, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); 609 610 /* Set total width & height */ 611 val = (total_width << 16) | total_height; 612 reg_update_bits(ldev->regs, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); 613 614 reg_write(ldev->regs, LTDC_LIPCR, (accum_act_h + 1)); 615 } 616 617 static void ltdc_crtc_atomic_flush(struct drm_crtc *crtc, 618 struct drm_crtc_state *old_crtc_state) 619 { 620 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 621 struct drm_device *ddev = crtc->dev; 622 struct drm_pending_vblank_event *event = crtc->state->event; 623 624 DRM_DEBUG_ATOMIC("\n"); 625 626 ltdc_crtc_update_clut(crtc); 627 628 /* Commit shadow registers = update planes at next vblank */ 629 reg_set(ldev->regs, LTDC_SRCR, SRCR_VBR); 630 631 if (event) { 632 crtc->state->event = NULL; 633 634 spin_lock_irq(&ddev->event_lock); 635 if (drm_crtc_vblank_get(crtc) == 0) 636 drm_crtc_arm_vblank_event(crtc, event); 637 else 638 drm_crtc_send_vblank_event(crtc, event); 639 spin_unlock_irq(&ddev->event_lock); 640 } 641 } 642 643 static const struct drm_crtc_helper_funcs ltdc_crtc_helper_funcs = { 644 .mode_valid = ltdc_crtc_mode_valid, 645 .mode_fixup = ltdc_crtc_mode_fixup, 646 .mode_set_nofb = ltdc_crtc_mode_set_nofb, 647 .atomic_flush = ltdc_crtc_atomic_flush, 648 .atomic_enable = ltdc_crtc_atomic_enable, 649 .atomic_disable = ltdc_crtc_atomic_disable, 650 }; 651 652 static int ltdc_crtc_enable_vblank(struct drm_crtc *crtc) 653 { 654 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 655 656 DRM_DEBUG_DRIVER("\n"); 657 reg_set(ldev->regs, LTDC_IER, IER_LIE); 658 659 return 0; 660 } 661 662 static void ltdc_crtc_disable_vblank(struct drm_crtc *crtc) 663 { 664 struct ltdc_device *ldev = crtc_to_ltdc(crtc); 665 666 DRM_DEBUG_DRIVER("\n"); 667 reg_clear(ldev->regs, LTDC_IER, IER_LIE); 668 } 669 670 bool ltdc_crtc_scanoutpos(struct drm_device *ddev, unsigned int pipe, 671 bool in_vblank_irq, int *vpos, int *hpos, 672 ktime_t *stime, ktime_t *etime, 673 const struct drm_display_mode *mode) 674 { 675 struct ltdc_device *ldev = ddev->dev_private; 676 int line, vactive_start, vactive_end, vtotal; 677 678 if (stime) 679 *stime = ktime_get(); 680 681 /* The active area starts after vsync + front porch and ends 682 * at vsync + front porc + display size. 683 * The total height also include back porch. 684 * We have 3 possible cases to handle: 685 * - line < vactive_start: vpos = line - vactive_start and will be 686 * negative 687 * - vactive_start < line < vactive_end: vpos = line - vactive_start 688 * and will be positive 689 * - line > vactive_end: vpos = line - vtotal - vactive_start 690 * and will negative 691 * 692 * Computation for the two first cases are identical so we can 693 * simplify the code and only test if line > vactive_end 694 */ 695 if (pm_runtime_active(ddev->dev)) { 696 line = reg_read(ldev->regs, LTDC_CPSR) & CPSR_CYPOS; 697 vactive_start = reg_read(ldev->regs, LTDC_BPCR) & BPCR_AVBP; 698 vactive_end = reg_read(ldev->regs, LTDC_AWCR) & AWCR_AAH; 699 vtotal = reg_read(ldev->regs, LTDC_TWCR) & TWCR_TOTALH; 700 701 if (line > vactive_end) 702 *vpos = line - vtotal - vactive_start; 703 else 704 *vpos = line - vactive_start; 705 } else { 706 *vpos = 0; 707 } 708 709 *hpos = 0; 710 711 if (etime) 712 *etime = ktime_get(); 713 714 return true; 715 } 716 717 static const struct drm_crtc_funcs ltdc_crtc_funcs = { 718 .destroy = drm_crtc_cleanup, 719 .set_config = drm_atomic_helper_set_config, 720 .page_flip = drm_atomic_helper_page_flip, 721 .reset = drm_atomic_helper_crtc_reset, 722 .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state, 723 .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state, 724 .enable_vblank = ltdc_crtc_enable_vblank, 725 .disable_vblank = ltdc_crtc_disable_vblank, 726 .gamma_set = drm_atomic_helper_legacy_gamma_set, 727 }; 728 729 /* 730 * DRM_PLANE 731 */ 732 733 static int ltdc_plane_atomic_check(struct drm_plane *plane, 734 struct drm_plane_state *state) 735 { 736 struct drm_framebuffer *fb = state->fb; 737 u32 src_w, src_h; 738 739 DRM_DEBUG_DRIVER("\n"); 740 741 if (!fb) 742 return 0; 743 744 /* convert src_ from 16:16 format */ 745 src_w = state->src_w >> 16; 746 src_h = state->src_h >> 16; 747 748 /* Reject scaling */ 749 if (src_w != state->crtc_w || src_h != state->crtc_h) { 750 DRM_ERROR("Scaling is not supported"); 751 return -EINVAL; 752 } 753 754 return 0; 755 } 756 757 static void ltdc_plane_atomic_update(struct drm_plane *plane, 758 struct drm_plane_state *oldstate) 759 { 760 struct ltdc_device *ldev = plane_to_ltdc(plane); 761 struct drm_plane_state *state = plane->state; 762 struct drm_framebuffer *fb = state->fb; 763 u32 lofs = plane->index * LAY_OFS; 764 u32 x0 = state->crtc_x; 765 u32 x1 = state->crtc_x + state->crtc_w - 1; 766 u32 y0 = state->crtc_y; 767 u32 y1 = state->crtc_y + state->crtc_h - 1; 768 u32 src_x, src_y, src_w, src_h; 769 u32 val, pitch_in_bytes, line_length, paddr, ahbp, avbp, bpcr; 770 enum ltdc_pix_fmt pf; 771 772 if (!state->crtc || !fb) { 773 DRM_DEBUG_DRIVER("fb or crtc NULL"); 774 return; 775 } 776 777 /* convert src_ from 16:16 format */ 778 src_x = state->src_x >> 16; 779 src_y = state->src_y >> 16; 780 src_w = state->src_w >> 16; 781 src_h = state->src_h >> 16; 782 783 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", 784 plane->base.id, fb->base.id, 785 src_w, src_h, src_x, src_y, 786 state->crtc_w, state->crtc_h, 787 state->crtc_x, state->crtc_y); 788 789 bpcr = reg_read(ldev->regs, LTDC_BPCR); 790 ahbp = (bpcr & BPCR_AHBP) >> 16; 791 avbp = bpcr & BPCR_AVBP; 792 793 /* Configures the horizontal start and stop position */ 794 val = ((x1 + 1 + ahbp) << 16) + (x0 + 1 + ahbp); 795 reg_update_bits(ldev->regs, LTDC_L1WHPCR + lofs, 796 LXWHPCR_WHSTPOS | LXWHPCR_WHSPPOS, val); 797 798 /* Configures the vertical start and stop position */ 799 val = ((y1 + 1 + avbp) << 16) + (y0 + 1 + avbp); 800 reg_update_bits(ldev->regs, LTDC_L1WVPCR + lofs, 801 LXWVPCR_WVSTPOS | LXWVPCR_WVSPPOS, val); 802 803 /* Specifies the pixel format */ 804 pf = to_ltdc_pixelformat(fb->format->format); 805 for (val = 0; val < NB_PF; val++) 806 if (ldev->caps.pix_fmt_hw[val] == pf) 807 break; 808 809 if (val == NB_PF) { 810 DRM_ERROR("Pixel format %.4s not supported\n", 811 (char *)&fb->format->format); 812 val = 0; /* set by default ARGB 32 bits */ 813 } 814 reg_update_bits(ldev->regs, LTDC_L1PFCR + lofs, LXPFCR_PF, val); 815 816 /* Configures the color frame buffer pitch in bytes & line length */ 817 pitch_in_bytes = fb->pitches[0]; 818 line_length = fb->format->cpp[0] * 819 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; 820 val = ((pitch_in_bytes << 16) | line_length); 821 reg_update_bits(ldev->regs, LTDC_L1CFBLR + lofs, 822 LXCFBLR_CFBLL | LXCFBLR_CFBP, val); 823 824 /* Specifies the constant alpha value */ 825 val = CONSTA_MAX; 826 reg_update_bits(ldev->regs, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); 827 828 /* Specifies the blending factors */ 829 val = BF1_PAXCA | BF2_1PAXCA; 830 if (!fb->format->has_alpha) 831 val = BF1_CA | BF2_1CA; 832 833 /* Manage hw-specific capabilities */ 834 if (ldev->caps.non_alpha_only_l1 && 835 plane->type != DRM_PLANE_TYPE_PRIMARY) 836 val = BF1_PAXCA | BF2_1PAXCA; 837 838 reg_update_bits(ldev->regs, LTDC_L1BFCR + lofs, 839 LXBFCR_BF2 | LXBFCR_BF1, val); 840 841 /* Configures the frame buffer line number */ 842 val = y1 - y0 + 1; 843 reg_update_bits(ldev->regs, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, val); 844 845 /* Sets the FB address */ 846 paddr = (u32)drm_fb_cma_get_gem_addr(fb, state, 0); 847 848 DRM_DEBUG_DRIVER("fb: phys 0x%08x", paddr); 849 reg_write(ldev->regs, LTDC_L1CFBAR + lofs, paddr); 850 851 /* Enable layer and CLUT if needed */ 852 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; 853 val |= LXCR_LEN; 854 reg_update_bits(ldev->regs, LTDC_L1CR + lofs, 855 LXCR_LEN | LXCR_CLUTEN, val); 856 857 ldev->plane_fpsi[plane->index].counter++; 858 859 mutex_lock(&ldev->err_lock); 860 if (ldev->error_status & ISR_FUIF) { 861 DRM_WARN("ltdc fifo underrun: please verify display mode\n"); 862 ldev->error_status &= ~ISR_FUIF; 863 } 864 if (ldev->error_status & ISR_TERRIF) { 865 DRM_WARN("ltdc transfer error\n"); 866 ldev->error_status &= ~ISR_TERRIF; 867 } 868 mutex_unlock(&ldev->err_lock); 869 } 870 871 static void ltdc_plane_atomic_disable(struct drm_plane *plane, 872 struct drm_plane_state *oldstate) 873 { 874 struct ltdc_device *ldev = plane_to_ltdc(plane); 875 u32 lofs = plane->index * LAY_OFS; 876 877 /* disable layer */ 878 reg_clear(ldev->regs, LTDC_L1CR + lofs, LXCR_LEN); 879 880 DRM_DEBUG_DRIVER("CRTC:%d plane:%d\n", 881 oldstate->crtc->base.id, plane->base.id); 882 } 883 884 static void ltdc_plane_atomic_print_state(struct drm_printer *p, 885 const struct drm_plane_state *state) 886 { 887 struct drm_plane *plane = state->plane; 888 struct ltdc_device *ldev = plane_to_ltdc(plane); 889 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; 890 int ms_since_last; 891 ktime_t now; 892 893 now = ktime_get(); 894 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); 895 896 drm_printf(p, "\tuser_updates=%dfps\n", 897 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); 898 899 fpsi->last_timestamp = now; 900 fpsi->counter = 0; 901 } 902 903 static bool ltdc_plane_format_mod_supported(struct drm_plane *plane, 904 u32 format, 905 u64 modifier) 906 { 907 if (modifier == DRM_FORMAT_MOD_LINEAR) 908 return true; 909 910 return false; 911 } 912 913 static const struct drm_plane_funcs ltdc_plane_funcs = { 914 .update_plane = drm_atomic_helper_update_plane, 915 .disable_plane = drm_atomic_helper_disable_plane, 916 .destroy = drm_plane_cleanup, 917 .reset = drm_atomic_helper_plane_reset, 918 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 919 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 920 .atomic_print_state = ltdc_plane_atomic_print_state, 921 .format_mod_supported = ltdc_plane_format_mod_supported, 922 }; 923 924 static const struct drm_plane_helper_funcs ltdc_plane_helper_funcs = { 925 .atomic_check = ltdc_plane_atomic_check, 926 .atomic_update = ltdc_plane_atomic_update, 927 .atomic_disable = ltdc_plane_atomic_disable, 928 }; 929 930 static struct drm_plane *ltdc_plane_create(struct drm_device *ddev, 931 enum drm_plane_type type) 932 { 933 unsigned long possible_crtcs = CRTC_MASK; 934 struct ltdc_device *ldev = ddev->dev_private; 935 struct device *dev = ddev->dev; 936 struct drm_plane *plane; 937 unsigned int i, nb_fmt = 0; 938 u32 formats[NB_PF * 2]; 939 u32 drm_fmt, drm_fmt_no_alpha; 940 const u64 *modifiers = ltdc_format_modifiers; 941 int ret; 942 943 /* Get supported pixel formats */ 944 for (i = 0; i < NB_PF; i++) { 945 drm_fmt = to_drm_pixelformat(ldev->caps.pix_fmt_hw[i]); 946 if (!drm_fmt) 947 continue; 948 formats[nb_fmt++] = drm_fmt; 949 950 /* Add the no-alpha related format if any & supported */ 951 drm_fmt_no_alpha = get_pixelformat_without_alpha(drm_fmt); 952 if (!drm_fmt_no_alpha) 953 continue; 954 955 /* Manage hw-specific capabilities */ 956 if (ldev->caps.non_alpha_only_l1 && 957 type != DRM_PLANE_TYPE_PRIMARY) 958 continue; 959 960 formats[nb_fmt++] = drm_fmt_no_alpha; 961 } 962 963 plane = devm_kzalloc(dev, sizeof(*plane), GFP_KERNEL); 964 if (!plane) 965 return NULL; 966 967 ret = drm_universal_plane_init(ddev, plane, possible_crtcs, 968 <dc_plane_funcs, formats, nb_fmt, 969 modifiers, type, NULL); 970 if (ret < 0) 971 return NULL; 972 973 drm_plane_helper_add(plane, <dc_plane_helper_funcs); 974 975 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); 976 977 return plane; 978 } 979 980 static void ltdc_plane_destroy_all(struct drm_device *ddev) 981 { 982 struct drm_plane *plane, *plane_temp; 983 984 list_for_each_entry_safe(plane, plane_temp, 985 &ddev->mode_config.plane_list, head) 986 drm_plane_cleanup(plane); 987 } 988 989 static int ltdc_crtc_init(struct drm_device *ddev, struct drm_crtc *crtc) 990 { 991 struct ltdc_device *ldev = ddev->dev_private; 992 struct drm_plane *primary, *overlay; 993 unsigned int i; 994 int ret; 995 996 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY); 997 if (!primary) { 998 DRM_ERROR("Can not create primary plane\n"); 999 return -EINVAL; 1000 } 1001 1002 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, 1003 <dc_crtc_funcs, NULL); 1004 if (ret) { 1005 DRM_ERROR("Can not initialize CRTC\n"); 1006 goto cleanup; 1007 } 1008 1009 drm_crtc_helper_add(crtc, <dc_crtc_helper_funcs); 1010 1011 drm_mode_crtc_set_gamma_size(crtc, CLUT_SIZE); 1012 drm_crtc_enable_color_mgmt(crtc, 0, false, CLUT_SIZE); 1013 1014 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); 1015 1016 /* Add planes. Note : the first layer is used by primary plane */ 1017 for (i = 1; i < ldev->caps.nb_layers; i++) { 1018 overlay = ltdc_plane_create(ddev, DRM_PLANE_TYPE_OVERLAY); 1019 if (!overlay) { 1020 ret = -ENOMEM; 1021 DRM_ERROR("Can not create overlay plane %d\n", i); 1022 goto cleanup; 1023 } 1024 } 1025 1026 return 0; 1027 1028 cleanup: 1029 ltdc_plane_destroy_all(ddev); 1030 return ret; 1031 } 1032 1033 /* 1034 * DRM_ENCODER 1035 */ 1036 1037 static const struct drm_encoder_funcs ltdc_encoder_funcs = { 1038 .destroy = drm_encoder_cleanup, 1039 }; 1040 1041 static int ltdc_encoder_init(struct drm_device *ddev, struct drm_bridge *bridge) 1042 { 1043 struct drm_encoder *encoder; 1044 int ret; 1045 1046 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); 1047 if (!encoder) 1048 return -ENOMEM; 1049 1050 encoder->possible_crtcs = CRTC_MASK; 1051 encoder->possible_clones = 0; /* No cloning support */ 1052 1053 drm_encoder_init(ddev, encoder, <dc_encoder_funcs, 1054 DRM_MODE_ENCODER_DPI, NULL); 1055 1056 ret = drm_bridge_attach(encoder, bridge, NULL); 1057 if (ret) { 1058 drm_encoder_cleanup(encoder); 1059 return -EINVAL; 1060 } 1061 1062 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); 1063 1064 return 0; 1065 } 1066 1067 static int ltdc_get_caps(struct drm_device *ddev) 1068 { 1069 struct ltdc_device *ldev = ddev->dev_private; 1070 u32 bus_width_log2, lcr, gc2r; 1071 1072 /* 1073 * at least 1 layer must be managed & the number of layers 1074 * must not exceed LTDC_MAX_LAYER 1075 */ 1076 lcr = reg_read(ldev->regs, LTDC_LCR); 1077 1078 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); 1079 1080 /* set data bus width */ 1081 gc2r = reg_read(ldev->regs, LTDC_GC2R); 1082 bus_width_log2 = (gc2r & GC2R_BW) >> 4; 1083 ldev->caps.bus_width = 8 << bus_width_log2; 1084 ldev->caps.hw_version = reg_read(ldev->regs, LTDC_IDR); 1085 1086 switch (ldev->caps.hw_version) { 1087 case HWVER_10200: 1088 case HWVER_10300: 1089 ldev->caps.reg_ofs = REG_OFS_NONE; 1090 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; 1091 /* 1092 * Hw older versions support non-alpha color formats derived 1093 * from native alpha color formats only on the primary layer. 1094 * For instance, RG16 native format without alpha works fine 1095 * on 2nd layer but XR24 (derived color format from AR24) 1096 * does not work on 2nd layer. 1097 */ 1098 ldev->caps.non_alpha_only_l1 = true; 1099 ldev->caps.pad_max_freq_hz = 90000000; 1100 if (ldev->caps.hw_version == HWVER_10200) 1101 ldev->caps.pad_max_freq_hz = 65000000; 1102 break; 1103 case HWVER_20101: 1104 ldev->caps.reg_ofs = REG_OFS_4; 1105 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; 1106 ldev->caps.non_alpha_only_l1 = false; 1107 ldev->caps.pad_max_freq_hz = 150000000; 1108 break; 1109 default: 1110 return -ENODEV; 1111 } 1112 1113 return 0; 1114 } 1115 1116 void ltdc_suspend(struct drm_device *ddev) 1117 { 1118 struct ltdc_device *ldev = ddev->dev_private; 1119 1120 DRM_DEBUG_DRIVER("\n"); 1121 clk_disable_unprepare(ldev->pixel_clk); 1122 } 1123 1124 int ltdc_resume(struct drm_device *ddev) 1125 { 1126 struct ltdc_device *ldev = ddev->dev_private; 1127 int ret; 1128 1129 DRM_DEBUG_DRIVER("\n"); 1130 1131 ret = clk_prepare_enable(ldev->pixel_clk); 1132 if (ret) { 1133 DRM_ERROR("failed to enable pixel clock (%d)\n", ret); 1134 return ret; 1135 } 1136 1137 return 0; 1138 } 1139 1140 int ltdc_load(struct drm_device *ddev) 1141 { 1142 struct platform_device *pdev = to_platform_device(ddev->dev); 1143 struct ltdc_device *ldev = ddev->dev_private; 1144 struct device *dev = ddev->dev; 1145 struct device_node *np = dev->of_node; 1146 struct drm_bridge *bridge[MAX_ENDPOINTS] = {NULL}; 1147 struct drm_panel *panel[MAX_ENDPOINTS] = {NULL}; 1148 struct drm_crtc *crtc; 1149 struct reset_control *rstc; 1150 struct resource *res; 1151 int irq, ret, i, endpoint_not_ready = -ENODEV; 1152 1153 DRM_DEBUG_DRIVER("\n"); 1154 1155 /* Get endpoints if any */ 1156 for (i = 0; i < MAX_ENDPOINTS; i++) { 1157 ret = drm_of_find_panel_or_bridge(np, 0, i, &panel[i], 1158 &bridge[i]); 1159 1160 /* 1161 * If at least one endpoint is -EPROBE_DEFER, defer probing, 1162 * else if at least one endpoint is ready, continue probing. 1163 */ 1164 if (ret == -EPROBE_DEFER) 1165 return ret; 1166 else if (!ret) 1167 endpoint_not_ready = 0; 1168 } 1169 1170 if (endpoint_not_ready) 1171 return endpoint_not_ready; 1172 1173 rstc = devm_reset_control_get_exclusive(dev, NULL); 1174 1175 mutex_init(&ldev->err_lock); 1176 1177 ldev->pixel_clk = devm_clk_get(dev, "lcd"); 1178 if (IS_ERR(ldev->pixel_clk)) { 1179 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) 1180 DRM_ERROR("Unable to get lcd clock\n"); 1181 return PTR_ERR(ldev->pixel_clk); 1182 } 1183 1184 if (clk_prepare_enable(ldev->pixel_clk)) { 1185 DRM_ERROR("Unable to prepare pixel clock\n"); 1186 return -ENODEV; 1187 } 1188 1189 if (!IS_ERR(rstc)) { 1190 reset_control_assert(rstc); 1191 usleep_range(10, 20); 1192 reset_control_deassert(rstc); 1193 } 1194 1195 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1196 ldev->regs = devm_ioremap_resource(dev, res); 1197 if (IS_ERR(ldev->regs)) { 1198 DRM_ERROR("Unable to get ltdc registers\n"); 1199 ret = PTR_ERR(ldev->regs); 1200 goto err; 1201 } 1202 1203 /* Disable interrupts */ 1204 reg_clear(ldev->regs, LTDC_IER, 1205 IER_LIE | IER_RRIE | IER_FUIE | IER_TERRIE); 1206 1207 for (i = 0; i < MAX_IRQ; i++) { 1208 irq = platform_get_irq(pdev, i); 1209 if (irq == -EPROBE_DEFER) 1210 goto err; 1211 1212 if (irq < 0) 1213 continue; 1214 1215 ret = devm_request_threaded_irq(dev, irq, ltdc_irq, 1216 ltdc_irq_thread, IRQF_ONESHOT, 1217 dev_name(dev), ddev); 1218 if (ret) { 1219 DRM_ERROR("Failed to register LTDC interrupt\n"); 1220 goto err; 1221 } 1222 } 1223 1224 1225 ret = ltdc_get_caps(ddev); 1226 if (ret) { 1227 DRM_ERROR("hardware identifier (0x%08x) not supported!\n", 1228 ldev->caps.hw_version); 1229 goto err; 1230 } 1231 1232 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); 1233 1234 /* Add endpoints panels or bridges if any */ 1235 for (i = 0; i < MAX_ENDPOINTS; i++) { 1236 if (panel[i]) { 1237 bridge[i] = drm_panel_bridge_add(panel[i], 1238 DRM_MODE_CONNECTOR_DPI); 1239 if (IS_ERR(bridge[i])) { 1240 DRM_ERROR("panel-bridge endpoint %d\n", i); 1241 ret = PTR_ERR(bridge[i]); 1242 goto err; 1243 } 1244 } 1245 1246 if (bridge[i]) { 1247 ret = ltdc_encoder_init(ddev, bridge[i]); 1248 if (ret) { 1249 DRM_ERROR("init encoder endpoint %d\n", i); 1250 goto err; 1251 } 1252 } 1253 } 1254 1255 crtc = devm_kzalloc(dev, sizeof(*crtc), GFP_KERNEL); 1256 if (!crtc) { 1257 DRM_ERROR("Failed to allocate crtc\n"); 1258 ret = -ENOMEM; 1259 goto err; 1260 } 1261 1262 ddev->mode_config.allow_fb_modifiers = true; 1263 1264 ret = ltdc_crtc_init(ddev, crtc); 1265 if (ret) { 1266 DRM_ERROR("Failed to init crtc\n"); 1267 goto err; 1268 } 1269 1270 ret = drm_vblank_init(ddev, NB_CRTC); 1271 if (ret) { 1272 DRM_ERROR("Failed calling drm_vblank_init()\n"); 1273 goto err; 1274 } 1275 1276 /* Allow usage of vblank without having to call drm_irq_install */ 1277 ddev->irq_enabled = 1; 1278 1279 clk_disable_unprepare(ldev->pixel_clk); 1280 1281 pm_runtime_enable(ddev->dev); 1282 1283 return 0; 1284 err: 1285 for (i = 0; i < MAX_ENDPOINTS; i++) 1286 drm_panel_bridge_remove(bridge[i]); 1287 1288 clk_disable_unprepare(ldev->pixel_clk); 1289 1290 return ret; 1291 } 1292 1293 void ltdc_unload(struct drm_device *ddev) 1294 { 1295 int i; 1296 1297 DRM_DEBUG_DRIVER("\n"); 1298 1299 for (i = 0; i < MAX_ENDPOINTS; i++) 1300 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); 1301 1302 pm_runtime_disable(ddev->dev); 1303 } 1304 1305 MODULE_AUTHOR("Philippe Cornu <philippe.cornu@st.com>"); 1306 MODULE_AUTHOR("Yannick Fertre <yannick.fertre@st.com>"); 1307 MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>"); 1308 MODULE_AUTHOR("Mickael Reulier <mickael.reulier@st.com>"); 1309 MODULE_DESCRIPTION("STMicroelectronics ST DRM LTDC driver"); 1310 MODULE_LICENSE("GPL v2"); 1311